Automated Validation Framework using On-Chip Event-Driven ...Software code execution flow is defined...

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 16 (2017) pp. 6164-6169

© Research India Publications. http://www.ripublication.com

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Automated Validation Framework using On-Chip Event-Driven Debugger

for Safe Code Execution Control Flow

Hyeonjae Shin1,2

, Jeonghun Cho1 and Daejin Park

1*

Postal: 41566, Daehak-ro 80, Buk-gu, Daegu City, 1School of Electrnoics Engineering, Kyungpook National University,

2LG Electronics, Republic of Korea. 1*

Corresponding Authors

1Orcid: 0000-0002-5560-873X, Scopus Author ID: 55463943600

Abstract

Software code execution flow is defined by user-programmed

code lines with specific safe execution flow conditions. Various

execution control paths under normally safe code executions

exist, so the original programmer has a hard time covering all

kinds of corner cases with the test patterns to validate the safety

of the target software code. This paper proposes an automated

validation framework for safe code execution flow by

specifically adopting an on-chip event-driven on-chip debugger

(OCEVD) for accelerating the test vector generation and

execution for the various sequences of code execution flows.

Instead of using conventional line-based breakpoints to break

code execution at specific lines in the target code, we propose

an event-driven breakpoint concept to trace the collection of

multiple triggered breakpoints using a built-in, hardware-in-

the-loop methodology. The tracer unit collects the skeleton of

the target code access flow with multiple conditions as event

breakpoints (EBKs). The proposed OCEVD is implemented

with hardware unit in the 8051-based microcontroller and

evaluated with the FPGA-based target system, using event-

breakpoint description for DhrystoneTM

benchmark. With

the reduce size of OCD hardware and small operating current,

the proposed approach-based results show that the verification

of the code execution flow can be fully automated without any

conventional line breakpoint.

INTRODUCTION AND MOTIVATION

The system-on-chip (SoC) validation is not easy because the

hardware and embedded software are tightly coupled and

integrated into a single system, as shown in Fig. 1. The

conventional system, which is based on discrete chips,

integrates all kinds of analog and digital components on a

printed circuit board (PCB). The functionality of this system

can be easily monitored by probing the interested contact points

on the target PCB. The components soldered onto the PCB

board are integrated with the internal system bus network on

the SoC chip [1]. Furthermore, the system mode and the

derived output are dependent from the given input, so that the

root causes of the system’s abnormal operations can be easily

estimated.

Figure 1: Complex validation of hardware-software tightly-

coupled SoC

The SoC-based system, which is controlled by the on-chip

software, has more complex conditions to determine the

debugging locations. The software execution results affect the

system mode, causing the transition of the output value. The

SoC validator has to prepare the software test vector to cover

all kinds of state transition sequences, but this iterative vector

preparation is not accurate and requires a large amount of

human effort.



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Figure 2: Static validation approach based on specific hardware or software insertion on the target SoC and OCD-based dynamic

code insertion method

There are three kinds of validation approaches to detecting

abnormal operations caused by the cross-coupled procedures of

the hardware and software execution. First, the functional test,

which is described in Fig. 2(a), emulates the expected input

conditions by forcing the input value on the target system and

compares the output value to whether the expected value is

monitored. It is not easy to prepare various conditions

emulating a real environment, so the fault coverage of

validation code is low.

Second, on-chip SCAN logics, illustrated in Fig. 2(b), are

embedded to validate the accessibility and controllability of on-

chip level-connected circuits. The self-test approach based on

SCAN logic cells requires a large amount of hardware overhead,

and it does not guarantee the dynamic functionality in runtime.

As shown in Fig. 2(c), the third approach to using the on-chip

debugger (OCD) starts with injecting the test code into the

target system during the runtime to emulate the various input

and output conditions under certain circumstances. To enable

the third approach, the system implementer has to integrate the

on-chip debugging unit in the hardware and prepare the

software code area on which the explicit debugging codes are

relocated in the runtime. The hardware unit connected with the

OCD can be controlled with the several commands such as

break, stop, go, continue, and watch.

This approach is too large to implement in a low-cost system

and requires more power consumption to invoke the dedicated

hardware blocks in the debugging mode. Furthermore, it is not

easy to handle various commands to emulate the multiple

execution paths driven by the relocated debugging codes. The

research motivation for this paper is to decrease the hardware

overheads and power consumption during code injection and

its emulation of software code execution using the proposed

OCEVD. The code execution validation using the proposed

OCEVD is automated by generating all kinds of software code

execution paths in the control flow, which are possible during

real operation circumstances.

The remainder of the paper is organized as follows: The related

works are discussed in Section 2, the proposed architecture and

its methods are described in Section 3, the implementation and

evaluation results are shown in Section 4, and conclusions are

presented in Section 5.

RELATED WORKS

The OCD, which is tightly coupled with the main CPU, is a

specifically designed hardware unit that can monitor clock-

accurate system operations. The host-side software, which is

connected with OCD, provides a source view in which the

breakpoint conditions of the expected value or program counter

are allocated. These breakpoints, which are described by the

programmer, are used to inspect a dynamic status from the run-

time system’s execution [2].

Because it is not easy to create an accurate function vector to

cover the various cases of the system’s environment [3], chip

verification in the commercial chip design flow has been

performed with the internal on-chip debugging features which

can interact with the external environment or user commands

[4]. Most digital systems provide OCD; this is tightly coupled

with the main CPU and system bus network. The OCD enables

the on-chip network to be monitored by the external I/O

without any interruption of system operations [5].

The conceptual inspection conditions using conventional OCD

are described with manually user-defined breakpoints, which

are separated at the primitive machine code level. The iterative

breakpoint allocation and inspection of the dynamic system

status through the manual code execution leads to the

complexity of chip-level debugging in embedded systems [6],

in which our original approach had been introduced. The

previous study [7] also presented the hardware-in-the-loop



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technique to trace event-level bus transactions and the

interoperation between the design units [8].

In this study, we propose OCEVD interface, describing pairs of

the variable access conditions and the elapsed time between the

visited functions and implementation the chip-level debugger

hardware. The final goal of this paper is to improve our initial

work in terms of the automation of code validation using the

proposed OCEVD.

Figure 3: Event-driven validation concept

Figure 4: Event-driven bus architecture (reduced transitions)



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Figure 5: Event-driven state control using OCEVD

PROPOSED ARCHITECTURE

Fig. 3 shows our event-driven validation approach. The OCD

interoperates its debugging functions with external discrete-

event models based on discrete-event specifications (DEVS)

[9]. Conventional discrete-timed digital systems perform

clock-triggered state transitions, but our proposed OCEVD acts

as a bridge between the event-driven world and an on-chip

clock-accurate machine. We implemented a state-to-event

converter via a USB interface. Users describe the DEVS

models in the host computer and plug the USB cable into the

target systems through the proposed OCEVD converter. The

circuit-level models are simulated on conventional Verilog

simulator. We extend the capability of the simulation to

interoperate with event-driven DEVS models through a Verilog

Procedure Interface (VPITM

).

To interoperate the digital models with the clock-accurate state

transitions of SoC, which are described in Fig. 4(a), we

modified the on-chip bus architecture using an event-driven

synchronizer and an event tracer to delay the state transitions,

as shown in Fig. 4(b). The conventional OCDs are directly

connected in the bus layer using complex multiplexed data

paths, causing more hardware overhead and power

consumption due to frequent state transitions in the system bus,

as shown in the bus timing diagram in Fig. 4(a).

The proposed OCEVD is indirectly interoperated through the

event tracer unit with the target system. The event tracer

collects the internal bus transitions until the

expected/monitored bus transition patterns are detected, so the

bus transition will be delayed, as shown in the timing diagram

of Fig. 4(b). The OCEVD does not require complex wide-bus

interconnections and multiplexed data paths, as shown in the

red line of Fig. 4(b). The event tracer in Fig. 4(c) is a type of

buffer with dedicated pattern comparators, which perform the

event collection without any CPU or software execution (Fig.

4(d)).

The CPU traverses the code execution flow, as described in the

user-programmed embedded software in Fig. 5(a). The OCD

software in the host side allocates the user-defined breakpoints

at the source level, and chip-level OCD hardware continuously

reports the control flow to the host. If the pre-defined

conditions are matched to breakpoints, the control flow is

transferred to the OCD unit to open the diagnosis functionality

to the user side in Fig. 5(b).

The EBK in the proposed OCEVD unit describes the expected

code access properties in the storage region, such as variables,

and the elapsed time between the accessed regions with the

following definition:

(1)

,where value condition (VC) is described by a pair of the access

values (av) and the access functions (af), and et is elapsed time

since the previous access event break.

The programmer allocates the EBK into the OCEVD to

construct the access graph of the CPU software execution flow.

The following equation describes an example of a user-defined

EBK and its tracer operations. The eb2 breakpoints explicitly

describe an invalid dangled node to trace the abnormal access

diagnosis.

The OCEVD unit automates the condition comparison and

sequential operations of the next expected breakpoint

determination until the kth final node tebk of the expected

access graph is reached in Fig. 5(c). We define ⨀ operation as

event-driven debugging to extract a code execution flow

diagnosis for the n-byte firmware code[1:N] of the target CPU

with the following equation.



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TEV={teb0,.,tebk}=OCEVD(EBK)⨀CPU(code[1:n])

(3)

If the expected condition of the next breakpoint is different with

the monitored state transition in kth breakpoint, the single

snapshot CPU executions is traced into the tracer buffer to

report the inspected diagnosis as a traced vector TEV to the

host side. These procedures will be automated during the entire

code execution control flows using our proposed OCEVD-

based validation approach. The conventional approach may

require large overhead on writing the validation code, preparing

the code injection and invoking the debugger. Slow debugging

is also big drawback to using code injection-based validation.

Our approach reduces these disadvantages of OCD-based

validation.

IMPLEMENTATION RESULT

We implemented an OCEVD-controlled microcontroller,

which is connected with OCEVD interoperable host machine,

which can interoperate with event-driven models. The OCEVD

generates various code execution sequences and automates the

code injections and comparisons of the derived outputs for fast

validation, which is demonstrated in Fig. 6(a).

The proposed OCEVD unit is implemented using synthesizable

Verilog RTL with custom-designed tracer, monitor, and

condition matcher, which are tightly integrated with the 8051

microcontroller in Fig. 6(a). The implemented OCEVD

hardware data-path requires additional 4,500 logic gates and

1K SRAM tracer buffer to hold the inspected diagnosis, which

is compared with the 5,500 gates of original OCD. Fig. 6(b)

summarizes the total area cost by considering the power block,

power routing area, and analog circuits.

The code execution verification by describing the featured

breakpoints in DhrystoneTM could be fully automated

without any iteration of the code break, and inspection in detail

and diagnosis analysis.

CONCLUSION

The SoC-based systems requires complex and powerful

validation methods for high-fault coverage. The OCD-based

code injection method has been adopted to increase the

validation capability, but it requires a large hardware cost to

compare the internal data transition through bus-level

interconnections. This paper introduces the discrete event-

based bus architecture to reduce the gate counts and number of

state transitions of the bus comparators and multiplexed data

paths for OCD function. The proposed OCEVD, which is based

on the control flow detection by the event-breakpoints instead

of line-by-line breakpoints, is successfully implemented on the

extended microcontroller architecture and enables a fully

automated code-debugging interface by extracting the code

execution flow for multiple inspection conditions.

Figure 6: Event-driven validation automation using OCEVD and required cost (hardware and energy)



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Conflict of Interest

The authors declare that there is no conflict of interest regarding

the publication of this paper.

ACKNOWLEDGMENT

This research was supported by the Basic Science Research

Program through the National Research Foundation of

Korea(NRF) funded by the Ministry of Education

(2014R1A6A3A04059410 and 2016R1D1A1B03934343).

Corresponding author is Daejin Park ([email protected]).

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