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Architectures for Packet Classification

CachingAuthor: Kang Li, Francis Chang, Wu-chang FengPublisher: INCON 2003Presenter: Yun-Yan ChangDate:2010/11/03

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Introduction Approach Cache Architecture Evaluation

Outline

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Given a limited silicon resources, what is the best way to implement a packet classification cache?

Determine how to best use the limited resource in three aspects:◦ Cache’s associativity◦ Replacement policy◦ Hash function

Introduction

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The method used to evaluate the performance of cache is to use trace-driven simulations.

◦ Packet Classification Cache Simulator (PCCS)

◦ Trace data set Bell Labs New Zealand University (OC-3 link)

Approach

Fig 1. Flow volume in traces

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The cache memory is an N-way set associative cache, which splits the cache memory into N memory banks.

Each memory bank is a directly mapped cache that is addressable by the output of the hash function.

Cache Architecture

Fig 2. Cache Architecture

m: Flow-ID sizek: result sizeN: set associative cache

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For an N-way set associative cache, every input FlowID selects N memory entries from each memory bank.

Each entry contains an m-bit FlowID and a k-bit classification result.

Classification result is at least 1 bit for a packet filter, but could be multiple bits.

Cache Architecture

Fig 2. Cache Architecture

m: Flow-ID sizek: result sizeN: set associative cache

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Cache associativity◦ Focus on storage costs on cache.

Direct-mapped N-way associative Fully associative

Evaluation

Fig 3. Cache associativity

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Cache replacement◦ Determines which entry must be replaced in order

to make room for a newly classified flow. LRU (Least-Recently-Used) replacement LFU (Least-Frequency-Used) replacement Probabilistic replacement

Algorithm:

Evaluation

update(state) if (state == 0)

h = alpha * h; else

h = alpha * h + (1 - alpha);

alpha = 0.9h: recent hit ratio

Upon cache miss: update(0) // replace entry with probability hUpon hit miss: update(1)

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◦ Performance of different cache replacement algorithms using a 4-way associative cache

Evaluation

Fig. 5. Replacement policies using 4-way caches

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Hash function◦ A critical component to implementing a cache is the

hash function used to index into it.

◦ Traditional hash function, such as SHA-1 hash function, the generation output takes more than 1000 logic operations (Shift, AND, OR, and XOR) using 32-bit word.

◦ To reduce the size of hash function and the latency, we design a XOR-based hash function operates on the packet header, and consumes only 16 logic operations (XOR and Shift).

Evaluation

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Evaluation

Fig 6. XOR-based hash function (needs 16 logic operations)

SHA-1 hash function(needs more than 1000 logic operations)

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◦ Compare the performance with 4-way associative LRU cache. The performance of XOR-based hash function is almost equal to the SHA-1 hash function.

Evaluation

Fig. 7. Hash performance using 4-way, LRU cache.