August 2008 Hi-Rel Operations 2010. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL ©...

August 2008

Hi-Rel Operations2010

August 2008

NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL© 2008 National Semiconductor Corporation. All Rights Reserved.

National – A Global Company

Taiwan

China

India

Finland

GermanySouth Portland, MEJapan

Malaysia

NetherlandsScotland

Santa Clara, CA

Estonia

Korea

– Santa Clara, Ca USA– Melaka, Malaysia

– South Portland, Maine USA– Greenock, Scotland

Regional Business Divisions

Wafer Fabs

Assembly Plants

– Americas– Europe

– United States (15)– Scotland– The Netherlands– Germany– Italy– India

World Headquarters

– Santa Clara, California, US

Design Centers

– China– Taiwan – Japan– Finland– Estonia– Korea

– Japan– Asia Pacific

Italy

August 2008


World-Class Manufacturing Our Strategic Asset

• Greenock, Scotland – 6in– Leading-edge analog Bipolar, BiCmos + Dmos,

CMOS processes

• South Portland, Maine – 8in– Advanced CMOS /

BiCMOS (SiGe and SOI) processes – Running advanced analog– US Secure Foundry

• Santa Clara, USA and Melaka, Malaysia – Custom Hermetic Package Design– Test & Assembly

August 2008

Hi Rel Operations

August 2008


National Semiconductor – A Rich Space Analog Portfolio

Analog Building BlocksAnalog Building Blocks QMLV Qualified ProductsQMLV Qualified Products

• State of the art radiation tolerant process technology (ELDRS Free)State of the art radiation tolerant process technology (ELDRS Free)

• Industry leading hermetic package technologyIndustry leading hermetic package technology

• Renewed focus on Technology Driven Analog SolutionRenewed focus on Technology Driven Analog Solution• Radiation Testing: SEL, SEU & TID ReportsRadiation Testing: SEL, SEU & TID Reports

30+ Years in the Space Market

August 2008


Hi-Rel Operations Customer Support and Documentation

• Ceramic Eval Boards• Radiation Reports

TID SEU/SET SEL

• Customer Communications

– Quarterly News Letter

– Customer Portals

– Hi-Rel Web Sitewww.national.com/space

National SemiconductorHi-Rel Operations Radiation Engineering/RHA Programs

2900 Semiconductor DriveSanta Clara, CA 95052

Single Event Effect Report

Micro Power12 b Digital to Analog Converter

DAC121S101WGMLSDAC121S101WGRQV(5962R0722601VZA)

Date: November 17, 2008Rev: B

Principle Investigator and Editor: Kirby Kruckmeyer+1 (408) [email protected]

Written By: Sandeepan DasGupta (Product Engineer Intern)

ADC08D1520CVAL

ADC14155HCVALADC14155LCVAL

ADC10D1000CVAL

LM98640CVAL

August 2008


Die Products at National

• WAFER– Whole wafers

in vials

• DICED– Waffle Pack– GEL-PAK®

– Tape on Reel– Wafer on

film frame

• Die Products contact– See web site for

information

• Web– www.national.com/die

August 2008


Hi-Rel Focused Satellite Strategy

ELDRS AOCS Communication Space Imaging Power

Work with our customers to help solve system challenges by developing leading edge Analog Solutions enabling innovative and successful missions.

1. Enhanced Heritage Products2. Aggressively pursue the satellite market with high

performance fully QMLV qualified analog products

Wide Band

Narrow Band

August 2008


What is ELDRS and Why is It Important?

• Many bipolar linear circuits are used in space systems and many suffer from ELDRS

• System performance may be degraded by ELDRS

• It is hard to identify system malfunctions related to ELDRS

– “Failures” are usually parametric and not functional

– Design margins are often high

– Circuits are often not “suspect” if they passed ground test at HDR

• ELDRS has been demonstrated in space (See papers from NSREC & RADECS)

Enhanced Low Dose Rate Sensitivity: An increase degradation in electrical performance between low dose rate and high dose rate.

High and Low Dose Rate Improvements- legacy Portfolio

August 2008


• We test them so you don’t have to!

• Every wafer tested and qualified at low dose rates

– per Mil-Std-883 method 1019 condition A&D– Low dose rate of 10 mrad/s (36 rad/hr)– Biased and unbiased

• DSCC unique low dose rate certified part numbers

• ELDRS Free Products LM111 LM117 LM124 LM136-2.5LM139 LM158 LM193 LM7171

LM119 LM2941 LMP2012

• Low Dose Rate Qualified LM117HV

•Products in Qualification LM101 LM137 LM113 LM2940

ELDRS-Free Products!

ELDRS-Free LM139

Also available in die form

August 2008


• Radiation process developed to improve total dose performance

– LM137 10krad 30krad

– LF411 10krad 50krad








– LM117HV 3krad 100krad

– LP2953 10krad In Progress

High Dose Rate Improvements - on Legacy Products

Continue to work on radiation performance for existing devices

Before Today

August 2008


Hi-Rel Focused New Product Development

Applications AOCS Power CommunicationSpace Imaging

System FunctionMaintain or Change

OrbitPayload & Bus

Backbone of Communications Market

Integral in National Security and Tracking

System Requirements

Lower Power, Increase Precision

Higher Efficiency, <1.2V, Faster Response Time, High Currents

Higher Bandwidth, Lower Noise Power Ratio, Lower Power

Lower Power, Higher Resolution, More Integration

Products Developed

1 MSPS ADC & DACs

Precision Amps

LDOSHigh Speed & Giga Sample

ADCsLow Power Analog

Front Ends

August 2008


ADC128S102WGRQV - QMLV Available today!

8-Channel, 12-Bit, 50 KSPS to 1MSPS, General Purpose ADC

– Only 2.3mW of Power

• 0.06 uW in Power Down

– Eight Input Channels

– DNL – -0.2 to +0.4 LSB typical

– INL – +/- 0.4 LSB typical

– Split Supplies

• VA 2.7V to 5.25V

• VD 2.7V to VA

– SPI Digital Output

– 16ld Gull Wing Ceramic Cerpac

– Space Level Version

• TID of 100 krad(Si)

• Single Event Latchup > 120 MeV

– Order as 5962R0722701VZA

50 KSPS 1 MSPS

August 2008


ADC128S102WGRQV Specifications

SPECIFICATION ADC128S102WGRQVResolution 12 bits

Input Channels 8Sampling Rate 50 KSPS to 1MSPSVoltage Supply +2.7V to +5.25V

Input Range 0 to VA

Reference InternalOutput Data Format SPI, QSPI, Microwire, DSP Interfaces

Guaranteed No Missing Codes 4096 Codes

DNL -0.7 to + 0.9 LSB (max)

@VA=VD=3.0V

INL +/- 1.0 LSB (max) @VA=VD=3.0V

SNR 73 dB (typ)SINAD 73 dB (typ)ENOB 11.8 bits (typ)THD -90 dB (typ)

SFDR 92 dB (typ)Offset Error +/-2.3 LSB (max)

Gain Error +/- 2.0 LSB (max)

• Std Ceramic package WG16A

• 8 Channels in only 16 pins– Reduces board space

and weight– Reduces PCB traces

and cabling

August 2008


DAC121S101WGRQV - QMLV Available Now!

12-Bit Micro Power General Purpose DAC with Rail-to-Rail Output

010100110100110010110011010101001101001

1001011001101010100110100110010110011010101001101001

1001011001101

Vcc

Gnd

DinSclkSnyc

Vout

– Only 0.64mW of Power• 0.14 uW in Power Down

– Supply range of +2.7V to +5.5V

– Guaranteed Monotonic

– DNL +0.25/-0.15 LSB

– 3-wire 20MHz SPI Digital Interface

– Settling Time 12μS– Hermetic 10ld Gull Wing Ceramic Cerpac




– Order as 5962R0722601VZA

August 2008


DAC121S101WGRQV Specifications

SPECIFICATION DAC121S101WGRQVResolution 12 bits

Input Data Format SPI, QSPI, Microwire, DSP InterfaceInput Rate 20 MHz

Voltage Supply Range +2.7V to +5.5VOutput Range Rail-to-Rail

Reference InternalDNL -0.15 to + 0.25 LSB (max)

Output Settling Time 12 us

Full-Scale Error -0.06 %FSR (max)

Gain Error -0.10 %FSR

• Std Ceramic package WG10A

• Serial interface

– Allows for small 10 pin package

– Reduces package footprint and weight

– Reduces PCB traces and cabling

August 2008


LMP2012WGLQMLV -

Dual Channel, High Precision, Rail-to-Rail Output Op Amp

– Very Low TCVOS – 0.015uV/°C

– Low Input offset voltage of 60 μV over time and temperature.

– No 1/f noise - input-referred voltage noise of 35 nV/ Hz

– Low supply current – 920uA

– Wide gain bandwidth – 3MHz

– 2.7 to 5.0V supply voltage range

– High CMRR – 130 dB

– High PSRR – 120 dB

– Hermetic 10-pin ceramic gullwing flat package

– Space Level version• TID of 50 krad(Si)

• ELDRS qualified to 50 krad(Si)

• Low SET Cross-Section

– Order as 5962L062061VZA

QMLV Available!

August 2008


No 1/f Noise

Input-Referred Voltage Noise of 35 nV/ Hz

August 2008


Offset Voltage - Over Supply and Temperature

August 2008


LM2941QML ELDRs Free 1A LDO

• Features– 1A Adjustable Regulator

– Adjustable Output Voltage 5V-20V

– Input Voltage up to 26V

– Input protection up to -15V

– Drop Out Voltage 0.5V

– Quiescent Current 10mA

– On / Off Pin

– Internal short circuit current protection

– ELDRs Free up to 100krad/si

Available!

August 2008


ADC14155 - Space Qualified Available Today!

14-bit 155 MSPS ADC

– Input bandwidth of 1.1GHz

– 11.3 ENOBs at fin=70 MHz, 11 ENOBs at fin=169MHz

– SNR of 70.1 dB at fin=70 MHz, 68.5 dB at fin=169MHz

– SFDR of 82.3 dB at fin=70 MHz, 80.5 dB at fin=169MHz

– Power Consumption of 967mW at 155 MSPS

– Guaranteed no missing codes

– Dual 1.8V and 3.3V operation

– In 48 pin Hermetic Ceramic Quad Flat Pack




PLLV

CO

BPF LMH6517 ADC14155

BPF LMH6517 ADC14155RF

August 2008


National vs. Competition

Part ADC14155QML XXXX XXXXResolution (bits) 14 14 14Speed (MSPS) 155 105 80Power Consumption 967mW 1.9W 1.75WENOB (Bits) 11.5 10.2 10.1SNR (dB) 69 at 240 MHz 63 at 230 MHz 72 at 200 MHzSFDR (dB) 77 at 240 MHz 64 at 230 MHz 63.5 at 200 MHzAnalog BW 1.1 GHz 570 MHz 270 MHzSEL SEL >120MeV SEL>60MeV

August 2008


ADC14155 ENOB vs. Temperature

10.500

10.700

10.900

11.100

11.300

11.500

11.700

11.900

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature deg. C

EN

OB

(b

its

)

socketed device Fs=100MHz, Fin=70MHz, ENOB

soldered device Fs=100MHz, Fin=70MHz, ENOB

August 2008


ADC14155 SFDR vs. Temperature

60.000

65.000

70.000

75.000

80.000

85.000

90.000

95.000

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature deg. C

SF

DR

(d

BF

S)

socketed device Fs=100MHz, Fin=70MHz, SFDR

soldered device Fs=100MHz, Fin=70MHz, SFDR

August 2008


ADC14155 SINAD vs. Temperature

65.000

66.000

67.000

68.000

69.000

70.000

71.000

72.000

73.000

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature deg. C

SIN

AD

(d

BF

S)

socketed device Fs=100MHz, Fin=70MHz, SINAD

soldered device Fs=100MHz, Fin=70MHz, SINAD

August 2008


ADC14155 Power vs. Sampling Rate

ADC14155 Power vs. Sampling Rate

y = 1.4916x + 704.39

700

750

800

850

900

950

1000

30 40 50 60 70 80 90 100 110 120 130 140 150 160

Sampling Rate (MSPS)

Po

wer

(m

W)

August 2008


• Dual Channel 8-Bit 1.5 GSPS ADC, Single 8-bit 3 GSPS ADC

ADC08D1520WGFQV - QMLV Available!

– Max sampling frequency 1.7GSPS– Inputs may be interleaved to obtain a 3GSPS

single ADC– Input bandwidth of 2 GHz– 7.2 ENOBs out to Nyquist– Lowest Power in the industry at 1 W per channel

at 1.5 GSPS from single 1.9V supply– Very low cross-talk (-66 dB @ 1160 MHz)– Low-noise deMUX’d LVDS outputs– Guaranteed no missing codes– In 128 pin Hermetic Ceramic Quad Flat Pack – Space Level Version

• TID of 300 krad(Si)• Single Event Latchup > 120 Mev

– Order as 5962F0721401VZC

August 2008


128-Lead Ceramic Quad (Gold Lead Finish)NS Package Number EL128A

August 2008


ADC08D1520WGFQV ENOB vs. Clock Freq,

Input Frequency 248.47MHz versus Temperature.

2

3

4

5

6

7

8

-100 100 300 500 700 900 1100 1300 1500 1700 1900 2100

Clock Frequency (MHz)

EN

OB

Bench @ Room and Hot

HotRoom

August 2008


Bench FFT , Sample Rate = 1500Mhz , Input 397.47MHz I Channel

August 2008



August 2008


7

7.2

7.4

7.6

7.8

25 35 45 55 65 75 85

Ambient Temperature ('C)

EN

OB

1.0 GSPS Clk +1.0dBm, 247.97Mhz +3.6dBm I/F Non-SPI Mode,FS=1(870mV pk-pk) Note: The Input Amplitude is held constant over

the temperature range.

Key Points: Key Points: Calibration was performed only Calibration was performed only upon Pwr up.upon Pwr up. Then Cal was performed Then Cal was performed again after last temperature sweep.again after last temperature sweep.

Calibration performed at every Temperature Calibration performed at every Temperature Change.Change.

Dynamic vs. TemperatureADC08D1520WGFQV with and without Cal

August 2008


GiG Evaluation SystemGiG Evaluation System- Enable complete system demo for customers- Enable complete system demo for customers

• NSC’s ceramic evaluation board interfaces to a PC through the USB interface.

• National uses a Xilinx Virtex-4 processor for the data capture.• National also supplies the wavevision software for data analysis.

August 2008


ADC10D1000QML - Space Qualified Available Today!

Dual Channel 10-Bit 1GSPS ADC, Single 10-bit 2 GSPS ADC– Full Power Bandwidth of 2.8 GHz

– 9.0 ENOBs @ Fin 249MHz Fs – 1.0GHz

8.9 ENOBs @ Fin 498MHz Fs – 1.0GHz

– 56.1dBc SNR @ Fin 249HMz Fs- 1.0GHz

56.8dBc SNR @ Fin 498HMz Fs- 1.0GHz

– 62.1dBc SFDR @ Fin 249MHz Fs – 1.0GHz

62dBc SFDR @ Fin 498MHz Fs – 1.0GHz

– Lowest Power in the industry at 1.45 W per channel at 1GSPS from single 1.9V supply

– Inputs may be interleaved to obtain a 2 GSPS single ADC

– Very low cross-talk (-61 dB @ 497 MHz)

– Low-noise deMUX’d LVDS outputs

– Guaranteed no missing codes

– In 376 pin Hermetic Ceramic Column Grid Array Package

– Space Level Version• TID of 100 krad(Si)


August 2008


National vs. Competition

Part ADC10D1000QML XXXXXXResolution (bits) 10 12Number of Channels 2 1Sample Rate 1 GSPS, 2GSPS 500 MSPSSupply 1.9V 5V & 3.3VDNL +/-0.2 LSB +/-1 LSBPower/Channel 1.45W 2.2WFull Power Bandwidth 2.8 GHz 1GHzSingle Event Latchup SEL >120MeV SEL ~63MeV

August 2008


Simplified Functional Block Diagram

August 2008


ENOB vs. Fin

6.66.97.27.57.88.18.48.7

99.39.6

90 290 490 690 890 1090 1290 1490 1690 1890 2090

Input Frequency

EN

OB

I Chan, Ceramic Package @ room, Fclk = 1 GHzQChan, Ceramic Package @ room Fclk = 1 GHz

August 2008

35

40

45

50

55

60

65

70

75

80

90 290 490 690 890 1090 1290 1490 1690 1890 2090

Input Frequency

SFD

R (d

B)

I and Q Channel (dBc).

I Chan, Ceramic Package @ room Fclk = 1 GHzQChan, Ceramic Package @ room Fclk = 1 GHz

SFDR vs. Fin

August 2008


NPR vs. Notch Width

• The NPR was measured at each notch width and the average is shown.

• At fc,notch = 320MHz, f=250MHz is never included for all notch widths.

• The measurement stabilizes after about 4%, so a 5% notch width (25MHz, ~750 bins) was chosen for most measurements.

• After 10%, the NPR begins to degrade.

NPR vs. Notch Width

47.00

47.50

48.00

48.50

49.00

0 5 10 15

Width [%]

NP

R [d

B]

NPR

August 2008


ADC10D1000QML Power

• Power vs Clock Frequency @ Room

1.1

1.4

1.3

1.2

1.5

1.6

1.9

1.8

1.7

Sample Rate (MSPS)

Po

wer

/Ch

ann

el (

W)

ADC10D1000QML

August 2008


ADC10D1000QML ENOB vs. fCLK

I Channel, LFS = Low I Channel, LFS = High

Writing the LFS bit High improves performance at fCLK = 100 MHz. LFS doubles the charge pump frequency improving performance with low fCLK.

August 2008


ADC10D1000QML Auto-Sync Feature

• The ADC10D1000QML has an auto-sync mode for continuous synchronization of an arbitrary number of ADCs in a system

• A Master-Slave configuration for the subdivision of the converter clock, CLK, to the slower DCLK output is used

D1<1:10>

D2<1:10>

DCLK

CLK

VIN

TDCLK =4 x TCLK

TCLK

ADC #4

RCLK_IN

RCLK1 RCLK2

AutoSync

D1<1:10>

D2<1:10>

DCLK

CLK

VIN

ADC #2

RCLK_IN

RCLK1 RCLK2

AutoSync

to ADC #5

to ADC #8 to ADC #9

from ADC #1(Master)

August 2008


376 Column Grid Array Package

August 2008


Columns from 6Sigma

• Column Core Material: 80Pb/20Sn• Column Diameter: 20mils• Column Height: 87mils• Column Core wrapped with Copper Ribbon

and eutectic solder coating of 37Pb/63Sn

Copper Ribbon

August 2008


National’s 376 Column Grid Array - Temperature Cycle Board

• Experiment between standard 80Pb/20Sn Copper Ribbon Columns

• Daisy Chain Test Chip

10Min Dwell

10Min Dwell

36°C/Min

125°C

-55°C

Time

1.5min 11.5min

13min0°C

16.5min 26.5min

30min

August 2008


ADC10D1000 Reinforced Copper Columns after 3000cycles

3000 cycles 80Pb/20Sn 3000 cycles 80Pb/20Sn

3000 cycles 80Pb/20Sn3000 cycles 80Pb/20Sn

August 2008


ADC10D1000 SEE Testing Results

• No SEL up to 120MeV

• No SEFI up to 120MeV

• SEU for DCLK– Outage Time: 0.02ps/month– Clock Upsets: 2.2X10-5 events/month– Longest Event: typically 1 clock cycle

• SEU Code Error Rate– Outage Time: 0.1ns/ch/month– Data Upsets: 1.8X10-3

events/ch/month– Longest Event: 55ns

August 2008


Weibull Plots for DCLK

August 2008


Weibull Plot for Code Error / Channel

August 2008


58

August 2008 Hi-Rel Operations 2010. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL ©...

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