ATE Signal Integrity Challenges for Multi- Gigabit...
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ATE Signal Integrity Challenges for Multi- Gigabit Communication Interfaces Heidi Barnes Jose Moreira Verigy 25 April 2008
Transcript of ATE Signal Integrity Challenges for Multi- Gigabit...
ATE Signal Integrity Challenges for Multi-Gigabit Communication Interfaces
Heidi BarnesJose Moreira
Verigy25 April 2008
Latest Work on Signal Integrity for
DUT Loadboard Design
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IC Specs@ DUT I/O
ATE Specs@ Pogo PinsPin Electronics
DUT Board TraceCoaxial Signal PathDriver DUT
Rogers 435019 mil trace width
18.8cm length
The Challenge
Pogo
DUT I/O
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Knowledge GAP
System Board Design DUT Board Design
The objective is to provide a medium of communication between the different board IC’s that guarantees functionality
The objective is to deliver the DUT outputs to the ATE pin electronics with minimum distortion
≠
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•Skin effect and dielectric Loss are the dominant loss factors on a DUT loadboard.
DUT Loadboard Loss Factors
SKIN EFFECT
DIELECTRIC LOSS
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At high frequencies, current flows predominantly near the surface of a conductor
Reduced usable area ⇒ higher resistance
Skin depth proportional to
Approximately: 0.2 mm at 100 kHz2 µm at 1 GHz
Depends on geometry but not on dielectric materials
f
Skin Effect
f1
DC RF Current Flow in Red
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Trace Width vs Trace Length
FREQUENCY , GHz
INSE
RTI
ON
LO
SS S
21, d
B
INSERTION LOSS COMPARISON, STRIPLINE IN FR4
50% Increasein Trace Width
Starting Design
30% Reductionin Length
Reduce LengthAnd Increase Trace Width
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Dielectric Loss Simulation/Measurements
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THE CHALLENGE IS NOT THAT THERE IS LOSS, IS THAT THE LOSS IS FREQUENCY DEPENDENT!!!
Effects of Loss in Time/Frequency
Transitions.. “the killer loss at high
data rates”
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The Ideal World
Oliver Heaviside1850-1925
Voltages and Currents are changing with Time and Distance (Magnitude and Phase)
• Create a simple model of a transmission line.
• Utilize calculus to analyze the model when summing a series of incremental length sections.
For small R and G Sinusoidal Input Resulting Relationships
Telegrapher’s Equations
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Demonstration of Impedance Mismatch Losses
1 2 3 4 5 6 7 8 90 10
-4
-3
-2
-1
-5
0
freq, GHz
dB(P
erfe
ct_M
atch
_21m
il..S
(2,1
))dB
(Sin
gle_
C_2
1mil.
.S(2
,1))
dB(S
ingl
e_C
LC_2
1mil.
.S(2
,1))
MICROSTRIP TRANSMISSION LINE DISCONTINUITY EXAMPLE
NO DISCONTINUITY (50 OHM MATCHED IMPEDANCE)
CAPACITIVE DISCONTINUITY (50 OHM MATCHED IMPEDANCE)
L-C-L FILTER DISCONTINUITY (50 OHM MATCHED IMPEDANCE)
MICROSTRIP
C
L-C-L
INSE
RTI
ON
LO
SS S
21 (d
B)
FREQUENCY (GHz)
AGILENT ADS SIMULATION
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Demonstration of the Effects of a Bad Via DesignNon-OptimizedOptimized
3.25Gb/s with a PRBS31 Pattern
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Performance ComparisonFrequency response
Pogo Pins
PCB Layers
Air
AirMicrostripTransmission Line
KV/m34
6
0Pogo Pins
PCB Layers
Air
AirMicrostripTransmission Line
KV/m34
6
0
Pogo Pins
PCB Layers
Air
AirMicrostripTransmission Line KV/m
34
6
0Pogo Pins
PCB Layers
Air
AirMicrostripTransmission Line KV/m
34
6
0
High-Speed Pogo Via Design
Ultra High-Speed Pogo Via Design
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V93000 Pogo Via DesignHigh Speed Pogo Via Ultra-High Speed Pogo Via
Ground Vias 100 mils from Signal Via Ground Vias 40 mils from Signal Via
Port 2
Port 1 Port 1
Port 2
STIMULUS 10Gbps ROGERS4350 and 4450BTaconic TSM29 and FastRise27Experimental Results
STIMULUS 43Gbps ROGERS4350 and 4450BTaconic TSM29 and FastRise27Experimental Results
Relays For Multi-Gigabit ATE BIST Applications
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Relays for BIST and ATE Lowspeed
ATE LOW SPEED PIN ELECTRONICS FOR DC AND SCAN MEASUREMENTS
DUT I/O CELL
TX
RX
WIRE LOOPBACK SCAN AND DC
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Parametric Loopback with Jitter Injection
IMPLEMENTATION EXAMPLE ON AN ATE CARD
Relays on the ATE Pin Electronics
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Evaluation with NAIS Relay
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Footprint Optimization
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Data Eye Comparison
WITHOUT RELAY WITH RELAY
DATA EYE AT 10Gb/s WITH A PRBS7 PATTERN USING THE VERIGY V93000 PINSCALE HX ATE CARD
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SRF300 Gullwing signal pins and single center ground pin:Strong package resonance around 4GHz… depends on height above PCB.
4GHz Resonance
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Modified SRF300 with improved grounding under the package:Package resonance moved past 12GHz, and lower losses at 10GHz.
Ground Block
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Teledyne RF300 Relay Grounding ModificationsThru Path (0V on Relay)
GRF303SMT
SGRF303Gull Wing
10Gbps , PRBS 2^9-1, 20pS Rise Time
SRF303-XGull Wing
Performance-at-the-DUT: Probe Measurements for Multi-Gigabits
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What Signal Reaches the DUT?
ATE Signal Source
ATE Test Fixture
DUT ReceiverWith SocketNo Socket
ATE Pin Electronics
DUT
*Simulated example of what one might expect from measurements.
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OBJECTIVES
•Develop equipment and techniques to measure the performance of the DUT loadboard on a bench setup without having to access to a Verigy V93000 system.
•This allows the verification of the DUT Loadboard and the socket without a working application with the accuracy provided by instruments like a vector network analyzer (VNA).
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Focus Calibration Techniques“Performance-at-the-DUT”
BENCH CHARACTERIZATION
ATE CHARACTERIZATION
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Probing the Loadboard Signal Path
50 ohm Coaxial Probe Tip
Gnd
Gnd
Sig
Loadboard
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VNA Non-Insertable Calibration
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Methods for removing the measurement cables, connectors, probes, and interposer adapters from the Network Analyzer S-Parameter measurements.
* Reference DesignCon 2007 Paper:“Differential PCB Structures using Measured TRL Calibration and Simulated Structure De-Embedding ”
Custom Calibration – PCB Reference Plane
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Reference Plane Adjustment –De-embedding the Probe and Interposer
NIST Traceable Coaxial Calibration with Probe Interposer Adapter De-Embedding provides for robust data collection.
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Calibration Reference Plane Issues
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Reference Planes on the ATE Test Fixture
Test FixtureReference Plane
DUT BGA
ATE Test Fixture
DUT Socket
DUT BGAReference Plane
Pogo Pin Connector
ATE Pin Electronics
ATE Pin ElectronicsReference Plane
Typical Reference Planes
Test FixtureReference Plane
DUT BGA
ATE Test Fixture
DUT Socket
DUT BGAReference Plane
Pogo Pin Connector
ATE Pin Electronics
ATE Pin ElectronicsReference Plane
Reference Planes for Cascading
DUT Socket ?Reference Plane
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Some Textbook References on Signal Integrity
•Eric Bogatin, “Signal Integrity Simplified”http://www.bethesignal.com/bogatin/index.php
•Howard Johnson “High Speed Digital Design”http://www.sigcon.com/
•Lee Ritchie “Right the First Time”http://www.speedingedge.com/
Thank You
