AT89C52 Micro Controller

7/27/2019 AT89C52 Micro Controller

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Features • Compatible with MCS-51™ Products

• 8K Bytes of !-System "epro#rammable Flash Memory

• $!dura!ce% 1&''' (rite)$rase Cycles

• Fully Static *peratio!% ' +, to . M+,

• /hree-le0el Pro#ram Memory oc2

• 53 4 8-bit !ter!al "M• 6 Pro#rammable )* i!es

• /hree 13-bit /imer)Cou!ters

• $i#ht !terrupt Sources

• Pro#rammable Serial Cha!!el

• ow-power dle a!d Power-dow! Modes

7escriptio!

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8

b!tes of "lash programmable an# erasable rea# onl! memor! $%&'OM() The #e*ice

is manufacture# using Atmel+s high-#ensit! non*olatile memor! technolog! an# is

compatible with the in#ustr!-stan#ar# 8C5 an# 8C52 instruction set an# pinout)

The on-chip "lash allows the program memor! to be reprogramme# in-s!stem or b! acon*entional non*olatile memor! programmer) .! combining a *ersatile 8-bit C%/ with

"lash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which

pro*i#es a highl!-fle0ible an# cost-effecti*e solution to man! embe##e# control

8-bit

Microco!troller

with 8K Bytes

Flash

/8C5

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/8C5



/8C5

The AT89C52 pro*i#es the following stan#ar# features 8

b!tes of "lash, 25 b!tes of 'AM, 62 4O lines, three -bit

timer4counters, a si0-*ector two-le*el interrupt architecture,

a full-#uple0 serial port, on-chip oscillator, an# clocB cir-

cuitr!) n a##ition, the AT89C52 is #esigne# with static logic

for operation #own to ero freDuenc! an# supports two

software selectable power sa*ing mo#es) The #le Mo#e

stops the C%/ while allowing the 'AM, timer4counters,

serial port, an# interrupt s!stem to continue functioning)

The %ower-#own mo#e sa*es the 'AM contents but

freees the oscillator, #isabling all other chip functions until

the ne0t har#ware reset)

Pi! 7escriptio!

<CCSuppl! *oltage)

=97<roun#)

Port '

%ort is an 8-bit open #rain bi-#irectional 4O port) As an

output port, each pin can sinB eight TT; inputs) >hen s

are written to port pins, the pins can be use# as high-

impe#ance inputs)

%ort can also be configure# to be the multiple0e# low-

or#er a##ress4#ata bus #uring accesses to e0ternal pro-

gram an# #ata memor!) n this mo#e, % has internal

pullups)

%ort also recei*es the co#e b!tes #uring "lash program-

ming an# outputs the co#e b!tes #uring program

*erification) &0ternal pullups are reDuire# #uring program

*erification)

Port 1

%ort is an 8-bit bi-#irectional 4O port with internal pullups)The %ort output buffers can sinB4source four TT; inputs)

>hen s are written to %ort pins, the! are pulle# high b!

the internal pullups an# can be use# as inputs) As inputs,

%ort pins that are e0ternall! being pulle# low will source

current $;( because of the internal pullups)

n a##ition, %) an# %) can be configure# to be the

timer4counter 2 e0ternal count input $%)4T2( an# the

timer4counter 2 trigger input $%)4T2&(, respecti*el!, as

shown in the following table)

%ort also recei*es the low-or#er a##ress b!tes #uring

"lash programming an# *erification)

Port Pi! lter!ate Fu!ctio!s

%) T2 $e0ternal count input to Timer4Counter 2(, clocB-

out

%) T2& $Timer4Counter 2 capture4reloa# trigger an#

#irection control(

Port

%ort 2 is an 8-bit bi-#irectional 4O port with internal pullups

The %ort 2 output buffers can sinB4source four TT; inputs

>hen s are written to %ort 2 pins, the! are pulle# high b!

the internal pullups an# can be use# as inputs) As inputs

%ort 2 pins that are e0ternall! being pulle# low will source

current $;( because of the internal pullups)

%ort 2 emits the high-or#er a##ress b!te #uring fetchesfrom e0ternal program memor! an# #uring accesses to

e0ternal #ata memor! that use -bit a##resses $MO: E

1%T'() n this application, %ort 2 uses strong internal pul

lups when emitting s) 1uring accesses to e0ternal #ata

memor! that use 8-bit a##resses $MO: E '(, %ort 2

emits the contents of the %2 Special "unction 'egister)

%ort 2 also recei*es the high-or#er a##ress bits an# some

control signals #uring "lash programming an# *erification)

Port 6

%ort 6 is an 8-bit bi-#irectional 4O port with internal pullups

The %ort 6 output buffers can sinB4source four TT; inputs

>hen s are written to %ort 6 pins, the! are pulle# high b!the internal pullups an# can be use# as inputs) As inputs

%ort 6 pins that are e0ternall! being pulle# low will source

current $;( because of the pullups)

%ort 6 also ser*es the functions of *arious special features

of the AT89C5, as shown in the following table)

%ort 6 also recei*es some control signals for "lash pro

gramming an# *erification)

Port Pi! lter!ate Fu!ctio!s

%6) '1 $serial input port( %6) T1 $serial output

port( %6)2 =T $e0ternal interrupt ( %6)6 =T

$e0ternal interrupt ( %6)7 T $timer e0ternal input(

%6)5 T $timer e0ternal input( %6) >' $e0ternal #ata

memor! write strobe( %6) '1 $e0ternal #ata memor!

rea# strobe(

"S/

'eset input) A high on this pin for two machine c!cles while

the oscillator is running resets the #e*ice)

$)P"*=

A##ress ;atch &nable is an output pulse for latching the

low b!te of the a##ress #uring accesses to e0ternal memor!) This pin is also the program pulse input $%'O<( #uring

"lash programming)

n normal operation, A;& is emitte# at a constant rate o

4 the oscillator freDuenc! an# ma! be use# for e0ternal

6



timingor clocBing purposes) =ote, howe*er, that one A;&

pulse is sBippe# #uring each access to e0ternal #ata

memor!)

f #esire#, A;& operation can be #isable# b! setting bit of

S"' location 8&?) >ith the bit set, A;& is acti*e onl! #ur-

ing a MO: or MO:C instruction) Otherwise, the pin is

weaBl! pulle# high) Setting the A;&-#isable bit has noeffect if the microcontroller is in e0ternal e0ecution mo#e)

PS$9%rogram Store &nable is the rea# strobe to e0ternal pro-

gram memor!)

>hen the AT89C52 is e0ecuting co#e from e0ternal pro-

gram memor!, %S&= is acti*ate# twice each machine

c!cle, e0cept that two %S&= acti*ations are sBippe# #uring

each access to e0ternal #ata memor!)

/able 1: AT89C52 S"' Map an# 'eset :alues

"8?

.

"?

&8?

ACC

&?

18?

$)<PP

&0ternal Access &nable) &A must be strappe# to <=1 in

or#er to enable the #e*ice to fetch co#e from e0ternal pro

gram memor! locations starting at ? up to """"?

=ote, howe*er, that if locB bit is programme#, &A will be

internall! latche# on reset)

&A shoul# be strappe# to : CC for internal program

e0ecutions)

This pin also recei*es the 2-*olt programming enable *olt

age $:%%( #uring "lash programming when 2-*olt

programming is selecte#)

>/1nput to the in*erting oscillator amplifier an# input to the

internal clocB operating circuit)

>/

Output from the in*erting oscillator amplifier)

""?

"?

&"?

&?

1"?



%

S



T2CO= T2MO1 'CA%2; 'CA%2? T;2 T?2



C? C

A8? A"?

%2

A? A?

98? SCO=

%S./"

9? 9?



88? TCO=

TMO1

T;

T;

T?

T?

8"?

8? %

S%

1%;

1%?

%CO=

8

. /8C5



/8C5

Special Fu!ctio! "e#isters A map of the on-chip memor! area calle# the Special

"unction 'egister $S"'( space is shown in Table )

=ote that not all of the a##resses are occupie#, an# unoc-

cupie# a##resses ma! not be implemente# on the chip)

'ea# accesses to these a##resses will in general return

ran#om #ata, an# write accesses will ha*e an in#etermi-nate effect)

/ser software shoul# not write s to these unliste# loca-

tions, since the! ma! be use# in future pro#ucts to in*oBe

/able : T2CO= @ Timer4Counter 2 Control 'egiste

new features) n that case, the reset or inacti*e *alues o

the new bits will alwa!s be )

/imer "e#isters Control an# status bits are

containe# in

registers T2CO= $shown in Table 2( an# T2MO1 $shown in

Table 7( for Timer 2) The register pair $'CA%2?, 'CA%2;are the Capture4'eloa# registers for Timer 2 in -bit cap

ture mo#e or -bit auto-reloa# mo#e)

!terrupt "e#isters The in#i*i#ual interrupt enable bits are

in the & register) Two priorities can be set for each of the

si0 interrupt sources in the % register)r

T2CO= A##ress F C8? 'eset :alue F . .it A##ressable

.it T"2 &"2 'C; TC; &&=2 T'2 C4T2 C%4';2

5 7 6 2

Symbol Fu!ctio!T"2 Timer 2 o*erflow flag set b! a Timer 2 o*erflow an# must be cleare# b! software) T"2 will not be set when either 'C; F or

TC; F )

&"2 Timer 2 e0ternal flag set when either a capture or reloa# is cause# b! a negati*e transition on T2& an# &&=2 F )

>hen Timer 2 interrupt is enable#, &"2 F will cause the C%/ to *ector to the Timer 2 interrupt

routine) &"2 must be cleare# b! software) &"2 #oes not cause an interrupt in up4#own counter mo#e

$1C&= F ()

'C; 'ecei*e clocB enable) >hen set, causes the serial port to use Timer 2 o*erflow pulses for its recei*e clocB in serial port

Mo#es an# 6) 'C; F causes Timer o*erflow to be use# for the recei*e clocB)

TC; Transmit clocB enable) >hen set, causes the serial port to use Timer 2 o*erflow pulses for its transmit clocB in serial port

Mo#es an# 6) TC; F causes Timer o*erflows to be use# for the transmit clocB)

&&=2 Timer 2 e0ternal enable) >hen set, allows a capture or reloa# to occur as a result of a negati*e transition on T2& if Timer 2

is not being use# to clocB the serial port) &&=2 F causes Timer 2 to ignore e*ents at T2&)

T'2 Start4Stop control for Timer 2) T'2 F starts the timer)

C4T2 Timer or counter select for Timer 2) C4T2 F for timer function) C4T2 F for e0ternal e*ent counter $falling e#getriggere#()

C%4';2 Capture4'eloa# select) C%4';2 F causes captures to occur on negati*e transitions at T2& if &&=2 F )C%4';2F causes automatic reloa#s to occur when Timer 2 o*erflows or negati*e transitions occur at T2& when

7ata MemoryThe AT89C52 implements 25 b!tes of on-chip 'AM) The

upper 28 b!tes occup! a parallel a##ress space to the

Special "unction 'egisters) That means the upper 28

b!tes ha*e the same a##resses as the S"' space but are

ph!sicall! separate from S"' space)>hen an instruction accesses an internal location abo*e

a##ress "?, the a##ress mo#e use# in the instruction

specifies whether the C%/ accesses the upper 28 b!tes

of 'AM or the S"' space) nstructions that use #irec

a##ressing access S"' space)

"or e0ample, the following #irect a##ressing instruction

accesses the S"' at location A? $which is %2()MOV 0A0H, #data



nstructions that use in#irect a##ressing access the upper

28 b!tes of 'AM) "or e0ample, the following in#irect

a##ressing instruction, where ' contains A?, accesses

the #ata b!te at a##ress A?, rather than %2 $whose

a##ress is A?()MOV @R0, #data

=ote that stacB operations are e0amples of in#irecta##ressing, so the upper 28 b!tes of #ata 'AM are a*ail-

able as stacB space)

/imer ' a!d 1

Timer an# Timer in the AT89C52 operate the same wa!

as Timer an# Timer in the AT89C5)

/imer

Timer 2 is a -bit Timer4Counter that can operate as either

a timer or an e*ent counter) The t!pe of operation is

selecte# b! bit C4T2 in the S"' T2CO= $shown in Table 2()Timer 2 has three operating mo#es capture, auto-reloa#

$up or #own counting(, an# bau# rate generator) The

mo#es are selecte# b! bits in T2CO=, as shown in Table 6)

Timer 2 consists of two 8-bit registers, T?2 an# T;2) n the

Timer function, the T;2 register is incremente# e*er!

machine c!cle) Since a machine c!cle consists of 2 oscil-

lator perio#s, the count rate is 42 of the oscillator

freDuenc!)

/able 6: Timer 2 Operating Mo#es

"CK ?/CK CP)"

/" M*7$

-bit Auto-reloa# -bit Capture

.au# 'ate <enerator $Off(

n the Counter function, the register is incremente# in

response to a -to- transition at its correspon#ing e0ternal

input pin, T2) n this function, the e0ternal input is sample#

#uring S5%2 of e*er! machine c!cle) >hen the samples

show a high in one c!cle an# a low in the ne0t c!cle, the

count is incremente#) The new count *alue appears in the

register #uring S6% of the c!cle following the one in which

the transition was #etecte#) Since two machine c!cles $27

oscillator perio#s( are reDuire# to recognie a -to- transition, the ma0imum count rate is 427 of the oscillato

freDuenc!) To ensure that a gi*en le*el is sample# at leas

once before it changes, the le*el shoul# be hel# for at leas

one full machine c!cle)

Capture Mode

n the capture mo#e, two options are selecte# b! b

&&=2 in T2CO=) f &&=2 F , Timer 2 is a -bit time

or counter which upon o*erflow sets bit T"2 in T2CO=

This bit can then be use# to generate an interrupt)

&&=2 F , Timer 2 performs the same operation, but a

to- transition at e0ternal input T2& also causes the current *alue in T?2 an# T;2 to be capture# into 'CA%2?

an# 'CA%2;, respecti*el!) n a##ition, the transition a

T2& causes bit &"2 in T2CO= to be set) The &"2 bit

liBe T"2, can generate an interrupt) The capture mo#e is

illus- trate# in "igure )

uto-reload @;p or 7ow! Cou!terA

Timer 2 can be programme# to count up or #own when

configure# in its -bit auto-reloa# mo#e) This feature is

in*oBe# b! the 1C&= $1own Counter &nable( bit locate# in

the S"' T2MO1 $see Table 7() /pon reset, the 1C&= bi

is set to so that timer 2 will #efault to count up) >hen

1C&= is set, Timer2 can count up or #own, #epen#ing onthe *alue of the T2& pin)



/8C5

Fi#ure 1: Timer in Capture Mo#eOSC G2

C4T2 F

T?2 T;2T"2

O:&'";O>



CO=T'O;

C4T2 F T'2

T2 %= CA%T/'&

'CA%2? 'CA%2;

T

'

TM&' 2



T2& %= &

CO=T'O;&&=2

"igure 2 shows Timer 2 automaticall! counting up when

1C&= F ) n this mo#e, two options are selecte# b! bit

&&=2 in T2CO=) f &&=2 F , Timer 2 counts up to

""""? an# then sets the T"2 bit upon o*erflow) The

o*erflow also causes the timer registers to be reloa#e#

with the -bit *alue in 'CA%2? an# 'CA%2;) The *alues

in Timer in Capture Mo#e'CA%2? an# 'CA%2; are presetb! software) f &&=2 F , a -bit reloa# can be triggere#

either b! an o*erflow or b! a -to- transition at e0ternal

input T2&) This transition also sets the &"2 bit) .oth the

T"2 an# &"2 bits can generate an interrupt if enable#)

Setting the 1C&= bit enables Timer 2 to count up or #own,

as shown in "igure 6) n this mo#e, the T2& pin controls

the #irection of the count) A logic at T2& maBes Timer 2

count up) The timer will o*erflow at """"? an# set the

T"2 bit) This o*erflow also causes the -bit *alue in

'CA%2? an# 'CA%2; to be reloa#e# into the timer regis

ters, T?2 an# T;2, respecti*el!)

A logic at T2& maBes Timer 2 count #own) The time

un#erflows when T?2 an# T;2 eDual the *alues store# in'CA%2? an# 'CA%2;) The un#erflow sets the T"2 bit an#

causes """"? to be reloa#e# into the timer registers)

The &"2 bit toggles whene*er Timer 2 o*erflows o

un#erflows an# can be use# as a th bit of resolution) n

this operating mo#e, &"2 #oes not flag an interrupt)



Fi#ure : Timer 2 Auto 'eloa# Mo#e $1C&= F (OSC G2

C4T2 F

T?2 T;2

O:&'";O> CO=T'O;T'2

C4T2 F

'&;OA1

T2 %= TM&'2

'CA%2? 'CA%2;

T"2 T'A=STO= 1&T&CTO'T2& %= &

CO=T'O;&&=2

/able .: T2MO1 @ Timer 2 Mo#e Control 'egister

T2MO1 A##ress F C9? 'eset :alue F . =ot .it A##ressable

@ @ @ @ @ @ T 2 O & 1 C & = . i t 5 7 6 2

Symbol Fu!ctio!

@=ot implemente#, reser*e# for future

T2O& Timer 2 Output &nable bit)

1C&= >hen set, this bit allows Timer 2 to be configure# as an up4#own counter)

8 /8C5



/8C5

Fi#ure 6: Timer 2 Auto 'eloa# Mo#e $1C&= F (

$1O>= CO/=T=< '&;OA1 :A;/&( TO<<;&

""? ""?

&"2

OSC 2G

C4T2 F

T?2 T;2 CO=T'O;

T'2

C4T2 F

T2 %=

O:&'";O> T"2

TM&' 2=T&''/%T

'CA%2? 'CA%2;

CO/=T

$/% CO/=T=< '&;OA1 :A;/&( 1'&CTO=

F/%

F1O>= T2& %=

Fi#ure .: Timer 2 in .au# 'ate <enerator Mo#e

TM&' O:&'";O>

G 2

HH HH

=OT& OSC) "'&3) S 1:1&1 .I 2, =OT 2

SMO1

OSC G 2 C4T2 F

HH HHT?2 T;2

'C;

'0

CO=T'O; C;OC

T'2 G

C4T2 F

HH HH

T2 %=

'CA%2? 'CA%2; TC; T0

T'A=STO=

G 1&T&CTO'

C;OC



T2& %= &"2 TM&'2

CO=T'O;

&&=2



Baud "ate =e!erator Timer 2 is selecte# as the bau# rate generator b! setting

TC; an#4or 'C; in T2CO= $Table 2() =ote that the

bau# rates for transmit an# recei*e can be #ifferent if Timer

increments e*er! state time $at 42 the oscillator fre

Duenc!() The bau# rate formula is gi*en below)

Mo#es an# 6

2 is use# for the recei*er or transmitter an# Timer is

use#

----------------------

-----------------

.au# 'ate

= ---------------------------------------------------

------------------------------------------

62 556 'CA%2? 'CA%2;for the other function) Setting 'C; an#4or TC; puts – ( , )

Timer 2 into its bau# rate generator mo#e, as shown in "ig-

ure 7)

The bau# rate generator mo#e is similar to the auto-reloa#

mo#e, in that a rollo*er in T?2 causes the Timer 2 registers

to be reloa#e# with the -bit *alue in registers 'CA%2?

an# 'CA%2;, which are preset b! software)

The bau# rates in Mo#es an# 6 are #etermine# b! Timer

2+s o*erflow rate accor#ing to the following eDuation)

Timer 2 O*erflow 'ate

where $'CA%2?, 'CA%2;( is the content of 'CA%2? an#

'CA%2; taBen as a -bit unsigne# integer)

Timer 2 as a bau# rate generator is shown in "igure 7) Thi

figure is *ali# onl! if 'C; or TC; F in T2CO=) =ote

that a rollo*er in T?2 #oes not set T"2 an# will not gener

ate an interrupt) =ote too, that if &&=2 is set, a -to-

transition in T2& will set &"2 but will not cause a reloa#

from $'CA%2?, 'CA%2;( to $T?2, T;2() Thus when Timer

2 is in use as a bau# rate generator, T2& can be

Mo#es an# 6 .au# 'ates

= -------------------------------

-----------------------------

an e0tra e0ternal interrupt) =ote that when Timer 2 i

running $T'2 F ( as a timer in

The Timer can be configure# for either timer or counter

operation) n most applications, it is configure# for timer

operation $C%4T2 F () The timer operation is #ifferent for

Timer 2 when it is use# as a bau# rate generator) =ormall!,

as a timer, it increments e*er! machine c!cle $at 42 the

oscillator freDuenc!() As a bau# rate generator, howe*er, it

Fi#ure 5: Timer 2 in ClocB-out Mo#e

the bau# rate generator mo#e, T?2 or T;2 shoul# not be

rea# from or written to) /n#er these con#itions, the Time

is incremente# e*er! state time, an# the results of a rea#

or write ma! not be accurate) The 'CA%2 registers ma! be

rea# but shoul# not be written to, because a write migh

o*erlap a reloa# an# cause write an#4or reloa# errors) The

timer shoul# be turne# off $clear T'2( before accessing the

Timer 2 or 'CA%2 registers)

OSC G2

T'2

T;2 $8-.TS(

T?2 $8-.TS(

'CA%2; 'CA%2? C4T2 .T

G2

T2O& $T2MO1)(

T'A=STO=1&T&CTO'

&"2

$T2&( =T&''/%T

&&=2



/8C5

Pro#rammable Cloc2 *ut

A 5J #ut! c!cle clocB can be programme# to come out

on %), as shown in "igure 5) This pin, besi#es being a

regu- lar 4O pin, has two alternate functions) t can be

programme# to input the e0ternal clocB for Timer4Counter 2

or to output a 5J #ut! c!cle clocB ranging from ? to 7

M? at a M? operating freDuenc!)

To configure the Timer4Counter 2 as a clocB generator, bitC4T2 $T2CO=)( must be cleare# an# bit T2O& $T2MO1)(

must be set) .it T'2 $T2CO=)2( starts an# stops the timer)

The clocB-out freDuenc! #epen#s on the oscillator fre-

Duenc! an# the reloa# *alue of Timer 2 capture registers

$'CA%2?, 'CA%2;(, as shown in the following eDuation)

the Timer 2 flag, T"2, is set at S2%2 an# is polle# in the

same c!cle in which the timer o*erflows)

/able 5: nterrupt &nable $&( 'egister

$MS.(

$;S.( &A @ &T2 &S &T & &T & &nable .it F enables the

interrupt)

&nable .it F #isables the interrupt)

Symbol Positio! Fu!ctio!

&A &) 1isables all interrupts) f &A F , no interrupt is

acBnowle#ge#) f

ClocB-Out "reDuenc!

=

Oscillator "eDuenc!

-------------------------------------------------

------------------------------------------

7556 'CA%2? 'CA%2;

×

]

–

( , )

&A F , each interrupt source is

in#i*i#uall! enable# or #isable#

b! setting or clearing its enable

n the clocB-out mo#e, Timer 2 roll-o*ers will not generate an

interrupt) This beha*ior is similar to when Timer 2 is use# as

a bau#-rate generator) t is possible to use Timer 2 as a

bau#-rate generator an# a clocB generator simulta- neousl!)

=ote, howe*er, that the bau#-rate an# clocB-out freDuencies

cannot be #etermine# in#epen#entl! from one another since

the! both use 'CA%2? an# 'CA%2;)

;"/

The /A'T in the AT89C52 operates the same wa! as the

/A'T in the AT89C5)

!terruptsThe AT89C52 has a total of si0 interrupt *ectors two e0ter-

nal interrupts $=T an# =T(, three timer interrupts $Timers

, , an# 2(, an# the serial port interrupt) These

bit)

@&) 'eser*e#) &T2 &)5 Timer 2 interrupt enable bit) &S

&)7 Serial %ort interrupt enable bit) &T &)6 Timer interrup

enable bit) & &)2 &0ternal interrupt enable bit) &T &)

Timer interrupt enable bit)

& &) &0ternal interrupt enable bit)

/ser software shoul# ne*er write s to unimplemente# bits

because the! ma! be use# in future AT89 pro#ucts)

Fi#ure 3: nterrupt Sources

interrupts are all shown in "igure )

&ach of these interrupt sources can be in#i*i#uall! enable#or #isable# b! setting or clearing a bit in Special "unction'egister &) & also contains a global #isable bit, &A, which#isables all interrupts at once)=ote that Table shows that bit position &) is unimple-mente#) n the AT89C5, bit position &)5 is alsounimplemente#) /ser software shoul# not write s to these

=T

T"

&

bit positions, since the! ma! be use# in future AT89

pro#ucts)

Timer 2 interrupt is generate# b! the logical O' of bits T"2 an# &"2

in register T2CO=) =either of these flags is cleare# b! har#ware

when the ser*ice routine is *ectore# to) n fact, the ser*ice routine

ma! ha*e to #etermine whether it was T"2 or &"2 that generate#

the interrupt, an# that bit will ha*e to be cleare# in software)

The Timer an# Timer flags, T" an# T", are set at S5%2 of the

c!cle in which the timers o*erflow) The *alues are then polle# b! the

circuitr! in the ne0t c!cle) ?owe*er,

=T

T"

T

'

T"2 &"2

&

11



*scillator Characteristics

TA; an# TA;2 are the input an# output, respecti*el!, of

an in*erting amplifier that can be configure# for use as an

on-chip oscillator, as shown in "igure ) &ither a Duart

cr!stal or ceramic resonator ma! be use#) To #ri*e the

#e*ice from an e0ternal clocB source, TA;2 shoul# be leftunconnecte# while TA; is #ri*en, as shown in "igure 8)

There are no reDuirements on the #ut! c!cle of the e0ternal

clocB signal, since the input to the internal clocBing circuitr!

is through a #i*i#e-b!-two flip-flop, but minimum an# ma0i-

mum *oltage high an# low time specifications must be

obser*e#)

dle Mode

n i#le mo#e, the C%/ puts itself to sleep while all the on-

chip peripherals remain acti*e) The mo#e is in*oBe# b!

software) The content of the on-chip 'AM an# all the spe-

cial functions registers remain unchange# #uring this

mo#e) The i#le mo#e can be terminate# b! an! enable#

interrupt or b! a har#ware reset)

=ote that when i#le mo#e is terminate# b! a har#ware

reset, the #e*ice normall! resumes program e0ecution

from where it left off, up to two machine c!cles before the

internal reset algorithm taBes control) On-chip har#ware

inhibits access to internal 'AM in this e*ent, but access to

the port pins is not inhibite#) To eliminate the possibilit! of

an une0pecte# write to a port pin when i#le mo#e is termi-

nate# b! a reset, the instruction following the one that

in*oBes i#le mo#e shoul# not write to a port pin or to e0ter-

nal memor!)

Power-dow! Moden the power-#own mo#e, the oscillator is stoppe#, an# the

instruction that in*oBes power-#own is the last instruction

e0ecute#) The on-chip 'AM an# Special "unction 'egis-

ters retain their *alues until the power-#own mo#e is

terminate#) The onl! e0it from power-#own is a har#ware

reset) 'eset re#efines the S"'s but #oes not change the on-chip 'AM) The reset shoul# not be acti*ate# before :CC

is restore# to its normal operating le*el an# must be hel#

acti*e long enough to allow the oscillator to restart an#

stabilie)

Fi#ure : Oscillator Connections

C2

TA;2 C

TA;

<=1

=ote C, C2 F 6 p" ± p" for Cr!stals

= 7 p"± p" for Ceramic 'esonators

Fi#ure 8: &0ternal ClocB 1ri*e Configuration

=C

TA;2

&T&'=A;TA; OSC;;ATO'S<=A;

Status of $4ter!al Pi!s 7uri!# dle a!d Powe-dow! Modes

Mode Pro#ram Memory $ PS$9 P*"/' P*"/1 P*"/ P*"/6

#le nternal 1ata 1ata 1ata 1ata #le &0ternal "loat 1ata A##ress 1ata %ower-#own nternal 1ata 1ata 1ata 1ata

%ower-#own &0ternal "loat 1ata 1ata 1ata



/8C5

Pro#ram Memory oc2 Bits

The AT89C52 has three locB bits that can be left unpro-

gramme# $/( or can be programme# $%( to obtain the

a##itional features liste# in the following table)

<PP 1<

Signature $6?( F &? $6?( F 52? $62?( F ""?

<PP 5<

$6?( F &?

$6?( F 52?

$62?( F 5?

oc2 Bit Protectio! ModesPro#ram oc2 Bits

B1 B B6 Protectio! /ype

/ / / =o program locB features)

2% / / MO:C instructions e0ecute# from e0ternal program

memor! are #isable# from

fetching co#e b!tes from

internal memor!, &A is

sample# an# latche# on reset,

an# further programming of

the "lash memor! is #isable#)

The AT89C52 co#e memor! arra! is programme# b!te-b!-

b!te in either programming mo#e) To program any

non-

blank byte in the on-chip Flash Memory, the entire memory

must be erased using the Chip Erase Mode.

Pro#rammi!# l#orithm .efore programming the

AT89C52, the a##ress, #ata an# control signals shoul# be

set up accor#ing to the "lash programming mo#e table an#

"igure 9 an# "igure ) To program the AT89C52, taBe the

following steps)

1. nput the #esire# memor! location on the

a##ress lines)

2. nput the appropriate #ata b!te on the #ata lines)



6% % / Same as mo#e 2, but *erif! is 6) Acti*ate the correct combination of control signals)

also #isable#) 7) 'aise &A4: %% to 2: for the high-*oltage program-

7% % % Same as mo#e 6, but e0ternal e0ecution is also

#isable#)ming mo#e)

5. %ulse A;&4%'O< once to program a b!te in the

"lash arra! or the locB bits) The b!te-write c!cle is



0000

0000 - 5 !!ww

!!ww

self-time# an# t!picall! taBes no more than )5 ms)

'epeat steps through 5, changing the a##ress

an# #ata for the entire arra! or until the en# of the

obKect file is reache#)

7ata Polli!# The AT89C52 features 1ata %olling to

in#i-

cate the en# of a write c!cle) 1uring a write c!cle, an

attempte# rea# of the last b!te written will result in the

com- plement of the written #ata on %O)) Once the write

c!cle has been complete#, true #ata is *ali# on all outputs

an# the ne0t c!cle ma! begin) 1ata %olling ma! begin an!

time after a write c!cle has been initiate#)

"eady)Busy The progress of b!te programming can

also

be monitore# b! the '1I4.SI output signal) %6)7 is pulle#

low after A;& goes high #uring programming to in#icate

./SI) %6)7 is pulle# high again when programming is

#one to in#icate '&A1I)

Pro#ram <erify f locB bits ;. an# ;.2 ha*e not

been

programme#, the programme# co#e #ata can be rea# bacB

*ia the a##ress an# #ata lines for *erification) The locB bits

cannot be *erifie# #irectl!) :erification of the locB bits is

achie*e# b! obser*ing that their features are enable#)Chip $rase The entire "lash arra! is erase# electricall! b!

using the proper combination of control signals an# b!

hol#ing A;&4%'O< low for ms) The co#e arra! i

written with all s) The chip erase operation must be

e0ecute# before the co#e memor! can be reprogramme#)

16



"eadi!# the Si#!ature Bytes The signature b!tes are

rea# b! the same proce#ure as a normal *erification of

locations 6?, 6?, an# 62?, e0cept that %6) an#

%6) must be pulle# to a logic low) The *alues returne# are

as follows)$6?( F &? in#icates manufacture# b! Atmel$6?( F 52? in#icates 89C52$62?( F ""? in#icates 2: programming

$62?( F 5? in#icates 5: programming

Flash Pro#rammi!# Modes

Pro#rammi!# !terface

&*er! co#e b!te in the "lash arra! can be written, an# the

entire arra! can be erase#, b! using the appropriate combi

nation of control signals) The write operation c!cle is self

time# an# once initiate#, will automaticall! time itself to

completion)

All maKor programming *en#ors offer worl#wi#e support fo

the Atmel microcontroller series) %lease contact !our loca

programming *en#or for the appropriate software re*ision)

Mode "S/ PS$9 $)P"*= $)<PP P:3 P: P6:3 P6:

>rite Co#e 1ata ? ; ?42: ; ? ? ?

'ea# Co#e 1ata ? ; ? ? ; ; ? ?

>rite ;ocB .it - ? ; ?42: ? ? ? ? .it - 2 ? ; ?42: ? ? ; ;

.it - 6 ? ; ?42: ? ; ? ;

Chip &rase ? ; ?42: ? ; ; ; $(

'ea# Signature .!te ? ; ? ? ; ; ; ; =ote ) Chip &rase reDuires a ms %'O< pulse)

1. /8C5



/8C5

Fi#ure : %rogramming the "lash Memor!

L5:

AT8"52 A - A

:

Fi#ure 1': :erif!ing the "lash Memor!

AT8"52 A - A :

L5:

A11') % CC



OOOO?4"""? OOOO?4"""? %<M

%2) - %2)7 % %<M %



1ATA A8 - A2 %2) - %2)7 $/S&

A8 - A2 %/;;

%2) %2)

S&& ";AS? %2) %2) A

A;& %'O< S&& ";AS?

%'O<'AMM=< %'O<'AMM=<

MO1&S TA.;& %6) MO1&S TA.;& %6)

:?

%6)TA;2 &A :4:

? %%

%6)TA;2 &A

6-27 M? 6-27 M?

TA; 'ST

:?

TA; 'ST?

<=1 %S&= <=1 %S&=

Flash Pro#rammi!# a!d <erificatio! Characteristics

T A F C to C, :CC F 5) N J

Symbol Parameter Mi! Ma4 ;!its:%%$( %rogramming &nable :oltage )5 2)5 :

%%$( %rogramming &nable Current ) mA

4tC;C; Oscillator "reDuenc! 6 27 M?

t A:<; A##ress Setup to %'O< ;ow 78t C;C;

t<?A

A##ress ?ol# after %'O< 78t C;C;



t1:<; 1ata Setup to %'O< ;ow 78tC;C;

t<?1 1ata ?ol# After %'O< 78tC;C;

t&?S? %2) $&=A.;&( ?igh to : 78t%%C;C;

tS?<; :%% Setup to %'O< ;ow s

t<?S;$( :%% ?ol# after %'O< s

t<;<? %'O< >i#th s

t A:3: A##ress to 1ata :ali# 78tC;

t&;3: &=A.;& ;ow to 1ata :ali# 78tC;

t&?3P 1ata "loat after &=A.;& 78t C;

t <?.;%'O< ?igh to ./SI ;ow ) s

t >C .!te >rite C!cle Time 2) ms

=ote ) Onl! use# in 2-*olt programming mo#e)

15



F%:

&



%

A11'&SS A11'&SS

t A:3:

%O'T 1ATA = 1ATA O/T

t 1:<;tt A:<;

<?1 t <?A

A;&4%'O<

tS?<;

t<;<?

:%%

t <?S;

;O<C



%%

t&;3:

&?3P

%2)

$&=A.;&(t <?.;

%6)7

$'1I4.SI( ./SI '&A1It>C

Flash Pro#rammi!# a!d <erificatio! (a0eforms - ow-0olta#e Mode @<PP5<A

%) - %)%2) - %2)7

%'O<'AMM=< A11'&SS

:&'"CATO=

%O'T 1ATA = t A:3:

1ATA

t 1:<;tt A:<;

<?1 t <?A

A;&4%'O<t S?<; t <;<?

;O<C

&A4:%% ;O<C

t&;3:

&?3P

%2)

$&=A.;&(t <?.;

%6)7

$'1I4.SI( ./SI '&A1I

t>C



/8C5

bsolute Ma4imum "ati!#sDOperating Temperature)))))))))))))))))))))))))))))))))) -55C to L25C

Storage Temperature))))))))))))))))))))))))))))))))))))) -5C to L5C

:oltage on An! %in

with 'espect to <roun#)))))))))))))))))))))))))))))))))))))-): to L):

Ma0imum Operating :oltage )))))))))))))))))))))))))))))))))))))))))))) ):

1C Output Current))))))))))))))))))))))))))))))))))))))))))))))))))))))5) mA

Q

=



stress rating onl! an# functional operation of the #e*ice at these

or an! other con#itions be!on# those in#icate# in the

operational sections of this specification is not implie#) &0posure

to absolute ma0imum rating con#itions for e0ten#e# perio#s

ma! affect #e*ice reliabilit!)



7C Characteristics

The *alues shown in this table are *ali# for T A F -7C to 85C an# :CC F 5): N 2J, unless otherwise note#)

Symbol Parameter Co!ditio! Mi! Ma4 ;!its

:;

:;

:?

:?

nput ;ow-*oltage $&0cept &A(-)5 )2 :CC-)

nput ;ow-*oltage $&A(-)5 )2 :CC-)6

nput ?igh-*oltage $&0cept TA;, 'ST( )2 : :CCL)9 CCL)5

nput ?igh-*oltage $TA;, 'ST( ) : :CC CCL)5

:

:

:

:



:O;

:O;

:O?

:O?

;

T;

;

Output ;ow-*oltage$( $%orts ,2,6( O; F ) mA

Output ;ow-*oltage$(

O; F 6)2 mA

$%ort , A;&, %S&=(

Output ?igh-*oltage

O? F - A, : CC F 5: N J

$%orts ,2,6, A;&, %S&=(

O? F -25 A

O? F - A

Output ?igh-*oltage

O? F -8 A, : CC F 5: N J

$%ort in &0ternal .us Mo#e(

O? F -6 A

O? F -8 A

;ogical nput Current $%orts ,2,6( := F )75:

;ogical to Transition Current

:= F 2:, : CC F 5: N J

$%orts ,2,6(

nput ;eaBage Current $%ort , &A( )75 := : CC

)75 :

)75 :

2)7 : )5 :

:CC

)9 : :CC

2)7 : )5 :

:CC

)9 : :CC

-5 A

-5 A N A

''ST 'eset %ull#own 'esistor 5 6

CO

%in Capacitance Test "reD) F M?, T A F 25C

p "

CC %ower Suppl! Current Acti*e Mo#e, 2 M? 25 mA

#le Mo#e, 2 M? )5 mA

%ower-#own Mo#e$( :CC F :

A:CC F 6: 7

A=otes ) /n#er stea#! state $non-transient( con#itions, O; must be e0ternall! limite# as follows

Ma0imum O; per port pin mA

Ma0imum O; per 8-bit port

%ort 2 mA %orts , 2, 6 5 mA Ma0imum total O; for all output pins mA

f O; e0cee#s the test con#ition, : O; ma! e0cee# the relate# specification) %ins are not guarantee# to sinB current greater

than the liste# test con#itions)

2. Minimum : CC for %ower-#own is 2:)

1



C Characteristics

/n#er operating con#itions, loa# capacitance for %ort , A;&4%'O<, an# %S&= F p" loa# capacitance for all other

outputs F 8 p")

$4ter!al Pro#ram a!d 7ata Memory Characteristics

1 M+, *scillator <ariable *scillator Symbol Parameter Mi! Ma4 Mi! Ma4 ;!its

4tC;C; Oscillator "reDuenc! 27 M?

t;?;;

t A:;;

t;;A

t;;:

t;;%;

t%;%?

t%;:

A;& %ulse >i#th 2 2tC;C;-7

A##ress :ali# to A;& ;ow 76 tC;C;-6

A##ress ?ol# After A;& ;ow 78 tC;C;-2

A;& ;ow to :ali# nstruction n 266 7tC;C;-5

A;& ;ow to %S&= ;ow 76 tC;C;-6

%S&= %ulse >i#th 25 6t

C;C;-2

%S&= ;ow to :ali# nstruction n 75 6tC;C;-75

ns

ns

ns

ns

ns

ns

ns



t %nput nstruction ?ol# after %S&= ns

t %P nput nstruction "loat after %S&= 59 t

t%A:

t A::

%S&= to A##ress :ali# 5 tC;C;-8

A##ress to :ali# nstruction n 62 5tC;C;-55

ns

ns



t %;AP%S&= ;ow to A##ress "loat ns

t ';'? '1 %ulse >i#th 7 t-

t >;>? >' %ulse >i#th 7 t-

t ';1: '1 ;ow to :ali# 1ata n 252 5t-

t '?1 1ata ?ol# After '1 ns

t'

?

1P 1ata "loat After '1 9

2t

t;;1:

t A:1:

t;;>;

t A:>;

t3:>

t3:>?

t>?3

A;& ;ow to :ali# 1ata n 5 8tC;C;-5

A##ress to :ali# 1ata n 585 9tC;C;-5

A;& ;ow to '1 or >' ;ow 2 6 6t 6tC;C;-5 C;C;L5

A##ress to '1 or >' ;ow 26 7tC;C;-5

1ata :ali# to >' Transition 26 tC;C;-2

1ata :ali# to >' ?igh 766 tC;C;-2

1ata ?ol# After >'

66 tC;C;-2

ns

ns

ns

ns

ns

ns

ns

t';AP '1 ;ow to A##ress "loat ns

t>

?

;

?

'1 or >' ?igh to A;& ?igh 76 26 tC;C;-2

tC;C;L25

ns



/8C5

$4ter!al Pro#ram Memory "ead Cyclet ;?;;

A;&

t A:;; t;;%; t;;: t%;%?

%S&= t%;:

t%;AP

t %A:

t ;;A t %P

t %

A - A A - A =ST' =

%O'Tt A::

%O'T2 A8 - A5 A8 - A5

$4ter!al 7ata Memory "ead Cyclet ;?;;

A;& t>?;?

%S&= t;;1:

t';'?

t;;>;

'1 t A:;; t;;A t';1: t '?1P

t';AP t'?1

%O'T A - A "'OM ' O' 1%; 1ATA = =ST' =A - A "'OM %C;

t A:>;

t A:1:

%O'T 2 %2) - %2) O' A8 - A5 "'OM 1%? A8 - A5 "'OM %C?

1



$4ter!al 7ata Memory (rite Cyclet ;?;;

A;&t >?;?

%S&=

t;;>;t>;>?

>' t;;A

t A:;; t3:> t3:>? t>?3

%O'T A - A "'OM ' O' 1%; 1ATA O/T =ST' =A - A "'OM %C;

t A:>;

%O'T 2 %2) - %2) O' A8 - A5 "'OM 1%? A8 - A5 "'OM %C?

$4ter!al Cloc2 7ri0e (a0eforms

tC?C

t C?C t C; C?

: - )5:CC

) :CC

)75:

tC;C

t C;C;

$4ter!al Cloc2 7ri0eSymbol Parameter Mi! Ma4 ;!its

4tC;C; Oscillator "reDuenc! 27 M?

t C;C;ClocB %erio# 7) ns

t C?C?igh Time 5 ns

t C;C;ow Time 5 ns

t C;C?'ise Time 2 ns

t C?C; "all Time 2 ns



/8C5The *alues in this table are *ali# for : CC F 5): N 2J an# ;oa# Capacitance F 8 p")

Symbol Parameter Mi! Ma4 Mi! Ma4 ;!its

t;;

t3:?

t?3

Serial %ort ClocB C!cle Time ) 2tC;C;

Output 1ata Setup to ClocB 'ising &#ge tC;C;-66

Output 1ata ?ol# After ClocB 'ising &#ge 5 2tC;C;-

s

ns

ns



t ?1nput 1ata ?ol# After ClocB 'ising &#ge ns

t ?1: ClocB 'ising &#ge to nput 1ata :ali# t

Shift "e#ister Mode /imi!# (a0eforms=ST'/CTO= 2 6 7 5

A;&

C;OC t;;

t3:?

t?3

>'T& TO S./" 2 6 7 5 O/T%/T 1ATA t ?1: t ?1 S&T T

C;&A' ' :A;1 :A;1

=%/T 1ATA S&T '



C /esti!# !put)*utput (a0eforms@1A Float (a0eforms@1A

: - )5:CC )2 : L )9:

):::;OA1L

)

T&ST %O=TS Timing 'eference:;OA1

)2 : - ):CC

%oints

)

)75:

=ote ) AC nputs #uring testing are #ri*en at : CC - )5: =ote ) "or timing purposes, a port pin is no longer floating

for a logic an# )75: for a logic ) Timing measure-

ments are ma#e at :? min) for a logic an# : ; ma0)

for a logic )

when a m: change from loa# *oltage occurs) A

port pin begins to float when a m: change fromthe loa#e# :

O?4: O; le*el occurs)



*rderi!# !formatio!Speed@M+,A

Power Supply *rderi!# Code Pac2a#e *peratio! "a!#e

2 5: ± 2J AT89C52-2AC

AT89C52-2UC AT89C52-2%C AT89C52-23C

77A77U7%773

Commercial

$°C to

°C(

AT89C52-2A AT89C52-2U AT89C52-2% AT89C52-23

77A77U7%773

n#ustrial

$-7°C to

85°C(

5: ± 2J AT89C52-AC

AT89C52-UC AT89C52-%C AT89C52-3C

77A77U7%773

Commercial

$°C to

°C(

AT89C52-A AT89C52-U AT89C52-%

AT89C52-3

77A77U7%773

n#ustrial

$-7°C to

85°C(

2 5: ± 2J AT89C52-2AC

AT89C52-2UC AT89C52-2%C AT89C52-23C

77A77U7%773

Commercial

$°C to

°C(

AT89C52-2A AT89C52-2U AT89C52-2% AT89C52-23

77A77U7%773

n#ustrial

$-7°C to

85°C(

27 5: ± 2J AT89C52-27AC

AT89C52-27UC

AT89C52-27%C AT89C52-273C

77A77U

7%773

Commercial

$°C to°C(

AT89C52-27A AT89C52-27U AT89C52-27% AT89C52-273

77A77U7%773

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