Assm13 Lecture 2 Digital Components

8/13/2019 Assm13 Lecture 2 Digital Components

1/67

10/6/2013 1

CSW 353(Assembly Language)

Computer

ArchitectureDr. Salma [email protected]
mailto:[email protected]:[email protected]


2/67

Course LogisticsTextbook Outline

2

Chapter 1:Digital Logic Circuits

Chapter 2:Digital Components

Chapter 3:Data Representation

Chapter 4:Register Transfer and

Microoperations

Chapter 5:Basic Computer OrganizationChapter 6:Programming the Basic Computer

Chapter 7:Microporgammed Control

Chapter 8:CPU

Chapter 11:I/O Organization

Chapter 12:Memory Organization


3/67

Digital

Components1. Integrated Circuits

2. Decoders3. Multiplexers

4. Registers

5. Binary Counters

6. Memory Units


4/67

1. Integrated Circuits

Miniature, low-costelectronics circuits whose

components are fabricated on

a single, continuous piece ofsemiconductor material to

perform a high-level function.

Usually referred to as a

monolithic IC.410/6/2013


5/67


6/67

1. Integrated Circuits(cont.)

610/6/2013

2. Circuit technology (digital logic family):Bipolar or MOS or both.

Bipolar:

Diode logic (DL). (obsolete) Resistor transistor logic (RTL). (obsolete)

Diode transistor logic (DTL). (obsolete)

Transistor Transistor logic (TTL).

Emitter Coupled Logic (ECL), also known as Current

Mode Logic(CML).

Integrated Injection logic (I2L). (obsolete)


7/67


2. Circuit technology (digital logic family):Bipolar or MOS or both.

MOS:

PMOS family (using P-channel MOSFETs) (obsolete) The NMOS family (using N-channel MOSFETs).

The CMOS family (using both N- and P-channel

devices). The Bi-MOS logic family uses both bipolar and MOS

devices.

710/6/2013


8/67


Data sheet

810/6/2013


9/67


Basic componentsCombinational

Decoders binary adders or any Boolean function

Multiplexers

Sequential

Flip-Flops

Registers binary counters and memory units

910/6/2013


10/67

2. Decoders

Converts binary information from codedinputs to a maximum of unique outputs.

-to-line or . (can use less than )

Each output represents one of the mintermsof the input variables.

1010/6/2013


11/67

2. Decoders(cont.)

A -to-line decoder

1110/6/2013


12/67

2. Decoders(cont.)

Truth table for

-to-

line decoder

1210/6/2013


13/67

2. Decoders(cont.)

A

-to-

line decoder can be used for: Binary to octal conversion: input variable may

represent a binary number, and outputs will

then represent the eight digits in a octalnumber system.

1310/6/2013


14/67

2. Decoders(cont.)

Generally, decoders can be used for: Implementing Boolean functions: any

combinational circuit with inputs and

outputs can be implemented with an

-to-

decoder and OR gates.

Example:

implement a full-adder circuit.

1410/6/2013


15/67

2. Decoders(cont.)

Decoders can be used for: Implementing Boolean functions.

Example:

implement a full-adder circuit.

1510/6/2013


16/67

2. Decoders(cont.)

A

-to-

line decoder with enable(demultiplexer)

1610/6/2013


17/67

2. Decoders(cont.)

Truth table for

-to-

line decoder withenable:

1710/6/2013


18/67

2. Decoders(cont.)

NAND gate decoders produce the mintermsin their complement form.

-to-line NAND decoder with enable.

1810/6/2013


19/67

2. Decoders(cont.)

Decoder expansion: constructing largerdecoder from smaller ones.

1910/6/2013

The most significant bit(s)decide(s) which decoder(s)

is/are enabled and which

is/are disabled.


20/67

2. Decoders(cont.)

An encoder circuit performs the inverseoperation of a decoder.

Has (or less) input lines and output

lines that generate the binary codecorresponding to the input value.

Example: octal to binary decoder.

2010/6/2013


21/67

2. Decoders(cont.)

An encoder circuit performs the inverseoperation of a decoder.

Has (or less) input lines and output

lines. Example: octal to binary decoder.

2110/6/2013

It is assumed that only

one input has the valueof 1 at any given time;

otherwise, the circuit

has no meaning.


22/67

Selected Problems

2210/6/2013


23/67

Selected Problems(cont.)

2310/6/2013


24/67

10/6/2013 24



25/67

10/6/2013 25



26/67

10/6/2013 26



27/67


28/67

3. Multiplexers

Multiplexing means transmitting a largenumber of information units over a smaller

number of channels or lines.

A digital multiplexer (MUX, data selector) isa combinational circuit that selects binary

information from one or many input lines

and directs it to as single output line. Selection is controlled by a set of selection

lines inputs and selection lines.2810/6/2013


29/67

3. Multiplexers(cont.)

-to-

multiplexer

2910/6/2013


30/67


A

-to-

multiplexer is constructed from an-to- decoder by adding to it input

lines, one from each data input and using

the inputs as selection lines.

May have enable input to control the

operation of the unit.

Two or more in single IC package.3010/6/2013


31/67


Quadruple

-to-

line multiplexer

3110/6/2013


32/67

10/6/2013 32



33/67

10/6/2013 33



34/67

10/6/2013 34



35/67

10/6/2013 35



36/67

4. Registers

ICs that contain storage cells are classifiedby the function they perform:

Registers

Counters

Memory units.

3610/6/2013


37/67

4. Registers(cont.)

A registeris a group of flip-flops. -bit register has a group of flip-flops and

is capable of storing any binary information

of bits. Built into the CPU Very fast

A register may hold a computer instruction ,

a storage address, or any kind of data.

Register = flip-flops (load) + gates (control

when/how data is transferred into register).3710/6/2013


38/67

4. Registers(cont.)

Loading= transfer ofnew info into a register.

Parallel load = all

bits of the register are loaded

simultaneously (single clock

pulse).

3810/6/2013

A 4-bit register


39/67

4. Registers(cont.)

Parallel load Master clock

then a separate

load control signal.

3910/6/2013


40/67

4. Registers(cont.)

Parallel load example Design a sequential circuit whose state table

is listed below.

4010/6/2013


41/67

4. Registers(cont.)


is listed below.

4110/6/2013


42/67

4. Registers(cont.)


is listed below.

4210/6/2013


43/67

4. Registers(cont.)

Parallel load example

4310/6/2013


44/67

4. Registers(cont.)

Shift Register: capable of shifting its binaryinformation in one (unidirectional) or both

directions (bidirectional).

Logical configuration: a chain of flip-flops incascade.

4410/6/2013 A 4-bit shift register


45/67

4. Registers(cont.)

Serial transfer

4510/6/2013

( )


46/67

4. Registers(cont.)

Serial transfer

4610/6/2013


47/67

i ( )


48/67

4. Registers(cont.)

Bidirectional shift register with parallel load

4810/6/2013

i ( )


49/67

4. Registers(cont.)


4910/6/2013

4 R i ( )


50/67

4. Registers(cont.)


often used to interface digital systems

situated remotely from each other, e.g.

transmission of

-bit between two points. Transmitter loads in parallel into a shift

register, transmits from serial output.

Receiver accepts one at a time through serialinput into a shift register, then taken in

parallel after all bits are accumulated.5010/6/2013

5 C


51/67

5. Counters

A counter is basically a register that goes

through a predetermined sequence of states

upon the application of input pulses.

The design of synchronous binary counters: Previous lecture (sequential circuits).

Direct inspection of the sequence of states that

the register must undergo. e.g. 0000, 0001, 0010 when does a bit change?

5110/6/2013

5 C ( )


52/67

5. Counters(cont.)

Synchronous binary counters have a regular

patter and their circuit will usually employ

flip-flops with complementing capabilities

T or JK. Example: 4-bit counter with JK flip-flips.

5210/6/2013

5 C t ( t )


53/67

5. Counters(cont.)

4-bit synchronous binary counter.

5310/6/2013

To extend counter to

next stage

5 C t ( t )


54/67

5. Counters(cont.)

Binary counters with Parallel Load for

transmitting an initial binary number prior

to the counter operation.

5410/6/2013

5 C t ( t )


55/67

5. Counters(cont.)

Binary counters with Parallel Load

5510/6/2013

S l t d P bl


56/67

10/6/2013 56

Selected Problems

S l t d P bl ( t )


57/67

10/6/2013 57


S l t d P bl ( t )


58/67

10/6/2013 58



59/67

Selected Problems (cont )


60/67

10/6/2013 60




61/67

10/6/2013 61


45

6

7



62/67

10/6/2013 62




63/67

10/6/2013 63




64/67

10/6/2013 64




65/67

10/6/2013 65


Next Lecture


66/67

Next Lecture

Register Transfer and Microoperations.

6610/6/2013

Assignment

- Reading: Chapters 2+3.


67/67

Assm13 Lecture 2 Digital Components

Documents

Transcript of Assm13 Lecture 2 Digital Components