assignment 1 - solution - comp228
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Brief Solution to Assignment 1 1(a) Memory is to store the program code and data. Processor is to serve as the interpreter of the ISA; it fetches a line of code and executes it using the necessary functional blocks (inside or outside the processor). Input/output serves as the interface to the outside world for external control/data interaction. (b) Registers are used to buffer program data produced during program execution, according to instructions executed. Program counter stores a memory address (pointer) that stores the next instruction to be executed. Hence it identifies the flow of the ‘control token’ key to the von Neumann (control-flow) model. (c) With two distinct blocks, program code cannot be confused with program data and hence information cannot be misused by error. However, it also reduces the flexibility in sharing the memory when program data grows larger than the data partition. 2(a) The key motivation is information hiding while creating more functionality in moving from one layer of abstraction to the next higher level. In particular, some lower level details are hidden from the higher level so that users in the higher level do not have to worry/deal with such details. (b) Cache, ALU and RAM chips are not part of the ISA. (c) Program counter and registers are not in the higher layer. (d) There are 20 18-month periods in 30 years. So the transistor count will scale up by 2 20 . If the bit count scale correspondingly (linearly in the same way), k = 2 22 . This is certainly unreal. If we restrict k to 128, according to this linear scaling assumption, we can have 2 22-7 processors, which is a huge number. In the third generation, the integrated circuit technology was only adequate to build a processor using many IC chips. However, with Moore’s law scaling, later a single chip has grown with so many transistors that they can build many functional units working in parallel. In order to actually use these effectively (actually doing useful work), parallel processing is the only reasonable avenue to follow. 3(a) 00000123 [=256+32+3] (b) FFFFFEDD (c) 00000001 + FFFFFEDD = FFFFFEDE The binary form can be similarly done. (d) 00323931 and 2D323931 respectively (e) 291 + x = 2 31 x = 2 31 – 291 [2 31 cannot be stored in 32 bits in 2’s complement] (f) Suppose x and y are both positive. Then x > x – y > -y. Since both x and –y can be represented without overflow, the same must hold for x – y. 4(a) 30324E5C = 3*16 7 + 3*16 5 + 2*16 4 + 4*16 3 + 14*16 2 + 5*16 + 12. Similarly for the half-word case. (b) Same as in (a), since the most significant bit is 0 (hence positive). (c) ‘02N\’
description
4(a) 30324E5C = 3*16 7 + 3*16 5 + 2*16 4 + 4*16 3 + 14*16 2 + 5*16 + 12. Similarly for the half-word case. (b) Same as in (a), since the most significant bit is 0 (hence positive). (c) ‘02N\’ Brief Solution to Assignment 1 Since a data word can represent difference data types, as the above examples demonstrate, the result can be different. This non-uniqueness cannot be resolved unless the person also knows the data type used. (d)
Transcript of assignment 1 - solution - comp228
Brief Solution to Assignment 1 1(a) Memory is to store the program code and data. Processor is to serve as the
interpreter of the ISA; it fetches a line of code and executes it using the necessary functional blocks (inside or outside the processor). Input/output serves as the interface to the outside world for external control/data interaction.
(b) Registers are used to buffer program data produced during program execution, according to instructions executed. Program counter stores a memory address (pointer) that stores the next instruction to be executed. Hence it identifies the flow of the ‘control token’ key to the von Neumann (control-flow) model.
(c) With two distinct blocks, program code cannot be confused with program data and hence information cannot be misused by error. However, it also reduces the flexibility in sharing the memory when program data grows larger than the data partition.
2(a) The key motivation is information hiding while creating more functionality in
moving from one layer of abstraction to the next higher level. In particular, some lower level details are hidden from the higher level so that users in the higher level do not have to worry/deal with such details.
(b) Cache, ALU and RAM chips are not part of the ISA. (c) Program counter and registers are not in the higher layer. (d) There are 20 18-month periods in 30 years. So the transistor count will scale up
by 220. If the bit count scale correspondingly (linearly in the same way), k = 222. This is certainly unreal. If we restrict k to 128, according to this linear scaling assumption, we can have 222-7 processors, which is a huge number.
In the third generation, the integrated circuit technology was only adequate to build a processor using many IC chips. However, with Moore’s law scaling, later a single chip has grown with so many transistors that they can build many functional units working in parallel. In order to actually use these effectively (actually doing useful work), parallel processing is the only reasonable avenue to follow.
3(a) 00000123 [=256+32+3] (b) FFFFFEDD (c) 00000001 + FFFFFEDD = FFFFFEDE The binary form can be similarly done. (d) 00323931 and 2D323931 respectively (e) 291 + x = 231 x = 231 – 291 [231 cannot be stored in 32 bits in 2’s
complement] (f) Suppose x and y are both positive. Then x > x – y > -y. Since both x and –y can
be represented without overflow, the same must hold for x – y. 4(a) 30324E5C = 3*167 + 3*165 + 2*164 + 4*163 + 14*162 + 5*16 + 12. Similarly for the half-word case. (b) Same as in (a), since the most significant bit is 0 (hence positive). (c) ‘02N\’
(d) Since a data word can represent difference data types, as the above examples demonstrate, the result can be different. This non-uniqueness cannot be resolved unless the person also knows the data type used.
5(a) There are an odd number of 1-bits in 30324E5C. So the parity bit should be 1 (to
make the total number even). If the most significant bit is toggled from 0 to 1, then the even parity invariant is violated. However, this error (and hence the invariant violation) could have occurred in any of the 33 bits (without knowing it in advance). So the location is not feasible.
(b) 2k > 32 + k k must be at least 6. We have the following encoded word: [I have used 0200300A as data word
instead, a version slightly different from the problem on the web]. 000000_10…..0110_0….0_101_0_ _ (31st) (19th) There are 5 1-bits in the data word, with positions as indicated:
31 = 16 + 8 + 4 + 2 + 1 19 = 16 + 2 + 1 18 = 16 + 2 7 = 4 + 2 + 1 5 = 4 + 1 Specifically bit 31 belongs to parity groups at bit positions 16, 8 4, 2 and 1, and
similarly for the rest. To ensure even parity, we must have the following encoded word:
000000010….011010….011011000; In other words, parity bit 1 is 0; parity bit 2 is 0; parity bit 4 is 1; parity bit 8 is 1;
parity bit 16 is 1; parity bit 32 is 0. (c) If the most significant bit [corresponding to bit position 38] is toggled from 0 to 1,
since 38 = 32 + 4 + 2, parity bit 32, parity bit 4 and parity bit 2 will have their even invariant violated and the rest of the parity bits will be fine. This pinpoints the error bit to be bit 38.
[Correction: if the error is in the least significant bit of the data word, this bit belongs to parity bit/group 1 and 2. As a result, similarly, the even parity invariant will be violated at groups 1 and 2, pinpointing that the error bit is bit 3 of the encoded word (and hence the least significant bit of the data word).]
