Asic vs Fpga
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Transcript of Asic vs Fpga
Xilinx CopyrightFPGA vs ASIC 1
ASIC vs. FPGA
Prof. S. S. S. P. RaoChief Technology OfficerXilinx India Development Centre, Hyderabad
18th September 2006
Xilinx CopyrightFPGA vs ASIC 2
Fundamental Law of VLSI Technology …
“The number of transistors in an integrated circuit will double every 18 months”
Today’s chips have close to 500 Million transistors !Source: Intel web site
Xilinx CopyrightFPGA vs ASIC 3
What is an ASIC? What is an FPGA?
• ASIC (Application Specific Integrated Circuit)
Fixed Function chip
• FPGA (Field Programmable Gate Array)
Programmable chip
Xilinx CopyrightFPGA vs ASIC 4
Processor vs. FPGA Programming
• Processor: hardware functionality already exists, software ‘programs’ use of hardware
• FPGA: hardware functionality created by ‘programming’
PROGRAM GATES PROGRAM INSTRUCTIONS
MEMA B
ALU
HW FIXED HW CREATED
Xilinx CopyrightFPGA vs ASIC 5
Types of chips Semi-conductors, ICs
• Available semiconductor chips can be generalized to three types 1. Processor2. Memory3. Logic, Interface chips
- ASICs- FPGAs
• System on Chip (SOC) - Integrated semiconductor chips containing all three types
Processor
Logic - I/F ChipsASICs FPGAs
Memory
SOC
Platform FPGAs can also implement SOC functions. Now have 2 PowerPCs, 10 Mb Memory and 11.1 Gbps IOs
Xilinx CopyrightFPGA vs ASIC 6
Major Application Areas
Radio tower
Satellite dishSatellite
Disk array
1 2 3
4 5 6
7 8 9
* 8 #
SD
SD
ESC
DLT
PROLIANT 8000
Networking
Communication - Wireless - Wired
Automotive
Industrial
Storage, Server and Computing
Aerospace, Military, Mission Critical
Consumer Electronics
FPGAs ASICs
Examples: Mars RoverBMW Cars
7
Source: Gartner Dataquest (December 2003)
• FPGA and ASIC combined market is still growing
FPGA and ASIC Market FPGAs are taking market share away from ASICs
13.70%
19.50%
0
5
10
15
20
25
2002 2003 2004 2005 2006 2007
Bill
ion
$
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
ASICFPGAFPGA %
8
ASIC, FPGA Design Starts
Source: Gartner Dataquest (December 2003)
0
20,000
40,000
60,000
80,000
100,000
120,000
1999 2000 2001 2002 2003 2004
FPG
A, A
SIC
- D
esig
n St
arts
0
100
200
300
400
500
600
Den
sity
- M
illio
n Tr
ansi
stor
s/ch
ip
(-27%)
(-60%)
Notes: 1. Decreasing number is due to increased integration (Moore’s law) 2. Designs of later years have much more equivalent functionality
74,941
102,000
8,950
24 M3,609
500 MFPGA
ASIC
Density
9
FPGA Design Trend Relative to ASICs Design Starts
200
300
400
500
100
2001 2002 2003 2004
ASICFPGA
Num
ber o
f Des
igns
(tho
usan
ds)
Source: Gartner Group
5 4 2 1.5
500
400
100X
Xilinx CopyrightFPGA vs ASIC 10
What’s Inside These Chips? ASIC FPGA
Functionality (or Logic)
Building block is a ‘Cell’
Building block is a programmable unit called ‘LUT’ (Look Up Table)
Interconnect (or Routing)
Routing is custom-crafted by hand or by tool
Pre-defined routing tracks which are programmable (using a ‘switch’ matrix)
Xilinx CopyrightFPGA vs ASIC 11
‘Complex’ function
AB
CD
Z
Cells
ASIC ‘Cell’ • Implements a fixed function like ‘And’, ‘XOR, ‘Mux’, ‘1 bit
adder’, etc (very much like TTL chips like the 74xx series)
• The entire chip is then built ‘hierarchically’ with cells being connected together to create more complex functions (eg. Multipliers, decoders, etc)
Xilinx CopyrightFPGA vs ASIC 12
‘Complex’ function
AB
CD
Z
‘standard cell’ or ‘custom’ circuit
Types of ASICs • Standard-cell based ASIC (80%):
– If ASIC is designed using a ‘standard’ library of cells, it is a ‘standard-cell’ or ‘cell-based’ ASIC
– Shorter design cycle, low-medium performance• Custom ASIC (20%):
– If ASIC is designed using ‘custom’ and ‘semi-custom’ circuits, it is a custom ASIC
– Longer design cycle, peak performance
Xilinx CopyrightFPGA vs ASIC 13
ASIC: Major Components
• Typically, ASICs contain the following types of blocks:– Clocking circuitry– Datapath– Control block– Cache– IO– Specialized blocks based on application – Routing
Xilinx CopyrightFPGA vs ASIC 14
SRAM Anti-fuse
SRAM cell
SRAM programmed with 1/0 to enable/disable connection
between A and B
A B
A B
A BUn-programmed Anti-fuse
Anti-fuse programmed to enable connection between
A and B
Programmed Anti-fuse
(open)
(closed)
Conductor
Insulator(oxide)
BA
FPGA Programming Technologies
Xilinx CopyrightFPGA vs ASIC 15
Note: Majority of FPGAs in the industry are SRAM based
SRAM vs. Anti-fuse
SRAM
Reprogrammable
Standard mfg
process
Larger size
Slower
Anti-fuse One-Time Programmable Special mfg process Smaller size Faster
Xilinx CopyrightFPGA vs ASIC 16
Combinatorial Function
AB
CD
Z
A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1
. . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1
FPGA Look-Up Table (LUT)• Combinatorial functions are implemented using a LUT
• A 4-input LUT has 16 ‘programmable’ SRAM cells to implement any arbitrary 4-input function- 22**4 = 65,536!! Functions
• Each of the 16 SRAM cells is ‘programmed’ with the output value of Z associated with that line in truth table
• Capacity limited by number of inputs, not complexity.4 inputs has been found to be optimum
Xilinx CopyrightFPGA vs ASIC 17
LUT Implementation
A B DCSRAM Cell
16 SRAM cells in a LUT
Z
A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1
. . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1
Xilinx CopyrightFPGA vs ASIC 18
16 bit Shift Register
16 x 1 RAM
4 input LUT
Multiple Personalities of a LUT
• With minimal additional circuitry, the same block can serve multiple purposes:– 4 input LUT– 16x1 RAM– Shift Register
Xilinx CopyrightFPGA vs ASIC 19
Slice 0
LUT Carry
LUT Carry D QCE
PRE
CLR
DQCE
PRE
CLR
Simplified FPGA ‘Slice’
• Moving up in hierarchy, an FPGA ‘slice’ has – 2 LUTs for combinational
logic– 2 registers for sequential
logic– carry logic for fast adders– 4 outputs, 2 registered +
2 non-registered
Xilinx CopyrightFPGA vs ASIC 20
CIN
SwitchMatrix
BUFTBUF T
COUTCOUT
Slice S0
Slice S1
Local Routing
Slice S2
Slice S3
CIN
SHIFT
Slices and CLB• Each CLB (Configurable
Logic Block) contains 4 slices
• Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs
• A switch matrix provides access to general routing resources
Xilinx CopyrightFPGA vs ASIC 21
Loca
l Int
erco
nnec
t
SwitchMatrixFor
GlobalInterconnect
Functionality/Logic
Interconnect/Routing
Interconnects Require a Lot of Care !
• We tend to focus on functionality, but watch out for those interconnects !! With increased integration,
• Interconnects now contribute the majority (70-80%) of the delay in most chips (vs 20-30% for functionality)
• Interconnects are the major source of the most subtle, complex, difficult-to-debug problems in a chip. Eg. Clocking and Coupling problems, race conditions, etc
Xilinx CopyrightFPGA vs ASIC 22
Today’s FPGA2 PowerPC™
Processors 450 MHz
High-speed 11.1 Gbps
Serial Transceivers
>500 DSP datapaths
18 Bit
18 Bit36 Bit
200, 000 LUTs (~10 million
gates)
Z
VCCIO
Z
Z
ImpedanceControl
Programmable IO+ DCI (Digitally
Controlled Impedance)
10Mbit Dual-Port™ RAM
Xilinx CopyrightFPGA vs ASIC 23
Translate
Map
Place & Route
HDL RTLSimulation
FunctionalSimulation
Attain Timing Closure
TimingSimulation
Implement
Create Design HDL/
Schematic Integrate IP Cores
Map: Assign (‘map’) gates to physical components (LUTs, registers, etc)
Unique to FPGA
Design-flow
Silicon:5 min (FPGA)vs.5 months (ASIC)!
VLSI Design FlowPlan & Budget
Synthesizeto Create
Netlist
CreateBit File (FPGA)
Mask Files (ASIC)
Translate: Merge multiple design files into single netlist
Xilinx CopyrightFPGA vs ASIC 24
The Physical Silicon Chips5 min vs. 5 months!
• FPGA– implemented in physical silicon by using the ‘bit’ file. – already manufactured. Hence the term ‘field’ programmable
• ASIC– implemented in physical silicon by using the ‘masks’ (which
are expensive) – transistors that implement the functionality/logic are
manufactured first (hence called ‘lower layers’) and then the interconnect between them (hence called ‘upper layers’).
Substrate
Metal
Oxide
Metal
Diagram from: The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx CopyrightFPGA vs ASIC 25
FPGA vs. ASICDesign Methodology Comparison
FPGA ASIC
Asynchronous circuits
Riskier to use because delays are hard to control
Lower risk since delays can be well controlled
Finite State Machines
One-hot encoding commonly used because of large number of registers
Gray, Binary, other encoding schemes
Pipelining Deeper pipelines because of large number of registers available
As needed
Scan, test circuits
Already in the chip
Need to be added separately
Physical Silicon
Takes 5 minutes!! Created using ‘bit’ files to program FPGA
Takes 5 months!! Created by manufacturing the chips using ‘masks’
Xilinx CopyrightFPGA vs ASIC 26
Key ‘Engineering’ Factors
• Cost
• Design cycle time / Time-To-Market
• Performance/Speed
• Density/Size
• Production volume
• Ease of fixing bugs, making changes
Xilinx CopyrightFPGA vs ASIC 27
FPGA vs. ASIC Cost High Design Cost of an ASIC is a major issue
• Total cost of IC product= Design cost (also called NRE or Non-Recurring
Engineering cost) + Cost of parts sold= Design cost + (# of parts sold * Cost/part)
• ASIC– High design/NRE cost ($ 3 to 5 Million plus $ 0.5 to 1
Million for the masks plus prototype costs)– Lower cost/part
• FPGA– Low design/NRE cost – Higher cost/part
Xilinx CopyrightFPGA vs ASIC 28
Volume
Total cost
ASIC .13µ
FPGA .13µFPGA .09µ
ASIC .09µ
ASIC Design Cost is much
higher(and
increasing)!!
For each technology advance, crossover volume moves higher
FPGA vs. ASIC Cost ASIC: High volumes needed to recover design cost
ASIC cost/part is lower
Xilinx CopyrightFPGA vs ASIC 29
FPGA vs. ASIC Time-To-MarketFPGA Time-To-Market is 9 months vs 2-3 years for ASIC
FPGA flexibility allows late changes, higher chance of meeting customer needs
Spec Design & verification SiliconPrototype
System Integration
SiliconProduction
FirstShip
ASIC
FirstShip
Spec Design & Verification System Integration
FPGA
55% less time
Xilinx CopyrightFPGA vs ASIC 30
Relative Cost of a BugVerify Verify Verify!!!
1 310
30
100
0
20
40
60
80
100
120
Arch Design Test System Customer
Note: Verification now takes longer than design!!
Xilinx CopyrightFPGA vs ASIC 31
FPGA vs. ASIC ComparisonBug Fixes/Design Changes
• FPGA: relatively straight-forward. Reprogram the FPGA• ASIC: changes much harder to implement. 2 types of fixes:
– metal-only. Fix to interconnect/‘upper layers’ only. Less expensive– full-turn. Fix to ‘transistors’/‘lower layers’. Entire chip has to be
refabricated. Most expensive• Due to the high cost of fabrication, every attempt is made to find a
metal-only fix
Substrate
Metal
Oxide
Metal
Diagram from: The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx CopyrightFPGA vs ASIC 32
FPGA ASIC Design Time / Time-To-Market
~ 9 Months
(2-3 Years)
Design Cost
($ 3-5 M, $1M masks)
Performance (speed, density, power)
Size (area)
Total Cost
at low-medium
volume
at high volume
Changes to design
FPGA vs. ASICEngineering Comparison
Xilinx CopyrightFPGA vs ASIC 33
FPGA & ASIC Trends
• Due to Moore’s law, both FPGAs and ASICs are increasingly target ‘System On Chip’ applications
• FPGAs: – Glue logic ASIC bug fixes ASIC prototypes
ASIC replacement System On Chip
• Due to increased integration, many ASIC market requirements now met by FPGAs– e.g. Virtex 4 has 2 processors, 10 Mb memory, 11.1
Gbps IO
Xilinx CopyrightFPGA vs ASIC 34
Summary
• FPGAs and ASICs are 2 different approaches to a problem
• Driven by Moore’s law, low design cost and shorter design cycle time, FPGAs are becoming an increasing % of solution!
• ASICs remain solution of choice only for high performance at increasingly high volume needs – a decreasing % of solution!
• FPGAs (or programmable logic) is the fastest growing segment in the semi-conductor industry!