ASIC Physical Design CMOS Processes - Auburn...
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ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste – “CMOS VLSI Design” Global Foundries: “BiCMOS_8HP8XP_Training.pdf” “BiCMOS_8HP_Design_Manual.pdf”
Transcript of ASIC Physical Design CMOS Processes - Auburn...
ASIC Physical DesignCMOS Processes
Smith Text: Chapters 2 & 3Weste – “CMOS VLSI Design”
Global Foundries: “BiCMOS_8HP8XP_Training.pdf”“BiCMOS_8HP_Design_Manual.pdf”
Physical design process overview
CMOS transistor structure and fabrication steps Standard cell layouts Creation, verification & characterization of a standard-cell
based logic circuit block Creation of a chip from circuit blocks
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ASIC layout
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ASIC Design Flow
BehavioralDesign
Gate-LevelNetlist
Transistor-LevelNetlist
PhysicalLayout
DFT/BIST& ATPG
VerifyFunction
VerifyFunction
Verify Function& Timing
Verify Timing
DRC & LVSVerification
Mask DataELEC 5250/6250/62564
ASIC Design Flow
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IC “Floorplan”
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Source: Weste “CMOS VLSI Design”
CMOS standardcell layout(generic)
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BiCMOS8HP NAND2_A Cell (LEF file)Yellow – “Pins” Orange = Poly Blue = Metal1
Cadence Encounter “Cell Viewer” ToolELEC 5250/6250/62568
BiCMOS8HP DFFS_B Cell (LEF file)Yellow – “Pins” Orange = Poly Blue = Metal1
Cadence Encounter “Cell Viewer” ToolELEC 5250/6250/62569
Standard Cell-Based Block
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Global Foundries BiCMOS8HP process cross-section
“Passivation”
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BiCMOS8HP process cross-section
Aluminum
Copper
PC = Polysilicon
Via
Via
Via
Via
CA = Contact to diffusion/poly
External Connections
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BiCMOS8HP metallization options: AM
(RF wiring)Analog Metal
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GND orVSS
+
VDS
LW
VGS
bulksource drain
Tox
Ex
electrons
++
VDS
bulk
drain
gate
sourceVGS
+
mobile channel charge
depletionregion
p-type
n-type n-type
gate
fixed depletion charge
Basic N-channel MOS transistor
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CMOS Inverter Cross-Section
Source: Weste “CMOS VLSI Design”ELEC 5250/6250/625615
Inverter cross-section with well and substrate contacts
Source: Weste “CMOS VLSI Design”ELEC 5250/6250/625616
1
2 4
3
6
As+
5
7 8 9 10 11 12
1 hour
grow crystal saw
resistsp infurnace
mask
etchresistoxide
wafer
grow oxide
IC fabrication process
4. Grow oxide SiO25. Apply photoresist6. UV light exposes resist7. Remove exposed resist
8. Etch exposed oxide9-10. Implant ions in exposed substrate11. Strip resist12. Etch oxide
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CMOSProcesssteps
P-substrate
SiO2 layer
Photoresist
Expose and etch
Etch SiO2
Remove photoresist
Implant n-well
Remove SiO2
Source: Weste “CMOS VLSI Design”ELEC 5250/6250/625618
Deposit poly
Etch
Deposit SiO2
Etch
Diffusion
Remove SiO2
Source: Weste “CMOS VLSI Design”
CMOSProcesssteps
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Invertermask set N-well
Poly
N+ diffusion
P+ diffusion
Contacts
Metal
Source: Weste “CMOS VLSI Design”
Generated byIC layout tools
“Layout” is a setof patterns foreach layer.
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Invertermask set
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Source: Smith, Figure 2.7
Standard Cell Mask Set (Submitted to foundry)
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MOSIS fabrication processes(www.mosis.org)
TSMC Fabrication Processes28, 40, 65, 90, 130, 180 and 350 nanometer processes. Tiny2 program is also available on 65 and 180nm processes.
GlobalFoundries Fabrication Processes14 nm, 28 nm, 40 nm, 55 nm, 0.13 µm,0.18 µm, 9HP (90 nm), 8HP (0.13 µm), 8XP (0.13 µm), 7WL (0.18 µm), 7RF SOI (0.18 µm) 7SW (0.18 µm) 9WG (90 nm), 9WG (90 nm), and TinyChip processes.
ON Semiconductor Fabrication Processes0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS.
ams AG Fabrication Processes180 and 350 nanometer processes - CMOS and high voltage CMOS and SiGe-BiCMOS.
AIM Fabrication ProcessesAIM Photonics Fabrication
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Source: Weste “CMOS VLSI Design”
(Older) MOSIS fab processes(http://www.mosis.org)
Mentor GraphicsASIC Design Kit
Scalable CMOS
AMI bought by ON Semiconductor: http://www.onsemi.com/TSMC (Taiwan Semiconductor): http://www.tsmc.com
=ON=ON
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nwell
pwell
nwell
pwell
ndiffpdiff
pdiffndiff
ndiffpdiff
pdiffnwell
poly
nwell
pwell
p-se lectn-se lect
ndiffpoly
poly
nwell
poly
metal2
m1
polycontact
pdiff
polyactivecontact
m3
via2m3
glass
m2
m1
n-select
pdiff
p-se lect
ndiff
pdiff
1. well 2. active 3. poly
4. select5. polycontact
6. activecontact
7. metal1
9. metal2 15. metal3 10. overglass (microns)
pwell
nwell
hot
poly
ndiff
m1 m2
via1
8. via1
m2
m3via2
via1
m2
14. via2
m2
via1
m1
21
4
3
5
6
7 8
15 10149
m3
0 (1.4) 9 (1 .2)
10 (1.1)
0 or 6 (1 .3)
3 (2 .1)
3(2.2)
5 (2 .3)0 or 4(2.5)
0 or 4(2.5)
3 (2 .4)3
(2.2)
3 (2 .1) 5 (2 .3) 3 (2 .4)
2 (3 .2)
2 (3 .1)
2 (3 .3)
1 (3 .5)
3 (3 .4)
1.5(5.2a)
2 2 (5.1a)
2 (5 .3a)
1.5 (6.2a)
2 2(6.1a)
2 (6 .4a)
1.5(6.2a)
3 (8 .2)2 2 (8.1)2 (8 .5)
2 (8 .5)2 (8 .4)
1 (8 .3)
2 (6 .3a)1 (4 .3)
2 (4 .2)
3 (7 .1)1 (7 .3)
3(7.2a)
1 (7 .4)
3 (4 .1)
2(7.2b)
3(14.2)
2 (14.4)
1(14.3)
2 2 (14.1)3 (9 .1)
4(9.2a)
1(9.3)
3(9.2b)
6(15.1)
4 (15.2)
2 (15.3)
6 (10.3) 30 (10.4)
15(10.5)
100 100 (10.1)
Scalable CMOS process design rules
Source: Smith, Figure 2.11ELEC 5250/6250/625625
MOSISDesignRules
Smith text:Tables 2.7-2.9
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MOSISDesignRules
Smith text:Tables 2.7-2.9
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MOSISDesignRules
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Smith text:Tables 2.7-2.9
MOSIS Design Rules
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Smith text:Tables 2.7-2.9
MOSIS Design Rules
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Smith text:Tables 2.7-2.9
