Pandian Saraswathi Yadav Engineering College,Madurai-Sivagangai Highway, Arasanoor – 630561

COURSE PLAN

Department: ECE / M.E. (VLSI DESIGN)

Subject code & Subject: VL9261 / ASIC DESIGN

Semester: III

Name of the faculty member: K.KARTHIK

Text and Reference Books S.No. Title of the book Author(s) Publications

R1Application Specific Integrated Circuits

M.J.S.Smith Wesley Longman Inc., 1997.

R2From ASICs to SOCs: A Practical Approach

Farzad Nekoogar and Faranak Nekoogar

Prentice Hall PTR, 2003.

R3FPGA-Based

System DesignWayne Wolf Prentice Hall PTR, 2004.

R4System-on-a-Chip Design and Test

R. Rajsuman Artech House Publishers, 2000.

R5Timing Verification of Application-Specific

Integrated Circuits (ASICs)F. Nekoogar Prentice Hall PTR, 1999.

Lecture No.

Unit No.

Topic to be taught Page No. of Text or

Reference bookINTRODUCTION TO ASICS, CMOS

LOGIC AND ASIC LIBRARY DESIGN1. I Types of ASICs R1(18-30)2. I Design Flow, CMOS Transistors R1(30-34),R1(55-63)3. I CMOS Design Rules, Combinational Logic Cell R1(72-74),R1(74-84)4. I Sequential Logic Cell R1(84-88)5. I Data Path Logic Cell R1(89-113)6. I Transistors as Resistors R1(131-136)7. I Transistor Parasitic Capacitance R1(136-143)8. I Logical Effort R1(143-155)9. I Library Cell Design ,Library Architecture R1(155-158)

PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE

ASIC I/O CELLS

10. IIAnti Fuse, Static RAM ,

EPROM and EEPROM TechnologyR1(184-190)

11. II PREP Benchmarks R1(193-198)12. II Actel ACT R1(205-218)13. II Xilinx LCA, Altera FLEX R1(218-223)

14. II Altera MAX R1(223-232)15. II DC & AC Outputs R1(246-257)16. II DC & AC Inputs R1(257-267)17. II Clock & Power Inputs R1(267-272)18. II Xilinx I/O Blocks R1(272-276)

PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC DESIGN SOFTWARE

AND LOW LEVEL DESIGN ENTRY19. III Actel ACT R1(289-298)20. III Xilinx LCA, Xilinx EPLD, R1(298-303)

21. IIIAltera MAX 5000 & 7000,

Altera MAX 9000, Altera FLEXR1(303-308)

22. III Design Systems, Logic Synthesis R1(313-320)23. III Half Gate ASIC R1(321-330)24. III Schematic Entry R1(342-359)25. III Low Level Design Language R1(359-367)26. III PLA tools, EDIF R1(367-383)27. III CFI Design Representation R1(383-386)

LOGIC SYNTHESIS,SIMULATION AND TESTING

28. IV Verilog and Logic Synthesis R1(594-607)29. IV VHDL and Logic Synthesis R1(607-619)30. IV Types of Simulation R1(655-666)31. IV Boundary Scan Test - I R1(728-738)32. IV Boundary Scan Test - II R1(738-750)33. IV Fault Simulation - I R1(759-763)34. IV Fault Simulation - II R1(763-769)35. IV Automatic Test Pattern Generation - I R1(769-772)36. IV Automatic Test Pattern Generation - II R1(773-778)

ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND ROUTING

37. V System Partitioning R1(823-834)38. V FPGA Partitioning R1(834-838)39. V Partitioning Methods R1(838-851)40. V Floor Planning R1(867-887)41. V Placement, Physical Design Flow R1(887-909)42. V Global Routing R1(924-936)43. V Detailed Routing R1(936-949)44. V Special Routing R1(949-953)45. V Circuit Extraction - DRC R1(953-959)

Signature of faculty member Signature of HOD Signature of Principal