ASIC Design Methodology

7/29/2019 ASIC Design Methodology

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Outline

Conventional System Design Methodology

ASIC/VLSI Design methodology

- Logic Design

- Physical Design

- Fabrication

Conclusion


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VariousTechnologies

Specification

PCB Product Design Methodology

Architecture Design

Logic Design

Physical Design

Product Assembly

Test

Production

Pr

oduct


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System Block Diagram

System

I

NPUT

o

UTPU

T

Control


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System Block Diagram

System

I

NPUT

o

UTPU

T

Control

A/D

PLA

I/O

comp

RAM


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Logic Design


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Physical Design -Layout


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Components for Assembly


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Product

IO Ports

Logic gates&

Components

nets

substrate


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Test

Functional Design Parameters

Environmental Reliability


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Miniaturization & Integration

ASIC

PCB Product


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VLSITechnology

Specification

Overview of VLSI Design Methodology

ASIC


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VariousTechnologies

Specification

ASIC/VLSI Design Methodology

Architecture Design

Logic Design

Physical Design

Fabrication

Test

Production

Product - ASIC

System Simulation

Logic Verification

Physical Verification

Extrapolatedverification

Electrical TestingEnvironmental Testing

Reliability Testing

Quality Assurance

TimingAn

alysis

PowerAn

alysis

crosstalkA

nalysis


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Parameters

Functional Parameters

Performance/Design Parameters-- Area-- Speed-- Power

-- Noise Technology-- Complexity/Density-- Design Turnaround Time-- Design Methodology

-- EDA Tools-- Process Technology-- Library-- Operating Conditions

-- Cost


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Moores Law

171

101001K

10K100K

1M

10M

Transisto

rs

80866800068020

803868048668040

80804004

Pentium ProPentiumPPC601

PPC603

MIPS R4000

Microprocessors

T h l Di SIZES


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Technology : Die SIZES

Fall2003

18

EE5301-

VLSIDesignAutomat

ionI

Intel386TM DXProcessor

Intel486TM DXProcessor

Pentium Processor

Pentium Pro &Pentium II Processors

1.5m 1.0m 0.8m 0.6m 0.35m 0.25mSilicon ProcessTechnology


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unc ona yTechnology

Functionality

Gate

Density Technology


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EDA Tools

20

Results

(design productivity)

Effort(EDA tool effort)

Transistor entry Calma, Computervision, Magic

Schematic entry Daisy, Mentor, Valid

Synthesis Cadence, Synopsys

Whats next?

D i Ab i


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Design Abstraction

Algorithmic

Encoding data, computation

scheduling, balancing

delays of components, etc.

Gate-level Reduce fan-out,

capacitance

Gate duplication, bufferinsertion

Layout / Physical-Design

Move cells/gates around to

shorten wires on critical

21

Eevene

Leofdea


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-Y Chart

Circuit abstraction levelMicro architecture

abstraction level

ogic abstraction level System abstractilevel

Physical domain

StructuralDomain

Behavioral Domain

Synthesis

Chips.MCM,boards

Cells

Chips / modules

Layout transistor

TransistorsLogic gates

ALUs , registers

processors

instructionsSubroutines ,B.equations

programs

Application algorithms

ASIC D i St l


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ASIC Design Styles

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Full Custom

Gate Array

Standard Cell

FPGA

DesignMethods

Cost /DevelopmentTime

Quality # Companiesinvolved


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LOGIC DESIGN

PHYSICAL DESIGN

Foundry

Specification

A Typical ASIC Design Flow

ASIC

Technologies


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Methodology

LogicSimulation

LogicSynthesis

ArchitecturalDesign

Gate Level

Netlist

Bug FreeRTL Code

StructuralDesign

Std. CellsMacrosIO Cells

LogicalLibrary

Customer

Specification


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System Architecture

datapath

controller

alucontrol

ph1

ph2

reset

memdata[7:0]

writedata[7:0]

adr[7:0]

memread

memwrite

op[5:0]

zero

pcen

regw

rite

irwrit

e[3:0

]

mem

toreg

iord

pcso

urce[1:0

]

alusr

cb[1:0

]

alusr

ca

aluop[1:0]

regdst

funct[5:0]

alu

co

ntrol[2:0

]


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Design HierarchyProcessor

ALUcontroller Data Path

Logic Arithmetic Sequencing

Full Adder MultiplierDivider

Half Adder Half Adder

XOR AND XOR AND

AND OR INV AND OR INV


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ALU : Block Level


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ALU : Gate Level

OP = 000 XOR

OP = 001 ANDOP = 010 OR

OP = 011 Addition

ALU Operations
http://upload.wikimedia.org/wikipedia/commons/9/9f/2-bit_ALU.png


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Full Adder : Block Level

a b

c

s

cout carry

sum

s

a b c

cout

fulladder


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Full Adder using half Adder

Logic : Gate


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Logic : GateLevel/Structural Model

ab

ac

b

c

cout

x

y

z

g1

g2

g3

g4

Structural :

Behavioral : assign cout = (a&b) | (a&c) | (b&c);

ABC

S = A + B + C

u er : e av ora


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u er : e av oraModel

module fulladder(input a, b, c,

output s, cout);

sum s1(a, b, c, s);carry c1(a, b, c, cout);

endmodule

module carry(input a, b, c,

output cout)

Design


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Carry : Gate Level Netlist

module carry(input a, b, c,

output cout)

wire x, y, z;

and g1(x, a, b);

and g2(y, a, c);

and g3(z, b, c);

or g4(cout, x, y, z);endmodule


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Bench

Design

INPU

T

OUTPUT

CONTROL VECTORS

TEST BENCH

Test Bench using HDL


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module main;reg a, b;wire sum, carry;halfadder add(a,b,sum,carry);always @(sum or carry)begin$display("time=%d:%b + %b = %b,carry = %b\n",$time,a,b,sum,carry);

endinitialbegina = 0; b = 0;#5

a = 0; b = 1;#5a = 1; b = 0;#5a = 1; b = 1;

endendmodule

Test Bench using HDLTest Bench


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Functional Verification

L i & Ph i l Lib


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Logic & Physical LibraryLogic Physical

A B Vdd

Vss

AB Y

INV

NAND

Vdd

Vss

Vdd

VssNOR

INV NAND NOR

A

Y

A

Y

B

A

Y

B

argete ec no ogy rary


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argete ec no ogy raryParametersTypes of Libraries : Area Optimized

Power Optimized

Timing Optimized Parameter Limit : Min, Typ , Max Parameters Types

Electrical : VDD (max/min) , V ol/oh, V ol/ih etc

Thermal : Defense, Industrial, ConsumerTiming : tp hl/hl, tr, tf , ts, th etcProcess : Stringent, Typical, Leanient

Library Components :Std.Cell around 400 Types various Drive Strengths

- INV,NAND,AOI,FF,MUX,LATCHES etcMacros PLL,RAM,ROM,ADC etcIO Cells VDD,VSS, Clk, Data Bus etc.

S th i t Lib


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Synthesis to Library

Std. Cell

Macros

IO Cell

Technology

Logic Library

SynthesisRTL Code

Gate Level

Netlist

Translation

Optimization

Mapping


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What is Synthesis?

Logic Synthesis is the automated

process of converting a functional

model of a system into a gate-level

circuit.


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Why Synthesis is required?

Benefits of synthesis:

High level design entry

Increased designer productivityReduction of layout design expertise

requirement

Improved quality

Technology independence

Facilitates design re-use and sharing


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SYNTHESIS

= TRANSLATION + OPTIMIZATION + MAPPING

+ Mapping

HDL Source

Generic ( GTECH)

Target Technology

S th i Fl


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Synthesis Flow


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SYNTHESIS = TRANSILATION + OPTIMIZATION + MAPPING

module and2 (z, a, b);

output z;

input a, b;

always @ (a or b)

if (a == 1 and b == 1)

z


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module or2 (z, a, b);

output z;

input a, b;

always @ (a or b)

if (a == 0 and b == 0)

z


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module cnt (q, d, clk, rst);

output q;

input d, clk, rst;

reg q;

always @ (posedge clk)

if (rst)

q


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module cnt (cout, clk, rst);

output [3:0] cout;

input clk, rst;

reg [3:0] cout;

always @ (posedge clk)

if (rst)

cout


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Code for Synthesis

Code that is functionally equivalent, butcoded differently, will give different

synthesis results.

You cannot rely solely on Tool to fix a

poorly coded design.

Try to understand the hardware you aredescribing, to give tool the best possible

starting point.


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Order and Group Arithmetic Functions

The ordering and grouping of arithmetic functions can influence

design performance.

For Verilog, the following two statements are not necessarilyequivalent.

Statement1:ADD = A1 + A2 + A3 + A4;

Statement2:ADD = (A1 + A2) + (A3 + A4);

The secondstatement creates two adders in parallel: A1 + A2 and A3 + A4. In

the second statement, the two additions are evaluated in parallel

and the results are combined with a third adder. RTL simulation

results are the same for both statements, however, the second

statement results in a faster circuit after synthesis (depending onthe bit width of the input signals).


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The first statement cascades three adders in series.

Statement1:ADD = A1 + A2 + A3 + A4;


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Statement2:ADD = (A1 + A2) + (A3 + A4);

In the second statement, the two additions are

evaluated in parallel and the results are combined

with a third adder.


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Resource Sharing

Resource sharing is an optimization technique that uses asingle functional block (such as an adder or comparator) to

implement several operators in the HDL code.

Use resource sharing to improve design performance by

reducing the gate count and the routing congestion.

If you do not use resource sharing, each HDL

operation is built with separate circuitry.

However, you may want to disable resource sharing for

speed critical paths in your design.

R Sh i


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Resource Sharing


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Resource Sharing

Mapping


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Mapping

High-level synthesis is Constraint-Driven.

High-level synthesis is based on design constraints andcoding style

Tool makes high-level synthesis decisions to produce area-

efficient results that meet timing.

High-level Synthesis takes place only when optimizing an

unmapped design

It will not occur when re-optimizing a gate-level netlist.

Exception: Incremental implementation selection can recur

after mapping to gates.


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Combinational mapping


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Order and Group Arithmetic FunctionsAlthough the second statement generally results in a faster circuit,

in some cases, you may want to use the first statement.

For example, if the A4 signal reaches the adder later than the

other signals, the first statement produces a faster implementation

because the cascaded structure creates fewer logic levels for A4.

This structure allows A4 to catch up to the other signals. In thiscase, A1 is the fastest signal followed by A2 and A3; A4 is the

slowest signal.

Most synthesis tools can balance or restructure the arithmeticoperator tree if timing constraints require it.

However, it is recommended that you code your design for your

selected structure.


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Multiple Architectures for each Macro

+

Ripple Carry

Ripple Carry-Select

Carry Look Ahead

Carry Save

yn es s npu :


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moduleHalfadder (a,b,sum,carry);input a,b;

output sum, carry;wire sum, carry;assign sum = a^b; // sum bitassign carry = (a&b) ;//carry bitendmodule

Design

yn es s npu :Code

Translation/Optimization Gentech


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Translation/Optimization - Gentech

S = A XOR B = A. B + A. B.

C = A AND B = A . B

Algorithmic

Schematic

Mapped to Generic Library


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Design : Generic

Mapped to Generic Library

u1u3

u4u2

A

B

C

SD

E

Mapped to Technology


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Mapped to Technology

u1u3

u4u2

A

B

C

SD

E

NOT GateANDLAND2LAND4LANDXL

OR GateORLOR2L

OR4LORXL

AND GateANDLAND2LAND4LANDXL

AOI Gate--------------

Design: Technology Mapped Technology Library

AND2L

OR2L

NOTLAND4L

Synthesized Gate Level Netlist


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Synthesized Gate Level NetlistModule Half Adder S, C, A, B ;

AND2L u1 S A B ;

OR2L u2 D A B ;

NOTL u3 E S ;

AND4L u4 C D E ;

--- - -----

End Module

Gates

instantiation

nets


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ASIC Design Methodology

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