ASEE 2014 Zone I Conference, April 3-5, 2014, University of Bridgeport, Bridgpeort, CT, USA.

PSPICE Implementation of an 8-bit Low Power Energy Recovery Full Adder

Xingguo Xiong

Abstract —Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arithmetic Logic Unit (ALU). It is a building block of the application of VLSI, digital signal processing, image processing and microprocessor. An 8-bit low power and low transistor count static energy recovery full adder (SERF) is implemented in this paper. The power consumption and general characteristics of the SERF adder are then compared with the 8-bit traditional CMOS full adder. PSPICE power simulation is used to verify its power consumption for the given input pattern sequence. Simulation result demonstrates effective power saving of the energy recovery full adder compared to static CMOS full adder.

Keywords —Low Power VLSI, Energy Recovery, Full Adder, PSPICE, Power Simulation.

I. INTRODUCTION The explosive development in laptop and portable systems and in cellular networks has intensified the research efforts in low power electronics. Today there are an ever-increasing number of portable applications requiring low power and high throughput than ever before. For portable information systems, power dissipation has a direct bearing on size, weight, cost, and battery life. So power dissipation is becoming widely recognized as a top-priority issue for VLSI circuit design. Therefore, low-power design has become a major design consideration. Static energy recovery full (SERF) adder with 10 transistors with reduced power consumption at the cost of large delay is presented in [1]. Energy recovery includes any technique or method of minimizing the input of energy to an overall system by exchange of energy from one sub-system of the overall system with another. Energy recovery logic utilizes a different way from standard CMOS logic to charge and discharge node capacitance and can achieve ultra-low power consumption, which the common techniques cannot reach.

One of the most efficient way to reduce power dissipation is energy recovery which was proposed a decade ago in the form of Hot-clock CMOS [13]. According to the proposal CMOS chips have been built and demonstrated [10-12]. The idea was to apply the power from low-impedance AC sources, such as the clock lines, to directly drive the large capacitive loads of an MOS chip. From their observation it was found that for increasing the transition time of the clock signals the energy that would be wasted as heat could be saved for future use. For the clock driver an inductor circuit was proposed which could deliver energy via resonant transistors. The quasi-static energy recovery logic (QSERL) is another method of reducing power dissipation [14] [15]. It uses two complementary sinusoidal supply clocks and possesses several positive characteristics of static CMOS logic. The lower switching activity reduces energy dissipation. During the slow charge and recovery process of node capacitance, the power clock together with the clock generator circuit forms a resonant network. The whole circuit dissipation is caused by the path resistance (which is called adiabatic loss) and the voltage difference of the two path ends (which is called non-adiabatic loss).Based on the power consumption energy recovery circuit can be divided into fully adiabatic and partially adiabatic circuit. Fully adiabatic circuit can avoid non-adiabatic loss by retractile power clock or reversible logic, both of which are impractical for realization. Partially adiabatic circuit has simpler structure and power clock scheme while consuming much less power compared to traditional CMOS digital circuit, so it is a viable option for real low power applications. Kim et al. proposed NMOS energy recovery logic (NERL)[16]. NERL exhibits low-energy consumption due to efficient energy transfer and recovery using bootstrapping. Tzartzanis et al [6] recently proposed an energy recovering adder which was shown to be power efficient however it required complex dynamic logic for its operation. Transmission gate CMOS adder (TGA) based on

Jian Chen1, Xingguo Xiong2, Mirza Rishad Hasan3 Department of Electrical Engineering

University of Bridgeport Bridgeport, CT 06604

Email1: ken.cj@hotmail.com, Email3: mihasan@my.bridgeport.edu

transmission gates with 20 transistors is reported in [7]. Main disadvantage of TGA is that it requires double number of transistors than pass transistor logic for implementations same logic function. The fourteen transistor full-adder [8], as the name implies, uses 14 transistors to realize the adder function. To date this is the most area efficient design. The 14T full adder cell, like the transmission function full adder cell, implements the complementary pass logic to drive the load.

II. CMOS DESIGN CMOS technology offers two types of transistors called “N-channel” (NMOS) and “P-channel” (PMOS). NMOS is generally connected to the lowest voltage level available in circuit. PMOS is generally connected to the highest voltage level in the circuit. The traditional full adder cell is made of two connected complex gates. A CMOS version of a full adder is shown in Figure 1. In this project, we use Cadence OrCAD PSPICE to build the circuit. The cell of the adder is shown in figure 2.

. Fig. 1. Schematic of a CMOS full adder [9]

Fig. 2. Design of 1-bit CMOS full adder

The tradition 1-bit CMOS full adder contains 28 transistors. The power simulation is done using hierarchical design. The hierarchy of power simulation is done in order to achieve accuracy and efficiency. This power-analysis system consists of two components. One is used to compute the information of circuit activity, and another is used for

power characterization data. A SPICE circuit simulation gives the accurate power dissipation of each input. The 8-bit circuit by using hierarchy logic is shown in fig. 3 below.

Fig. 3. Schematic view of 8-bit CMOS full adder

There are 28 transistors in each block, so there are totally 224 transistors in the circuit. In the simulation, I give 8 patterns to both input A and input B. The input A: a0a1a2a3a4a5a6a7 = ‘01111000’, ‘01101010’, ‘11101100’, ‘10001111’, ‘00100111’, ‘00110100’, 10110010’, ‘01001010’. The input B: b0b1b2b3b4b5b6b7 =‘11101010’, ‘11001001’, ‘11010110’, ‘01100111’, ‘00001101’, ‘10111001’, ‘10010001’, ‘11000111’.

Fig. 4. PSPICE waveforms of input A

Fig. 5. PSPICE wave form of input B

After using PSPICE simulation, the output SUM of the

traditional CMOS full adder is shown in fig 6.

Fig. 6. Sum of the CMOS full adder

Table 1. Compare expected result with simulated result of CMOS full adder

Input Output

Expected Simulated A7A6A5A4A3A2A1

B7B6B5B4B3B2B1

S7S6S5S4S3S2S1

S7S6S5S4S3S2S1

00011110 01010111 01110101 01110101 01010110 10010011 11101001 11101001 00110111 01101011 10100010 10100010 11110001 11100110 11010111 11010111 11100100 10110000 10010100 10010100 00101100 10011101 11001001 11001001 01001101 10001001 11010110 11010110 01010010 11100011 00110101 00110101 From the figure and table above, we can see all the inputs and outputs trace are correct. Fig. 7 shows the power consumption of the 8-bit traditional CMOS full adder.

Fig. 7. Power dissipation of traditional full adder

From the image above we can see the power consumption of the traditional CMOS full adder design for the given input pattern sequence is 1.4312mW.

III. Static Energy Recovery Full Adder (SERF) Design The cell of static energy recovery full adder only use 10 transistors and it does not need inverted inputs. The design was inspired by the XNOR gate full adder design. The SERF adder has no direct path to the ground. The elimination of a path to the ground reduces power consumption, removing the Psc variable (product of Isc and voltage) from the total power equation. The charge stored at the load capacitance is reapplied to the control gates. This circuit operates well at higher supply voltages, but if the supply voltage is scaled to voltages lower than 0.3V, this circuit fails to work. This is confronted with some problems especially when the SERF adder at lower supply voltage. Assume that one of the two patterns ABCin= ‘110’ and ‘111’ are applied. As seen from figure 8, when A=1 and B=1, the voltage at node F is Vdd-Vth. Now if the Cin is ‘0’ then Cout will be equal to Vdd-2Vth and the sum signal will go to zero. When Cin=1, Cout is connected to Vdd (may be lower) and the SUM signal is going to Vdd-Vth. Another problem with this circuit is when the floating node is connected to 0 (A=0, B=1 or A=1, B=0). When Cin=1, Cout is connected to Vdd, but if Cin is ‘0’, Cout will be discharged to ground by a PMOS pass transistor that cannot fully discharge the output. A 1-bit SERF adder is shown in figure 8.

Fig. 8. Static Energy-Recovery Full (SERF) Adder (10 transistors)

We also use PSPICE and hierarchical design to build the 1-bit and 8-bit SERF adder circuit.

Fig 9. 1-bit SERF adder

Fig. 10. 8-bit SERF adder

The SERF adder only uses 10 transistors in each cell, so the total number of transistors in the 8-bit SERF adder is 80. To compare with the traditional adder, we use the same inputs patterns as CMOS full adder. The input patterns are shown in Figure 4 and Fig. 5. After simulated by PSPICE, the output SUM signal of 8-bit SERF adder is shown in Fig. 11 below.

Fig. 11. Sum of 8-bit SERF adder

Table 2. Compare expected result with simulated result of SERF adder Input Output

Expected Simulated A7A6A5A4A3A2A1

B7B6B5B4B3B2B1

S7S6S5S4S3S2S1

S7S6S5S4S3S2S1

00011110 01010111 01110101 01110101 01010110 10010011 11101001 11101001 00110111 01101011 10100010 10011110 11110001 11100110 11010111 11010111 11100100 10110000 10010100 10010100 00101100 10011101 11001001 11001001 01001101 10001001 11010110 11010110 01010010 11100011 00110101 01110101 In above figure and table, most patterns are correct, however it seems for some patterns the voltage waveform is

showing some intermediate voltage values (e.g. for some patterns, V (S5) is showing values of ~2.5V). This is abnormal. Such voltage level cannot be correctly recognized as either “0” or “1”. That’s because in 1-bit SERF adder design, there are some special patterns (‘001’, ‘100’, ‘110’, and ‘111’) not performing well. When the adder runs these patterns, it affects the result. Fig. 12 shows the power dissipation of the 8-bit SERF adder.

Fig. 12. Power dissipation of 8-bit SERF adder

From the image above we can see the power consumption of the traditional CMOS full adder design for the given input pattern sequence is 773.901µW.

III. POWER DISSIPATION SOURCES

A. Power dissipation types There are two types of power dissipation: Dynamic (switching) Power Consumption and Static (leakage) Power Consumption. The dynamic power consumption appears when signals which go through the circuit change their logic state. The charging and discharging of capacitive loads during the states change. The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor is considered as leakage power which also called static power consumption. The leakage of a CMOS logic gate does not depend on input transition or load capacitance but remains constant for a logic cell.

B. Lower power design space For the lower power design it should reduce the dynamic power or static power. In general, the main factor for low-dynamic power design space is voltage, capacitance, and data activity. For the circuit level power can be reduced by some methods, such as transistors sizing, inverter chain, and threshold voltage, PIN ordering in CMOS, related logic, use parallelism and pipelining in system architecture, use standby modes-clock disabling and power down of selected logic blocks, software redesign to low power dissipation and

pass transistor logic. One or more of these factors to be reduced can optimize the power.

IV. ADIABATIC PRINCIPLE The operation of adiabatic logic gate can be divided into two distinct stages: one stage is used for logic evaluation; the other stage is used to reset the gate output logic value. Both of stages utilize adiabatic switching principle.

A. Conventional Switching The three major components that contribute to the power consumption in CMOS circuit are the static dissipation due to leakage current, the dissipation due to switching transient current and the dissipation due to charge and discharge of load capacitance [3]. The equivalent circuits of CMOS logic for charging and discharging is shown in figure 1. The total power in a CMOS circuit is given by the following equation [2].

P = ΣiV!!V!"#$%C!"#$fPi + V!!ΣiI!"# + V!!I! (1)

Where Vdd is the power supply voltage, Vswing is the voltage swing of the output which is ideally equal to Vdd, Cload is the output load capacitance at node i, f is the system clock frequency, Pi is the switching activity at node I, and Iisc is the short circuit current at node I, and Il is the leakage current. The summation is over all the nodes of the circuit. It is important to note that, in simulation studies, for accurate estimation of the switched capacitance the number of simulation cycles that is needed. It is recommended to have between 50 and 100 simulation cycles for an accurate estimation of the capacitance. A reduction in any of the appropriate components in above equation will obviously reduce power consumption.

Fig. 13. Conventional CMOS (a) Charging (b) Discharging

B. Adiabatic Switching Adiabatic switching can be achieved by ensuring that the potential across the switching devices is kept arbitrarily small. This can be achieved by charging the capacitor from a time-varying voltage source or constant current source as shown in fig. 14.

Fig. 14. Schematic for Adiabatic Charging Process

Here R represents the on-resistance of the pMOS network. Also note that a constant charging current corresponds to a linear voltage ramp. Assuming that the capacitance voltage Vc is zero initially, the variation of the voltage as a function of time can be found as

𝑉! 𝑡 = !!!!

(1)

Hence the charging current can be expressed as a function of Vc and time t

𝐼! =!!!(!)

! (2)

The amount of energy dissipated in the resistor R from t = 0 to t = T can be found as

𝐸!"## = 𝑅 𝐼!!!! 𝑑𝑡 = 𝑅𝐼!!𝑇 (3)

Combining (3) and (4), the dissipated energy during this charge-up transition can be also expressed as

𝐸!"## =!"!𝐶𝑉!!(𝑇) (4)

From (5) it can be seen that the dissipated energy is smaller than for the conventional case if the charging time 𝑇 ≫ 2𝑅𝐶 and can be made small by increasing the charging time. A portion of the energy thus stored in the capacitance can also be reclaimed by reversing the current source direction, allowing the charge to be transferred from the capacitance back into the supply. Adiabatic logic circuits thus require non-standard power supplies with time-varying voltage, also called pulsed power supplies. The additional hardware overhead associated with these specific power supply circuits is one of the design trade-off. Practical supplies can be constructed by using resonant inductor circuits. But the use of inductors should be limited from integrated circuit point because of so many factors like chip integration, accuracy, efficiency etc. An alternative to using pure voltage ramps is to use stepwise supply voltage waveforms, where the output voltage of the power supply is increased and decreased in small increments during charging and discharging. Since the energy dissipation depends on the average voltage drop across the resistor by using smaller voltage steps the dissipation can be reduced considerably. The total dissipation using step wise charging is given by equation (6).

𝐸!"#$$ =!!𝐶𝑉!!! /2 (5)

Where n is the number of steps used to charge up capacitance to Vdd. Energy recovery includes any technique or method of minimizing the input of energy to an overall system by exchange of energy from one sub-system of the overall system with another. Energy recovery logic utilizes a different way from standard CMOS logic to charge and discharge node capacitance and can achieve ultra-low power consumption, which the common techniques cannot reach.

During the slow charge and recovery process of node capacitance, the power clock together with the clock generator circuit forms a resonant network. The whole circuit dissipation is caused by the path resistance (which is called adiabatic loss) and the voltage difference of the two path ends (which is called non-adiabatic loss).Based on the power consumption energy recovery circuit can be divided into fully adiabatic and partially adiabatic circuit. Fully adiabatic circuit can avoid non-adiabatic loss by retractile power clock or reversible logic, both of which are impractical for realization. Partially adiabatic circuit has simpler structure and power clock scheme while consuming much less power compared with traditional CMOS digital circuit, so it is a viable option for real low power applications [4][5]

V. CONCLUSIONS AND FUTURE WORK In this paper, the design and simulation of an 8-bit SERF adder with PSPICE is proposed. In order for comparison, an 8-bit CMOS full adder is also designed. The total number of transistors used in CMOS full adder and SERF adder are 224 and 80. The power dissipation of CMOS full adder and SERF adder are 1.4312mW and 773.901uV. It is easy to see that SERF adder uses less space and has lower power consumption. These make the energy-recovery technique a promising candidate for low power design. In this paper there are some description about other CMOS adders which gives the comparison against each other too.

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