LAB: 1

TITLE: INTRODUCTION TO SCHEMATIC LOGIC DESIGN

Learning Outcomes:

At the end of the practical, student able to:

i. Explain schematic design using CPLD

ii. Explain function clocks (wave form) in digital computer.

iii. Use schematic CPLD to simulate digital output for SR, D, master slave and JK flip-flop.

iv. Design shift register using flip-flop JK.

Laboratory Equipment:

i. Computer

ii. Software Altera Max Plus II

BASIC FLIP FLOP

)Truth table: 2)The Karnaugh Map (K-Map)

Input Output a b Y Z0 0 0 00 1 0 11 0 0 11 1 1 1

3)The Boolean equations.

Y =ab

Z = a+b

0 10 0 01 0 1

0 10 0 11 1 1

SR NOR FLIP FLOP

Input OutputOperation

S R Q Q

1 0 1 0 Set

0 0 1 0 Hold

0 1 0 1 Reset

0 0 0 1 Hold

1 0 1 0 Set

1 1 0 1 Invalid

0 0 0 1 Hold

SR NAND FLIP FLOP

INPUT OUTPUTOPERATIONS R Q Q’

1 0 1 0 SET0 0 1 0 NO CHANGE0 1 0 1 RESET0 0 0 1 RESET1 0 1 0 SET1 1 0 1 INVALID0 0 0 1 NO CHANGE

JK FLIP FLOP

INPUT OUTPUTOPERATIONS R Q Q’

1 0 0 1 RESET0 0 1 0 INVALID0 1 1 0 SET0 0 1 0 NO CHANGE1 0 0 1 RESET1 1 0 1 NO CHANGE

0 0 1 0 INVALID

D FLIP FLOP

CLK INPUT OUTPUT OPERATION

J K Q Q’1 0 1 0 Set0 0 1 0 Hold0 1 0 1 Reset1 1 1 0 Toggle0 0 1 0 Hold0 1 0 1 Reset

0 0 0 1 Hold

MASTER SLAVE

CLKInput Output

OperationS R Q Q’ Y Y’

0 0 1 1 1 1

0 1 1 1 1 0

1 0 1 1 0 1

1 1 1 1 X X

0 0 X X 1 1

0 0 1 1 1 1

0 1 1 1 1 0

QUESTION…..

1. Basic Flip-flopI. Draw the logic circuit for an unclocked NOR gate flip-flop.

II. Enter the expected timing diagram for signals Q and Q' in Figure 26.

III.

Figure 26: NOR gate flip-flop timing diagram

IV. Draw the logic circuit for an unclocked NAND gate flip-flop.

V. Enter the expected timing diagram for signals Q and Q' in Figure 27.

Figure 27: NAND gate flip-flop timing diagram

2. Master Slave Flip-flop

i. Draw the logic circuit implemented with gates for the SR master-slave flip-flop in Figure 24. Use NOR gate flip-flops.

ii. Enter the expected timing diagram for the signals Y, Y', Q, and Q' in Figure 28.

Figure 28: SR master-slave flip-flop timing diagram

3. Edge triggered flip-flop

i. Draw the logic circuit for the D-type positive-edge triggered flip-flop in Figure 5.

ii. Enter the expected timing diagram for the signals S, R, Q, and Q' in Figure 29.

Figure 29: D-type edge triggered flip-flop timing diagram

CONCLUSION

What we can conclude in this practical lab ,we be able to explain the schematic design using CPL. After that ,we be able to explain the function clocks(waveform) in digital computer. Then , we can use the schematic CPLD to stimulate digital output for SR flip-flop,D flip-flop ,Master Slave flip-flop and JK flip-flop . More than that ,we know how to design shift register using flip-flop JK . We learn that a digital system can be represented at different levels of abstraction . This keeps the description and design of complex system manageable.Lastly, we managed to understand that the highest level of abstraction is the behavional level that describes a system in terms of what it does(or how it behaves) rather than in terms of its components and interconnection between them.