Artificial Intelligence Solutions for Verification ofAnalog and Mixed-Signal Smart Power Systems

Ramin M. Hasani1, Benjamin Kulnik1, Dieter Haerle2, Radu Grosu1

1Cyber-Physical Systems, TU Wien, Austria1KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, Villach, Austria

Correspondances to: ramin.hasani@tuwien.ac.at

Abstract

In this work, we explore novel artificial intelli-gence (AI) solutions for the verification of analogand mixed-signal (AMS) complex integrated cir-cuits (IC). The main target is to improve the timeperformance and the accuracy of the verificationprocess of AMS circuits. In this regard, we de-velop numerous neural network models for AMSICs, and utilize such models into the verificationprocess. We show that such methods can result ingaining up to two orders of magnitude speed-upin the fault-injection simulations of ICs. In termsof developmental-efficiency and automation perfor-mance, our AI modeling suite is superior over ex-isting methods.

1 IntroductionOne challenging issue in the verification process of analogand mixed signal (AMS) ICs is the development of highperformance models for carrying out time-efficient simula-tions. Transistor-level fault simulations of a single IC cantake up to one or two weeks to be completed. Figure 1A-leftshows the fast-fault-injection method (FFIM) where one canmodel some parts of the a complex IC with top-level mod-els and inject fault in the transistor-level of the small remain-ing part of the IC, in order to gain speed-ups in the fault-simulations. Figure 1B demonstrates an accuracy versus per-formance trade-off between various modeling approaches forthe FFIM. In the present study, we propose various neural net-work (NN) architectures for modeling parts or the entire Ana-log IC and illustrate their accuracy and time-performance.

2 MethodsNNs are designed in MATLAB and TensorFlow and were in-tegrated into Cadence design environment by the availableco-simulation toolboxes such as MATLAB/AMS DesignerCosimulation platform for the MATLAB NN models andInter-Process Communication for Python models. We nowdescribe various neural network architectures have been de-signed and to be designed:

2.1 NARX models of ICsWe introduced a black-box method for automatically learn-ing an approximate but simulation-time efficient high-levelabstraction of given analog integrated circuit (IC) in [Hasaniet al., 2016]. The learned abstraction consists of a non-linear auto-regressive neural network with exogenous input(NARX), which is trained and validated from the input-outputtraces of the IC stimulated with particular inputs. We showedthe effectiveness of such approach on the power-up behaviorand supply dependency of a CMOS band-gap reference cir-cuit (BGR) (See Figure 1D). The approach is scaleable to themodeling of overall behavior of an IC (See Figure 1E as anexample of the NARX network architecture).

2.2 Compositional Neural Network Models of ICsWe introduced a compositional method for the constructionof a neural-network (NN) capturing the dynamic behaviorof a complex analog multiple-input multiple-output (MIMO)system [Hasani et al., 2017]. The method first learns foreach input/output pair (i, O), see Figure 1A-right, a small-sized NARX network representing the transfer-function hiO.The training dataset is generated by varying input i of theMIMO, only. Then, for each output O, the transfer functionshiO are combined by a time-delayed neural network (TDNN)layer, fO. The training dataset for fO is generated by vary-ing all MIMO inputs. The final output is f =(f1, . . ., fn).The NN’s parameters are learned using Levenberg-Marquardtback-propagation algorithm. We applied our method to learnan NN abstraction of a BGR. First, we learned the NARXNNs corresponding to trimming, load-jump and line-jump re-sponses of the circuit. Then, we recomposed the outputs bytraining the second layer TDNN structure. We demonstratedthe performance of our learned NN in the transient simulationof the BGR by reducing the simulation-time by a factor of 17compared to the transistor-level simulations. Such methodallows us to map particular parts of the NN to specific behav-ioral features of the BGR.

2.3 MLP Models of ICsMultilayer-perceptrons were employed for modeling of aBGR, and illustrated remarkable accuracy on a test set. Fig-ure 1F shows the output of a BGR together with its 6-layeredtime-delayed neural nets (TDNN) response. Besides the

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Figure 1: Overview. A) left: fault injection method, middle: a CMOS bad-gap reference circuit (BGR), right: decompositionand recomposition of behavioral functions of a BGR, to be modeled by neural networks. B) A trade-of between accuracy andspeed performance of various AMS ICs’ modeling approaches. C) Sample architecture of a deep neural net. D) sample learnedbehavioral feature of a BGR by a NARX network. E) Single layer small-sized NARX network. F) sample output of an ICtogether with its neural network model after the training process to a test set.

high-level of accuracy, by using such models we gain a simu-lation speed-up with a factor of 20 up to 50 depending on thecircuit while maintaining a high level of accuracy.

2.4 LSTM models of Analog ICsWe are currently developing long short-term memory(LSTM) recurrent networks for modeling CMOS Oscillator,BGR and floating regulator circuits. Our aim is to achievemuch better accuracy compared to the previously developedmodels. Python models are being designed in TensorFlowand will be co-simulated in Cadence environment using Inter-Process Communication (IPC).

3 Next Steps• Developmet of more integrated circuit’s models by neu-

ral networks in order to assess the overall pros and consof the approach

• Trying various architectures of neural networks andbenchmark them against each other.

• Find an efficient procedure for inclusion of the NN mod-els into the Cadence design environment.

• Employ our neural network models into the actual ver-ification process of the AMS circuits and evaluate thetime-performance and fault-coverage rate of the method.

4 Final NoteArtificial intelligence and in particular deep learning solu-tions for various industrial applications is rapidly growingtowards providing smarter, safer and autonomous methods.Accordingly, within the next couple of years, an improvedversion of our approach is going to merge existing efficientmethods for the verification of AMS ICs into a global au-tonomous smart verification suit which will presumably turninto the common method for fast and reliable pre-silicon ver-ification of AMS integrated circuits.

References[Hasani et al., 2016] Ramin M Hasani, Dieter Haerle, and

Radu Grosu. Efficient modeling of complex analog in-tegrated circuits using neural networks. In the 12th Con-ference on Ph. D. Research in Microelectronics and Elec-tronics (PRIME), pages 1–4. IEEE, 2016.

[Hasani et al., 2017] Ramin M Hasani, Dieter Haerle, Chris-tian F. Baumgartner, Alessio R. Lomuscio, and RaduGrosu. Compositional neural-network modeling of com-plex analog circuits. In Accepted at the 30th InternationalJoint Conference on Neural Networks (IJCNN). IEEE,2017.