ARM Architecture Subroutine and Flags

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SUBROUTINES & FLAGS

Transcript of ARM Architecture Subroutine and Flags

Page 1: ARM Architecture Subroutine and Flags

SUBROUTINES & FLAGS

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GROUP MEMBERS: UBAID UR REHMAN (FA13-BSE-055) ABDULLAH HAMEEDULLAH (FA13-BSE-073) MUBASHER YOUNAS (FA13-BSE-112) BILAL AHMED (FA13-BSE-076) SHAKIR ULLAH (FA13-BSE-082)

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DEFINITIONS & TERMINOLOGIES

Routine, subroutine: A block of code that performs a task based on some

arguments and optionally returns a result. Routine is used for clarity where there are nested calls:

a routine is the caller and a subroutine is the callee.

Procedure: A routine that returns no result value. Function: A routine that returns a result value. Intrinsic Functions: Which are part of the language.User defined Funcs.: By which we extend language.

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DEFINITIONS & TERMINOLOGIES

Parameter: A variable in the declaration of function.

Argument: The actual value of this variable that gets passed to function

Variadic routine: No. of args. & their type, determined by caller instead of the callee.

Subroutines collectively with functions are named procedures.(1)

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DEFINITIONS & TERMINOLOGIES

Procedure(subroutine) provide a very powerful extension to language by: Breaking down into simpler problems. Avoiding us to concentrate one aspect of prob. At a time. Avoiding duplication of code. Hiding away messy code so that a main program is a

sequence of calls to procedure and so on… Types of Functions: No return type & no parameters, return type & no parameters, no return type & parameters, no return type no parameters.

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DEFINITIONS & TERMINOLOGIES(CONT.) To Implement Subroutines we must have some information about flags.Global register: A register whose value is neither saved nor

destroyed by a subroutine. (may be updated)

Program state: The state of the program’s memory, including values in machine registers.

Scratch register, temporary register: A register used to hold an intermediate value during a calculation (limited lifetime).

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ARM REGISTERSVariable register, v-register: A register used to hold the value of

a variable, usually one local to a routine, and often named in the source code.

ARM Registers In all ARM processors, the following registers are available and accessible in any processor mode: 13 general-purpose registers R0-R12 1 Stack Pointer (SP) 1 Link Register (LR) 1 Program Counter (PC) 1 Application Program Status Register (APSR)

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REGISTERS R0-R3(4 Registers): Used to pass arguments to subroutines & R0

to pass a result back to the callers.R9 (Base Register): Holds the Address.LDM & STM(Load or Store Multiple Instructions): Load (Store) any

subset of the 16(r0 to r15) general-purpose registers from (to) memory, using a single instruction.

A single LDM instruction can load up to 16 registers from memory using only a single instruction rather than 16 individual LDR instructions.

Execute time also shortens, since only one instruction must be fetched from memory.

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REGISTERS(CONT.)Syntaxop{addr_mode}{cond} Rn{!}, reglist{^} where: op can be either:CONDITION FLAGS & CODESLDM Load Multiple registers.STM Store Multiple registers.addr_mode is any one of the following:IA Increment address After each transfer. This is the default, and can be omitted.IB Increment address Before each transfer (ARM only).DA Decrement address After each transfer (ARM only).DB Decrement address Before each transfer.

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REGISTERS (CONT.)cond is an optional condition code.Rn is a base register, the ARM register holding the address for transfer. Rn must not be r15.! is an optional suffix. If !  is present, the final address is written back into Rn.reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. SPSR: (State program status register) The SPSR is used to store the current value of the CPSR when an exception is taken so that it can be restored after handling the exception. Each exception handling mode can access its own SPSR. User mode and System mode do not have an SPSR because they are not exception handling modes.

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CALLING SUBROUT

INEA subroutine is a block of code that performs a task based on some arguments and optionally returns a result. By convention, registers R0 to R3 are used to pass arguments to subroutines, and R0 is used to pass a result back to the callers. A subroutine that needs more than 4 inputs uses the stack for the additional inputs.

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CALLING SUBROUTINES (CONT.)

To call subroutines, use a branch and link instruction. The syntax is:BL destinationWhere destination  is usually the label on the first instruction of the subroutine.

The BL  Instruction: Places the return address in the link register sets the PC to

the address of the subroutine. After the subroutine code is executed you can use a BX

LR instruction to return.

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CALLING SUBROUTINES (CONT.) Data or addresses can be move into or out a subroutine , and these values are called parameters. These can be passed to a subroutine through registers, memory or stack. We’ll se what the trade-offs and requirements are for the different approaches, starting with the use of registers. Passing Parameters in Registers The registers are an ideal place

to pass value parameters to a procedure. If you are passing a single parameter to a procedure The base standard provides for passing arguments in core registers (r0-r3) and on the stack. For subroutines that take a small number of parameters, only registers are used, greatly reducing the overhead of a call. Parameter passing is defined as a two-level conceptual model.

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PASSING PARAMETERS(CONT.) A mapping from a source language argument onto a machine type The marshalling of machine types to produce the final parameter

list The mapping from the source language onto the machine type is specific for each language and is described separately (the C and C++ language bindings are described in §7, ARM C and C++ language mappings). The result is an ordered list of arguments that are to be passed to the subroutine. In the following description there are assumed to be a number of co-processors available for passing and receiving arguments. The co-processor registers are divided into different classes. An argument may be a candidate for at most one co-processor register class. An argument that is suitable for allocation to a co- processor register is known as a Co-processor Register Candidate (CPRC).

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PASSING PARAMETERS(CONT.) In the base standard there are no arguments that are candidates for a co-processor register class. A variadic function is always marshaled as for the base standard. For a caller, sufficient stack space to hold stacked arguments is assumed to have been allocated prior to marshaling: in practice the amount of stack space required cannot be known until after the argument marshalling has been completed. A callee can modify any stack space used for receiving parameter values from the caller. When a Composite Type argument is assigned to core registers (either fully or partially), the behavior is as if the argument had been stored to memory at a word-aligned (4-byte) address and then loaded into consecutive registers using a suitable load-multiple instruction.

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PASSING PARAMETERS(CONT.) Stage A – Initialization This stage is performed exactly once, before processing of the arguments commences. A.1 The Next Core Register Number (NCRN) is set to r0. A.2 Co-processor argument register initialization is performed. A.3 The next stacked argument address (NSAA) is set to the current stack-pointer value (SP). A.4 If the subroutine is a function that returns a result in memory, then the address for the result is placed in r0 and the NCRN is set to r1. Stage B – Pre-padding and extension of arguments For each argument in the list the first matching rule from the following list is applied.

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PASSING PARAMETERS(CONT.) B.1 If the argument is a Composite Type whose size cannot be statically determined by both the caller and callee, the argument is copied to memory and the argument is replaced by a pointer to the copy. B.2 If the argument is an integral Fundamental Data Type that is smaller than a word, then it is zero- or sign-extended to a full word and its size is set to 4 bytes. If the argument is a Half-precision Floating Point Type it is converted to Single Precision. B.3.cp If the argument is a CPRC then any preparation rules for that co-processor register class are applied. B.4 If the argument is a Composite Type whose size is not a multiple of 4 bytes, then its size is rounded up to the nearest multiple of 4.

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CONDITION FLAGS & CODESThe Instruction Set: ARM provides by way of memory and

registers, and the sort of instructions to manipulate them.ARM instructions are 32 bits long Here is a typical one:

10101011100101010010100111101011 Fortunately, we don't have to write ARM programs using such codes. Instead we use assembly languageUsually, mnemonics are followed by one or more operands which

are used to completely describe the instruction. An example mnemonic is ADD, for 'add two registers'.  

If the left and right hand side of the addition are R1 and R2 respectively, and the result is to go in R0, the operand part would be written R0,R1,R2.  Thus the complete add instruction, in assembler format, would be: ADD R0, R1, R2 ;R0 = R1 + R2

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CONDITION FLAGS & CODESMost ARM mnemonics consist of three letters,

e.g. SUB, MOV, ADD. Condition Codes:ARM, like many other architectures, implements conditional

execution using a set of flags which store state information about a previous operation.

There are four bits of condition encoded into an instruction word. This allows sixteen possible conditions. 

 If the condition for the current instruction is true, the execution goes ahead. If the condition does not hold, the instruction is ignored and the next one executed.

The result flags are altered mainly by the data manipulation instructions.  For example, a MOV instruction which copies the contents of one register to another. No flags are affected. However, the MOVS (move with Set) instruction additionally causes the result flags to be set.

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CONDITIONS FLAGS & CODES

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CONDITION FLAGS & CODESTo make an instruction conditional, a two-letter suffix is added to

the mnemonic. AL Always: An instruction with this suffix is always executed. To

save having to type 'AL' after the majority of instructions which are unconditional, the suffix may be omitted in this case. Thus ADDAL and ADD mean the same thing: add unconditionally.

NV Never: All ARM conditions also have their inverse, so this is the inverse of always. Any instruction with this condition will be ignored. Such instructions might be used for 'padding' or perhaps to use up a (very) small amount of time in a program.

EQ Equal: This condition is true if the result flag Z (zero) is set. This might arise after a compare instruction where the operands were equal, or in any data instruction which received a zero result into the destination.

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CONDITION FLAGS & CODES NE Not equal: This is clearly the opposite of EQ, and is true if

the Z flag is cleared. If Z is set, and instruction with the NE condition will not be executed.

VS Overflow set: This condition is true if the result flag V (overflow) is set. Add, subtract instructions affect the V flag.

VC Overflow clear: The opposite to VS. MI Minus: Instructions with this condition only execute if the N

(negative) flag is set. Such a condition would occur when the last data operation gave a result which was negative. That is, the N flag reflects the state of bit 31 of the result. (All data operations work on 32-bit numbers.)

PL Plus: This is the opposite to the MI condition and instructions with the PL condition will only execute if the N flag is cleared.

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CONDITION FLAGS & CODES The next four conditions are often used after comparisons of two

unsigned numbers. If the numbers being compared are n1 and n2, the conditions are n1>=n2, n1<n2, n1>n2 and n1<=n2, in the order presented.

CS Carry set: This condition is true if the result flag C (carry) is set. The carry flag is affected by arithmetic instructions such as ADD, SUB and CMP. It is also altered by operations involving the shifting or rotation of operands (data manipulation instructions).

When used after a compare instruction, CS may be interpreted as 'higher or same', where the operands are treated as unsigned 32-bit numbers. For example, if the left hand operand of CMP was 5 and the right hand operand was 2, the carry would be set. You can use HS instead of CS for this condition.

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CONDITION FLAGS & CODES CC Carry clear: This is the inverse condition to CS. After a

compare, the CC condition may be interpreted as meaning 'lower than', where the operands are again treated as unsigned numbers. An synonym for CC is LO.

HI Higher: This condition is true if the C flag is set and the Z flag is false. After a compare or subtract, this combination may be interpreted as the left hand operand being greater than the right hand one, where the operands are treated as unsigned.

LS Lower or same: This condition is true if the C flag is cleared or the Z flag is set. After a compare or subtract, this combination may be interpreted as the left hand operand being less than or equal to the right hand one, where the operands are treated as unsigned.

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CONDITION FLAGS & CODES The next four conditions have similar interpretations to the previous four, but are used when signed numbers have been compared. The difference is that they take into account the state of the V (overflow) flag, whereas the unsigned ones don't. Again, the relationships between the two numbers which would cause the condition to be true are n1>=n2, n1<n2, n1>n2, n1<=n2. GE Greater than or equal: This is true if N is cleared and V is

cleared, or N is set and V is set. LT Less than: This is the opposite to GE and instructions with

this condition are executed if N is set and V is cleared, or N is cleared and V is set.

GT Greater than: This is the same as GE, with the addition that the Z flag must be cleared too.

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CONDITION FLAGS & CODES LE Less than or equal This is the same as LT, and is also true whenever the Z flag is set. Note: although the conditions refer to signed and unsigned numbers, the operations on the numbers are identical regardless of the type. The only things that change are the flags used to determine whether instructions are to be obeyed or not. The flags may be set and cleared explicitly by performing operations directly on R15, where they are stored.

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