Arithmetic logic and Verilogtinoosh/cmpe650/slides/subtract-mult.pdfVerilog Digital Design...
Transcript of Arithmetic logic and Verilogtinoosh/cmpe650/slides/subtract-mult.pdfVerilog Digital Design...
Arithmetic logic and Verilog
CMPE 415
Verilog
B. Baas, © 2011 EEC 281 2
Subtraction
Essentially the same hardware as an adder
A – B = A + (-B)
Recall that for 2’s complement numbers, -B = (~B) + 1
So now we haveA – B = A + (~B) + 1
Verilog
B. Baas, © 2011 EEC 281 3
Subtraction
Often easy to find a place to add in a ―1‖ in the lsb position
adder
A – B
00000001A ~B
adder
A – B
cin = 1
A ~B
Verilog
Digital Design — Chapter 3 — Numeric Basics 4
Adder/Subtracter Circuits
Adder can be any of those we have seen
depends on constraints
y0
y1
yn–1
y0
c0
cn
y1
yn–1
…
…
…
…
x0
x1
xn–1
x0
x1
xn–1
… s0
s1
sn–1
sn–1
/dn–1
s1/d
1s
0/d
0
…
adder
add/sub
ovf/unf
(mode)
Verilog
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Subtraction in Verilog
module adder_subtracter ( output [12:0] s,input [11:0] x, y,input mode );
assign {s} = !mode ? (x + y) : (x - y);
endmodule
When mode=0 => adds
else subtracts
Verilog
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Verilog
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Verilog
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Equality Comparison
XNOR gate: equality of two bits
Apply bitwise to two unsigned numbers
assign eq = x == y;
In Verilog, x == y gives
a bit result
1'b0 for false, 1'b1 for true
x0
eq…
y0
x1
y1
xn–1
yn–1
…
Verilog
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Verilog
Digital Design — Chapter 3 — Numeric Basics 10
Verilog
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Verilog
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Verilog
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Verilog
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Inequality Comparison
Magnitude comparator for x > yx
n–1
gt
xn–1
> yn–1
xn–1
= yn–1
xn–2
> yn–2
xn–2
= yn–2
yn–1
xn–2
yn–2
x1 > y
1
x1…0
> y1…0
xn–2…0
> yn–2…0
x1 = y
1
x1
y1
x0 > y
0x
0
y0
……
…
Verilog
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Comparison Example in Verilog
Thermostat with target termperature
Heater or cooler on when actual temperature is more than 5° from target
module thermostat ( output heater_on, cooler_on,input [7:0] target, actual );
assign heater_on = actual < target - 5;assign cooler_on = actual > target + 5;
endmodule
Verilog
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Scaling by Power of 2
This is x shifted left k places, with k bits
of 0 added on the right
logical shift left by k places
e.g., 000101102 × 23 = 000101100002
Truncate if result must fit in n bits
overflow if any truncated bit is not 0
0
0
2
2
1
1 222 xxxx n
n
n
n
01
0
2
2
1
1 2)0(202222
kknk
n
nk
n
k xxxx
Verilog
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Scaling by Power of 2
This is x shifted right k places, with k
bits truncated on the right
logical shift right by k places
e.g., 011101102 / 23 = 011102
Fill on the left with k bits of 0 if result must fit in n bits
0
0
2
2
1
1 222 xxxx n
n
n
n
k
kk
kn
n
kn
n
k xxxxxx
222222/ 0
1
1
02
2
1
1
Verilog
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Scaling in Verilog
Shift-left (<<) and shift-right (>>) operations
result is same size as operand
assign y = s << 2;
s = 000100112 = 1910
y = 010011002 = 7610
assign y = s >> 2;
s = 000100112 = 1910
y = 0001002 = 410
Verilog
B. Baas, © 2011 EEC 281 19
Multipliers
Widely used in DSP processors, less so in general-purpose processors
Hardware is typically done the same as you would do it with paper and pencil
Partial products are copies of the multiplicand AND’d by bits of the multiplier
<draw picture in notes>
Verilog
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Multipliers 3 Main Steps
Generate partial products
Reduce the partial product array (normally using carry-save addition)
Linear array addition
Tree addition (Wallace tree)
Final adder
Convert carry-save form to single word form
Whichever one you like, probably a faster one
Carry-propagate adder (CPA)
Verilog
Array Multiplier
Verilog
Serial Multiplier
Adds one per cycle
Requires writing state machines
Verilog
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Unsigned Multiplication
yi x 2i is called a partial product
if yi = 0, then yi x 2i = 0
if yi = 1, then yi x 2i is x shifted left by i
Combinational array multiplier AND gates form partial products
adders form full product
0
0
2
2
1
1
0
0
2
2
1
1
222
222
xyxyxy
yyyxxy
n
n
n
n
n
n
n
n
Verilog
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Unsigned Multiplication
Adders can be any of those we have seen
Optimized multipliers combine parts of adjacent adders
x0
y1
x1
xn–1
y0
c0
cn
y1
yn–1
yn–2
…
……
xn–2
x0
x1
xn–2
… s0
s1
s2
xn–1
…
sn–1
… s1
s2
…
… … …
sn–1
adder
x0
y2
x1
xn–1
y0
c0
cn
y1
yn–1
yn–2
…
…
…
…
xn–2
x0
x1
xn–2
s0
xn–1
…
adder
… s1
s2
…
sn–1
x0
y0
x1
xn–1
y0
c0
cn
y1
yn–1
yn–2
…
…
…
…
xn–2
x0
x1
xn–2
s0
xn–1
adder
… s1
s2
…
sn–1
x0
yn–1
x1
xn–1
y0
c0
cn
y1
yn–1
yn–2
…
…
…
…
xn–2
p0
p1
p2
pn–1
pn
pn+1
p2n–2
p2n–1
x0
x1
xn–2
s0
xn–1
adder
Verilog
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Product Size
Greatest result for n-bit operands:
1221222)12)(12( 122 nnnnnnn
Requires 2n bits to avoid overflow
Multiplying n-bit and m-bit operands
requires n + m bits
wire [ 7:0] x; wire [13:0] y; wire [21:0] p;...
assign p = {14'b0, x} * {8'b0, y};
assign p = x * y; // implicit resizing
Verilog
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Verilog
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Verilog
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Verilog
B. Baas, © 2011 EEC 281 29
Reset-able and Enable-able Registers
Use reset-able FFs only where needed
FFs are a little larger and higher power
Requires the global routing of the high-fanout reset signal
cos()
x +reset only these two registers, but now
reset must be enabled for at least
3 clock cycles
reset
R
R
Verilog
B. Baas, © 2011 EEC 281 30
Three types of ―case‖ statements in verilog
1) case
− Normal case statement
2) casez
− Allows use of wildcard ―?‖ character for don’t cares.casez(in)
4’b1???: out = a;
4’b01??: out = b;
4’b00??: out = c;
default: out = d;
endcase
3) casex
Don’t use it. Could use ―z‖ or ―x‖ logic.
default
Normally set output to an easily-recognizable value (such as x’s) in a default statement to make mistakes easier to spot
Verilog
B. Baas, © 2011 EEC 281 31
Hardwired Complex Functions
Complex or ―arbitrary‖ functions are not uncommon
Examples
sin/cos
tangent-1
logsin/costheta
out_real
out_imag
Verilog
B. Baas, © 2011 EEC 281 32
Hardwired Function in Verilog using a Lookup Table
always @(input) begincase (input)4’b0000: begin real=3’b100; imag=3’b001; end4’b0001: begin real=3’b000; imag=3’b101; end4’b0010: begin real=3’b110; imag=3’b011; end
...default: begin real=3’bxxx; imag=3’bxxx; endendcase
end
Often best to write a matlab program to write the verilog table as plain text You will need several versions to get it right Easy to adapt to other specifications
Not efficient for very large tables Tables with data that is less random will have
smaller synthesized area