Architecture des ordinateurs : Bibliographie · Philippe Darche : Architecture des ordinateurs -...

Chapitre 1

Introduction : la fonction de mémorisation

[ANSI/IEEE 91]“IEEE Standard for Test Procedures for Magnetic Cores”. IEEE Std 393-1991 (Revision of IEEE Std 393-1977). Approved June 27,1991.[Bardeen and Brattain 48]J. Bardeen and W. H. Brattain : “The Transistor, A Semiconductor Triode”. Physical Review, Vol. 74, N° 2, pp. 230-231. July 15, 1948. Reprinted in [IEEE 98], pp. 29-30.[Bashe et al. 86 89 03]Charles J. Bashe, Lyle R. Johnson, John H. Palmer and Emerson W. Pugh : IBM's Early Computers. Fourth edition. The MIT Press 2003. ISBN-10: 0262523930 and ISBN-13: 978-0262523936.[Beaulieu 02]Norman C. Beaulieu : “Introduction to 'Certain topics in telegraph transmission theory'”. Pro-ceedings of the IEEE, Vol. 90, N° 2, pp. 276-279. February 2002.[Belady et al. 81]L. A. Belady, R. P. Parmelee and C. A. Scalzi : “The IBM History of Memory Management Tech-nology”. IBM Journal of Research and Development, Vol. 25, N° 5, pp. 491-504. September 1981.[Bell et al. 78]“Computer Engineering : A DEC View of Hardware Systems Design”. C. Gordon Bell, J. Craig Mudge and John E. McNamara Editors. 1978.[Boland and Dollas 94]Keith Boland and Apostolos Dollas : “Predicting and Precluding Problems with Memory Latency”. IEEE Micro, Vol. 14, N° 4, pp. 59-67. August 1994.[Bornhauser 64]Hans Bornhauser : “Core Storage Matrix”. United States (US) Patent N° 3154763. Filing Date: July 10, 1957. Publication Date: October 27, 1964.[Burks 47]Arthur W. Burks : “Electronic Computing Circuits of the ENIAC”. Proceedings of IRE, Vol. 35, N° 8, pp. 756-767. August 1947. Reprinted in [Burks 97].[Burks 97]Arthur W. Burks : “Electronic Computing Circuits of The ENIAC”. Proceedings of the IEEE, Vol. 85, N° 7, pp. 1172-1182. July 1997.

Introduction : la fonction de mémorisation2

[Chen and Patterson 93]P. M. Chen and D. A. Patterson : “Storage Performance-Metrics and Benchmarks”. Proceedings of the IEEE, Vol. 8, N° 9, pp. 1151-1165. September 1993.[Chisvin and Duckworth 89]L. Chisvin and R. J. Duckworth : “Content-Addressable and Associative Memory: Alternatives to the Ubiquitous RAM”. IEEE Computer, Vol. 22, N° 7, pp. 51-64. July 1989.[Chu and Klein 52]J. C. Chu and R. J. Klein : “Williams Tubes Selection Program”. Proceedings of the 1952 ACM National Meeting, pp. 110-114. 1952. Meeting Location: Toronto, Ontario, Canada.[Ciminiera and Valenzano 87]Luigi Ciminiera and Adriano Valenzano : Advanced Microprocessor Architectures. Electronic Systems Engineering Series. Addison-Wesley Publishing Co. 1987. ISBN 0-201-14550-2.[Cohen et al. 89]E. I. Cohen, G. M. King and J. T. Brady : “Storage Hierarchies”. IBM Systems Journal, Vol. 28, N° 1, pp. 62-76. 1989.[Darche 00]Philippe Darche : Architecture des ordinateurs - Représentation des nombres et codes - Cours avec exercices corrigés. Collection Support IUT. Édition Gaëtan Morin. Novembre 2000. ISBN 2-910749-49-5. 388 pages.[Darche 02]Philippe Darche : Architecture des ordinateurs - Fonctions booléennes, logiques combinatoire et séquentielle - Cours avec exercices et exemples en VHDL. Édition Vuibert. Mars 2002. ISBN 2-7117-8688-9. 360 pages.[Darche 03]Philippe Darche : Architecture des ordinateurs - Interfaces et périphériques - Cours avec exercices corrigés. Éditions Vuibert. Juin 2003. ISBN 2-7117-4814-6. 416 pages.[Darche 04]Philippe Darche : Architecture des ordinateurs - Logique booléenne : implémentations et technologies. Édi-tions Vuibert. Novembre 2004. ISBN 2-7117-4821-9. 284 pages[Dewilde and Vandewalle 92]Computer Systems and Software Engineering: State-Of-The-Art. Edited by Patrick Dewilde and Joos Vandewalle. Kluwer Academic Publishers 1992. ISBN: 0-7923-1718-1.[Eccles and Jordan 19]W. H. Eccles and F. W. Jordan : “A Trigger Relay Utilizing Three-electrode Thermionic Vacuum Tubes”. The Radio Review, Vol. 1, pp. 143-146. December 1919.[Eckert 49]J. Presper Eckert, Jr. : “An Electrostatic Memory System”. Proceedings of a Second Symposium on Large-Scale Digital Calculating Machinery, Vol. XXVI, pp. 32-43. Symposium Date: 13-16 September 1949. The Annals of the Computation Laboratory of Harvard University, Harvard University Press. Cambridge, Massachusetts 1951.[Eckert 53]J. Presper Eckert, Jr. : “A Survey of Digital Computer Memory Systems”. Proceedings of the IRE, Vol. 41, N° 10, pp. 1393-1406. October 1953. Reprinted in Annals of the History of Com-puting, Vol. 20, N° 4, pp. 15-28. April 1998. Also reprinted in Proceedings of the IEEE, Vol. 85, N° 1, pp. 184-197. January 1997. Voir aussi [Schneck 97].[Eveleth 65]J. H. Eveleth : “A Survey of Ultrasonic Delay Lines Operating Below 100 Mc/s”. Proceedings of the IEEE, Vol. 53, N° 10, pp. 1406-1428. October 1965.

Bibliographie 3

[Forrester 51]Jay W. Forrester : “Digital Information Storage in three Dimensions Using Magnetic Cores”. Journal of Applied Physics, Vol. 22, N° 1, pp. 44-48. January 1951.[Forrester 56]Jay W. Forrester: “Multicoordinate Digital Information Storage Device”. United States (US) Pat-ent N° 2736880. Filing Date: May 11, 1951. Publication Date: February 28, 1956.[Godfrey and Hendry 93]M. D. Godfrey and D. F. Hendry : “The Computer as von Neumann Planned it”. Annals of the History of Computing, vol. 15, N° 1, pp. 11-21. January-March 1993. In CD-ROM of [Shriver and Smith 98].[Greifer 69]Aaron P. Greifer : “Ferrite Memory Materials”. IEEE Transactions on Magnetics, Vol. 5, N° 4, pp. 774-811. December 1969.[Grossman 85]C. P. Grossman : “Cache-DASD Storage Design for Improving System Performance”. IBM Sys-tems Journal, Vol. 24, N° 3-4, pp. 316-334. 1985.[Hake and Homberg 90]J.-F. Hake and W. Homberg : “The Impact of Memory Organization on the Performance of Matrix Multiplication”. Proceedings of Supercomputing '90, pp. 34-40. Conference Date: 12-16 November 1990.[Handy 98]Jim Handy : The Cache Memory Book. Second Edition (First Edition in 1993). Academic Press 1998. ISBN 0-12-322980-4. [IEC 00]“Letter symbols to be used in electrical technology - Part 2: Telecommunications and electronics - Symboles littéraux à utiliser en électrotechnique - Partie 2 : Télécommunications et électro-nique”. International Electrotechnical Commission. IEC 60027-2 - Edition 2.0 - Bilingual. November 22, 2000.[IEEE 96a]IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink). IEEE Std 1596.4-1996. Approved March 19, 1996. ISBN 1-55937-745-3.[IEEE 98]“Special Issue: 50th Anniversary of the Transistor!”. Proceedings of the IEEE, Vol. 86, N° 1. January 1998.[IEEE 02a]“Draft Standard for Prefixes for Binary Multiples”. IEEE Std P1541/D5. The Institute of Elec-trical and Electronics Engineers. New York, United States of America (USA). 18 April 2002.[IEEE 02b]IEEE Std 1541-2002 : IEEE Standard for Prefixes for Binary Multiples. 2002. ISBN 0-7381-3386-8.[IEEE Spectrum 00]“A Backward Glance. Arriving at the Punched-Card System”. IEEE Spectrum, Vol. 37, N° 2, pp. 58-61. February 2000.[ Julian and Samuel 49]R. S. Julian and A. L. Samuel : “Coördinate Tubes for Use with Electrostatic Storage Tubes”. Proceedings of a Second Symposium on Large-Scale Digital Calculating Machinery, Vol. XXVI, pp. 96-114. Symposium Date: 13-16 September 1949. The Annals of the Computation Labora-tory of Harvard University, Harvard University Press. Cambridge, Massachusetts 1951.


[Kaneko 74]T. Kaneko : “Optimal Task Switching Policy for a Multilevel Storage System”. IBM Journal of Research and Development, Vol. 18, N° 4, pp. 310-315. July 1974.[Katayama 97]Yasunao Katayama : “Trends in Semiconductor Memories”. IEEE Micro, Vol. 17, N° 6, pp. 10-17. November/December 1997.[Kistermann 91]F. W. Kistermann : “The Invention and Development of the Hollerith Punched Card: In Com-memoration of the 130th Anniversary of the Birth of Herman Hollerith and for the 100th Anni-versary of Large Scale Data Processing”. IEEE Annals of the History of Computing, Vol. 13, N° 3, pp. 245-259. July-September 1991.[Kistermann 05]F. W. Kistermann : “Hollerith Punched Card System Development (1905-1913)”. IEEE Annals of the History of Computing, Vol. 27, N° 1, pp. 56-66. January-March 2005.[Knoll and Kazan 52]Max Knoll and Benjamin Kazan : “Storage Tubes and Their Basic Principles”. pp. 92-96. John Wiley and Sons, Inc. 1952.[Marguin 94]Jean Marguin : Histoire des instruments et machines à calculer, Trois siècles de mécanique pensante, 1642-1942. Éditions Hermann. 1994. ISBN 2-7056-6166-3.[Meinadier 71 88]Jean-Pierre Meinadier : Structure et Fonctionnement des Ordinateurs. Série Informatique. Librairie Larousse. Paris 1971 et 1988. ISBN 2-03-851065-2.[Nakagomi 93]T. Nakagomi, M. Holzbach, R., III, Van Meter and S. Ranade : “Re-Defining the Storage Hierar-chy: an Ultra-Fast Magneto-Optical Disk Drive”. Proceedings of the Twelfth IEEE Symposium on Mass Storage Systems : “Putting all that Data to Work”, pp. 267-274. Symposium Date: 26-29 April 1993.[von Neumann 45]John von Neumann : “First Draft of a Report on the EDVAC”. Contract N° W-670-ORD-4926Moore School of Electrical Engineering, University of Pennsylvania. June 30, 1945. See also [Godfrey and Hendry 93]. In CD-ROM of [Shriver and Smith 98].[Nyquist 28]Harry Nyquist : “Certain Topics in Telegraph Transmission Theory”. Transactions of the Amer-ican Institute of Electrical Engineers (AIEE), Vol. 47, N° 2, pp. 617-644. April 1928. Reprinted in Proceedings of the IEEE, vol. 90, N° 2, pp. 280-305. February 2002. See also [Beaulieu 02].[O'Brien 10]Frank O'Brien : The Apollo Guidance Computer: Architecture and Operation. Springer Praxis Books Series / Space Exploration. Springer and Praxis Publishing. ISBN-13: 978-1441908766. Septem-ber 2010.[Patterson et al. 97]David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Kimberly Keeton, Christoforos Kozyrakis, Randi Thomas and Katherine Yelick : A case for intelligent RAM: IRAM”. IEEE Micro, Vol. 17, N° 2, pp. 34-44. Mars/April 1997.[Proebster 92]Walter E. Proebster : “The Evolution of Data Memory and Storage: An Overview”. In [Dewilde and Vandewalle 92], pp. 1-23. 1992.[Przybylski 96]

Bibliographie 5

Steven A. Przybylski : “SDRAMs Ready to Enter PC Mainstream”. Microprocessor Report, Vol. 10, N° 6, pp. 17-23. May 6, 1996.[Pugh 71]Emerson W. Pugh : “Storage Hierarchies: Gaps, Cliffs, and Trends”. IEEE Transactions on Magnetics, Vol. 7, N° 4, pp. 810-814. December 1971.[Pugh et al. 81]E. W. Pugh, D. L. Critchlow, R. A. Henle and L. A. Russell : “Solid State Memory Development in IBM”. IBM Journal of Research and Development, Vol. 25, N° 5, pp. 585-602. September 1981.[Pugh 84b]Emerson W. Pugh : Memories That Shaped an Industry. The MIT Press 1984. ISBN-10: 0262160943 and ISBN-13: 978-0262160940.[Puthuff 78]Steven H. Puthuff : “Technical Innovations in Information Storage and Retrieval”. IEEE Trans-actions on Magnetics, Vol. 14, N° 4, pp. 143-148. July 1978.[Rajan 09]Suresh Rajan : “Integrated Memory Core and Memory Interface Circuit”. United States (US) Patent N° 7515453. Application Number: 11/474075. Filing Date: June 23, 2006. Publication Date: April 07, 2009.[Rajchman 48]Jan Rajchman : “The Selectron - a Tube for Selective Electrostatic Storage”. Proceedings of a Symposium on Large-Scale Digital Calculating Machinery, pp. 133-135. January 1948. Harvard University Press. Cambridge, Massachusetts.[Rajchman 49]Jan Rajchman : “The Selectron”. Proceedings of a Second Symposium on Large-Scale Digital Calculating Machinery, Vol. XXVI, pp. 365-373. Symposium Date: 13-16 September 1949. The Annals of the Computation Laboratory of Harvard University, Harvard University Press. Cam-bridge, Massachusetts 1951.[Rajchman 51]Jan Rajchman : “The Selective Electrostatic Storage Tube”. RCA Review, Vol. XII, N° 1, pp. 53-97. March 1951.[Rajchman 57]Jan A. Rajchman : “A Survey of Magnetic and Other Solid-State Devices for the Manipulation of Information”. IRE Transactions on Circuit Theory, Vol. 4, N° 3, pp. 210-225. September 1957.[Rege 76]S. L. Rege : “Cost, Performance and Size Tradeoffs for Different Levels in Memory Hierachy”. Proceedings of the 3rd Annual International Symposium on Computer Architecture (ISCA '76), pp. 64-67, 67A-67D. January 19-21, 1976.[Schmitt 88]William F. Schmitt : “The UNIVAC Short Code”. Annals of the History of Computing, Vol. 10, N° 1, pp. 7-18. January 1988.[Schneck 97]Paul B. Schneck : “Introduction to the Classic Paper : ’A Survey of Digital Computer Memory Systems’ [Eckert 53]”. Proceedings of the IEEE, Vol. 85, N° 1, pp. 181-183. January 1997.[Scrupski 01]Steve Scrupski : “Thin-Film Memory Gives Fast Output”. Electronic Design, Vol. 49, p. 50. August 20, 2001.[Self 99]Kevin Self : “Memory in megabytes and/or mebibytes”. IEEE Spectrum, Vol. 36, N° 8, p. 18.


August 1999.[Shannon 48]Claude Elwood Shannon : “A Mathematical Theory of Communication”. The Bell System Tech-nical Journal, vol. 27, pp. 379. 1949. Réimprimé dans [Shannon 93].[Shannon 93]Claude Elwood Shannon, Collected Papers. Edited by N. J. A. Sloane and Aaron D. Wyner. IEEE PRESS 1993. ISBN 0-7803-0434-9.[Shriver and Smith 98]Bruce Shriver and Bennett Smith : The Anatomy of a High-Performance Microprocessor: A Systems Per-spective. IEEE Press 1998. ISBN 0-8186-8400-3.[Wang and Woo 50]An Wang and Way Dong Woo : “Digital Information Storage in three Dimensions Using Mag-netic Cores”. Journal of Applied Physics, Vol. 21, N° 1, pp. 49-54. January 1950.[Wang 55]An Wang : “Pulse Transfer Controlling Device”. United States (US) Patent N° 2708722. Filing Date: October 21, 1949. Publication Date: May 17, 1955.[Williams 73]John G. Williams : “Asymmetric Memory Hierarchies”. Communications of the ACM (CACM), Vol. 16, N° 4, pp. 213-222. April 1973.[Williams 97]Michael Roy Williams : A History of Computing Technology. Second Edition. IEEE Computer Soci-ety Press. ISBN 0-8186-7739-2.[Zilberstein 65]R. M. Zilberstein : “Variable Ultrasonic Delay Line”. Correspondence. Proceedings of the IEEE, Vol. 53, N° 6, pp. 637-637. June 1965.

Chapitre 2

Organisation générale d’une mémoire à semi-conducteurs à accès aléatoire

[Ahn et al. 09a]Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber and Norman P. Jouppi : “Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs”. IEEE Com-puter Architecture, Vol. 8, N° 1, pp. 5-8. January-June 2009.[Ahn et al. 09b]Jung Ho Ahn, Norman P. Jouppi and Christos Kozyrakis : “Future Scaling of Processor-Mem-ory Interfaces”. Technical Report N° HPL-2009-180. HP Laboratories 2009.[Amdahl et al. 64]Gene M. Amdahl, Gerrit A. Blaauw and Frederick P. Brooks : “Architecture of the IBM System/360”. IBM Journal of Research and Development, Vol. 8, N° 2, pp. 87-101. April 1964.[Asato et al. 95]Creigton Asato, Robert Montoye, John Gmuender, E. Wade Simmons, Atsushi Ike and John Zasio : “A 14-Port 3.8 ns 116-Word 64b Read-Renaming Register File”. 1995 IEEE Interna-tional Solid-State Circuits Conference (ISSCC 1995). Digest of Technical Papers, pp. 104-105, 345. February 1995.[Ayukawa et al. 98]Kazushige Ayukawa, Takao Watanabe and Susumu Narita : “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's”. IEEE Journal of Solid-State Circuits (JSSC), Vol. 33, N° 5, pp. 800-806. May 1998.[Becker et al. 93]Michael K. Becker, Michael S. Allen, Charles R. Moore, John S. Muhich and David P. Tuttle : “The Power PC 601 Microprocessor”. IEEE Micro, Vol. 13, N° 5, pp. 54-68. September/Octo-ber 1993.[Bell et al. 78]“Computer engineering : A DEC View of Hardware Systems Design”. C. Gordon Bell, J. Craig Mudge and John E. McNamara Editors. 1978.[Berlekamp 74]Key Papers in The Development of Coding Theory. Edited by Elwyn R. Berlekamp. IEEE Press 1974. ISBN 0-87942-031-6 and 0-87942-032-4.

Organisation générale d’une mémoire à semi-conducteurs à accès aléatoire8

[Blake 73]Algebraic Coding Theory : History and Development”. Benchmark Papers in Electrical Engineering and Com-puter Science. Edited by Ian F. Blake. Dowden, Hutchinson & Ross, Inc. 1973. ISBN 0-87933-038-4.[Boonstra et al. 73]Loek Boonstra, Cees W. Lambrechtse and Roelof H. W. Salters : “A 4096-b One-Transistor Per Bit Random-Access Memory with Internal Timing and Low Dissipation”. IEEE Journal of Solid-State Circuits (JSSC), Vol. SC-8, N° 5 (Special Issue on Semiconductor Memory and Logic), pp. 305-310. October 1973.[Brugler and Jespers 69]J. S. Brugler and P. G. A. Jespers : “Charge Pumping in MOS Devices”. IEEE Transactions on Electron Devices, Vol. 16, N° 3, pp. 297-302. March 1969.[Burnett and Coffman 70]G. J. Burnett and E. G. Coffman, Jr : “A Study of Interleaved Memory Systems”. Proceedings of the 1970 Spring Joint Computer Conference, Session: Computer System Modeling and Analysis, pp. 467-474. Conference Date: May 5-7, 1970. Conference Location: Atlantic City, New Jersey, United States of America (USA).[Chan et al. 06]Yuen H. Chan, Uma Srinivasan and Jatinder K. Wadhwa : “High Performance CMOS NOR Pre-decode Circuit”. United States (US) Patent N° 20060176757. Filing Date: February 9, 2005. Publication Date: August 10, 2006.[Chen and Hsiao 84]C. L. Chen and M. Y. Hsiao : “Error-Correcting Codes for Semiconductor Memory Applica-tions : A State-of-the-Art Review”. IBM Journal of Research and Development, Vol. 28, N° 2, pp. 124-134. March 1984.[Cohen 81]Danny Cohen : “On Holy Wars and a Plea for Peace”. IEEE Computer, Vol. 14, N° 10, pp. 48-54. October 1981. Original : IEN (Internet Engineering Note) 137. USC/ISI (University of Southern California /Information Sciences Institute). April 1, 1980.[Collège d’experts 03]Collège d’experts chargé du contrôle des systèmes de vote et de dépouillement automatisés : “Rapport concernant les élections du 18 mai 2003”. 2 juin 2003.[Darche 00]Philippe Darche : Architecture des ordinateurs - Représentation des nombres et codes - Cours avec exercices corrigés. Collection Support IUT. Éditions Gaëtan Morin. Novembre 2000. ISBN 2-910749-49-5. 388 pages.[Darche 02]Philippe Darche : Architecture des ordinateurs - Fonctions booléennes, logiques combinatoire et séquentielle - Cours avec exercices et exemples en VHDL. Éditions Vuibert. Mars 2002. ISBN 2-7117-8688-9. 360 pages.[Darche 03]Philippe Darche : Architecture des ordinateurs - Interfaces et périphériques - Cours avec exercices corrigés. Éditions Vuibert. Juin 2003. ISBN 2-7117-4814-6. 416 pages.[Darche 04]Philippe Darche : Architecture des ordinateurs - Logique booléenne : implémentations et technologies. Édi-tions Vuibert. Novembre 2004. ISBN 2-7117-4821-9. 284 pages.

Bibliographie 9

[Davis 85]H. L. Davis : “A 70ns Word-Wide 1-Mb ROM with On-Chip Error-Correction Circuits”. IEEE Journal of Solid-State Circuits (JSSC), Vol. SC-20, N° 5, pp. 958-963. October 1985.[Dell 97]Timothy J. Dell : “A White Paper on the Benefits of Chipkill Correct ECC for PC Server Main Memory”. IBM Microelectronics Division. Rev. 11/19/97.[Dickinson et al. 94]Alexander G. Dickinson, Mehdi Hatamian and Sailesh K. Rao : “Synchronous Static Random Access Memory”. United States (US) Patent N° 5309395. Filing Date: October 22, 1992. Publi-cation Date: May 3, 1994.[Diefendorff 94]Keith Diefendorff : “History of the PowerPC architecture”. Communications of the ACM (CACM), Vol. 37, N° 6, pp. 28-33. June 1994.[Dijkstra 65] Edsgar Wybe Dijkstra : “Solution of a Problem in Concurrent Programming Control”. Commu-nications of the ACM (CACM), Vol. 8, N° 9, p. 569. September 1965.[DiMarco et al. 94]David P. DiMarco, James W. Nicholes and Douglas D. Smith : “Sense Amplifier and Latching Circuit for an SRAM”. United States (US) Patent N° 5289415. Filing Date: April 17, 1992. Pub-lication Date: February 22, 1994.[Dubujet 90]Bruno Dubujet : “Circuit for the Detection of Address Transitions”. United States (US) Patent N° 4922122. Filling Date: August 23, 1988. Publication Date: May 1, 1990.[Eto et al. 98]Akira Eto, Mitsumori Hidaka, Yutaka Okuyama, Katsutaka Kimura and Masayuki Hosono : Impact of Neutron flux on Soft Errors in MOS Memories. 1998 International Electron Devices Meet-ing (IEDM '98). Technical Digest, pp. 367-370. San Francisco, CA, United States of America (USA). 12 September 1998. ISBN 0-7803-4774-9.[Foss and Harland 75]Richard C. Foss and Robert Harland : “Peripheral Circuits for One Transistor Cell MOS RAMs”. IEEE Journal of Solid-State Circuits (JSSC), Vol. SC-10, N° 5 (Special Issue on Semi-conductor Memory and Logic), pp. 255-261. October 1975.[Frederick 85]Bruce A. Frederick : “MOS Depletion Load Circuit”. United States (US) Patent N° 4516225. Filing Date: February 18, 1983. Publication Date: May 7, 1985.[Fujii et al. 89a]Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshi-kawa, Seiji Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto and Ko-ichi Toita : “ A 45ns 16Mb DRAM with Triple-Well Structure”. 36th IEEE International Solid-State Circuits Conference (ISSCC 1989). Digest of Technical Papers, pp. 248-249. February 1989.[Fujii et al. 89b]Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshi-kawa, Seiji Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto and Ko-ichi Toita : “A 45-ns 16-Mbit Dram With Triple-well Structure”. IEEE Journal of Solid-State Circuits (JSSC), Vol. 24, N° 5 (Special Issue on Logic and Memory), pp. 1170-1175. October 1989.


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Chapitre 4

Les mémoires vives statiques

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Les mémoires vives statiques24

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Les mémoires vives dynamiques à communication par paquet56

[Slater 92]Michael Slater : “Rambus Unveils Revolutionary Memory Interface”. Microprocessor Report, pp. 15-21. March 4, 1992.[Stern 01a]Richard H. Stern : “Preventing Abuse of IEEE Standards Policy”. Micro Law. IEEE Micro, Vol. 21, N° 3, pp. 8-11. May/June 2001.[Stern 01b]Richard H. Stern : “More Standardization Skullduggery”. Micro Law. IEEE Micro, Vol. 21, N° 4, pp. 12-15, 69. July/August 2001.[Stern 01c]Richard H. Stern : “Another Update on Standardization Skullduggery”. Micro Law. IEEE Micro, Vol. 21, N° 5, pp. 8-10. September/October 2001.[Stern 02]Richard H. Stern : “FTC Piles onto Standardization Rambus' Skullduggery”. Micro Law. IEEE Micro, Vol. 22, N° 4, pp. 6- 7, 86-87. July/August 2002.[Stern 03]Richard H. Stern : “Weird Turn of Events in Continuing Rambus Saga”. Micro Law. IEEE Micro, Vol. 23, N° 1, pp. 76-80. January/February 2003.[Stern 07]Richard H. Stern : “Coming Down the Home Stretch in the Rambus Standardization Skulldug-gery Saga: To levy or Not to Levy Royalties”. Micro Law. IEEE Micro, Vol. 27, N° 2, pp. 80-82. March/April 2007.[Stern 09]Richard H. Stern : “One of the Last Updates on Rambus Standardization Skullduggery”. Micro Law. IEEE Micro, Vol. 29, N° 1, pp. 139-143. January/February 2009.[Trodden and Anderson 93]Jay Trodden and Don Anderson: Hypertransport System Architecture. PC System Architecture Series. MindShare, Inc. Addison-Wesley. 1993. ISBN 00-321-16845-3.[Xanthaki 94]Zacharenia Xanthaki : “A Memory Controller for Access Interleaving over a Single Rambus”. Report N° FORTH-ICS/TR-124. University of Crete, Computer Science Department. July 1994.[Ware and Hampel 05]Frederick A. Ware and Craig Hampel : “Micro-threaded Row and Column Operations in a DRAM Core”. Rambus White Paper. 7 pages. March 2005.[Ware et al. 01]Frederick A. Ware, Richard M. Barth, Donald C. Stark, Craig E. Hampel, Ely K. Tsern, Abhijit M. Abhyankar, Thomas J. Holman, Andrew V. Anderson and Peter D. Macwilliams : “Apparatus and Method for Bus Timing Compensation”. United States (US) Patent N° 6226757. Filing Date: October 9, 1998. Publication Date: May 1, 2001.[Ware 07]Fredrick A. Ware : “Memory Systems with Variable Delays for Write Data Signals”. United States (US) Patent N° 7301831. Application Number: 10/942225. Filing Date: September 15, 2004. Publication Date: November 27, 2007.[Xanthaki 94]Zacharenia Xanthaki : “A Memory Controller for Access Interleaving over a Single Rambus”. Report N° FORTH-ICS/TR-124. University of Crete, Computer Science Department. July 1994.

Bibliographie 57

[Yip et al. 07]Wai-Yeung Yip, Scott Best, Wendemagegnehu Beyene and Ralf Schmitt : “System Co-Design and Co-Analysis Approach to Implementing the XDR™ Memory System of the Cell Broad-band Engine™ Processor: Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production”. Proceedings of the 2007 Asia and South Pacific Design Automation Con-ference (ASP-DAC '07), pp. 858-865. Conference Date: 23-26 January 2007.

Conclusion

[Calhoun and Brooks 10]Benton H. Calhoun and David Brooks : “Can Subthreshold and Near-Threshold Circuits Go Mainstream?”. IEEE Micro, Vol. 30, N° 4, pp. 80-85. July/August 2010.[Dreslinski et al. 10]Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester and Trevor Mudge : “Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits”. Proceedings of the IEEE, Vol. 98, N° 2, pp. 253-266. February 2010.[Itoh et al. 00]Kiyoo Itoh, Takao Watanabe, Shin'ichiro Kimura and Takeshi Sakata : “Reviews and Prospects of High-Density RAM Technology”. Proceedings of the International Semiconductor Confer-ence (CAS 2000), Vol. 1, pp. 13-22. Conference Date: October 10-14, 2000. Conference Loca-tion: Sinaia, Romania.[ITRS 05]“International Technology Roadmap For Semiconductors - Emerging Research Devices”. ITRS Emerging Research Devices Technology Working Group. 2005 Edition.[ Jung et al. 04]Soon-Moon Jung, Jaehoon Jang, Wonseok Cho, Jaehwan Moon, Kunho Kwak, Bonghyun Choi, Byungjun Hwang, Hoon Lim, Jaehun Jeong, Jonghyuk Kim and Kinam Kim : “The Revolution-ary and Truly 3-Dimensional 25F2 SRAM Technology with the Smallest S3 (Stacked Single-Crys-tal Si) cell, 0.16μm2, and SSTFT (Stacked Single-Crystal Thin Film Transistor) for Ultra High Density SRAM”. 2004 Symposium on VLSI Technology. Digest of Technical Papers, pp. 228-229. Symposium Date: 15-17 June 2004.[Keeth and Baker 00]Brent Keeth and Russel Jacob Baker : DRAM Circuit Design: A Tutorial. IEEE Press Series on Microelectronic Systems. Wiley-IEEE Press Publisher 2000. ISBN 0-7803-6014-1.[Keeth et al. 07]Brent Keeth, Russel Jacob Baker, Brian Johnson and Feng Lin : DRAM Circuit Design: Fundamen-tal and High-Speed Topics. IEEE Press Series on Microelectronic Systems. Wiley-IEEE Press Pub-lisher 2007. ISBN 978-0-470-18475-2.[Prince 83 96]Betty Prince : Semiconductor Memories - A Handbook of Design, Manufacture, and Application. Second Edition. John Wiley & Sons, Ltd. England 1996. ISBN 0-471-92465-2.[Prince 99]Betty Prince : High Performance Memories - New Architecture DRAMs and SRAMs Evolution and Func-tion. Revised Edition. John Wiley & Sons, Ltd. New York, USA 1999. ISBN 0-471-98610-0.

Conclusion60

[Rusu et al. 09]Stefan Rusu, Simon Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta and Sailesh Kottapalli : “A 45nm 8-Core Enterprise Xeon® Processor”. 2009 IEEE International Solid-State Circuits Conference (ISSCC 09). Digest of Technical Papers, pp. 56-57. Conference Date: 8-12 February 2009.[Sharma 02a]Ashok K. Sharma : Semiconductor Memories: Technology, Testing, and Reliability. Wiley-IEEE Press. September 2002. ISBN 0-7803-1000-4.[Sharma 02b]Ashok K. Sharma : Advanced Semiconductor Memories: Architectures, Designs, and Applications. Wiley-IEEE Press. October 2002. ISBN 0-471-20813-2.[Slater et al. 93]Michael Slater, Michael Farmwald, Marc Hannah, David V. James, Joel A. Karp, Masaki Kumanoya and John Szarek : “Which DRAM Will Win the Great DRAM Sweepstakes?”. 40th

IEEE International Solid-State Circuits Conference (ISSCC 1993). Digest of Technical Papers, pp. 76-77. Meeting Date: 24-26 February 1993.

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