Scalable Many-Core Memory Systems Topic 1: DRAM Basics and DRAM Scaling
Architecting Phase Change Memory as a Scalable DRAM ... · PDF fileArchitecting Phase Change...
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Architecting Phase Change Memory as aScalable DRAM Alternative
Benjamin Lee†, Engin Ipek†, Onur Mutlu‡, Doug Burger†
† Computer Architecture GroupMicrosoft Research
‡ Computer Architecture LabCarnegie Mellon University
International Symposium on Computer Architecture22 June 2009
Benjamin C. Lee et al. 1 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Memory in Transition
I Charge MemoryB Write data by capturing charge QB Read data by detecting voltage VB Examples: Flash, DRAM
I Resistive MemoryB Write data by driving current dQ/dtB Read data by detecting resistance RB Examples: PCM, MRAM, memristor
Benjamin C. Lee et al. 2 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Limits of Charge Memory
B Unscalable charge placement and control
B Flash: floating gate charge
B DRAM: capacitor charge, transistor leakage
Benjamin C. Lee et al. 3 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
Towards Resistive Memory
I ScalableB Program with current ∝ cell sizeB Map resistance to logical state
I Non-VolatileB Set atomic structure in cellB Incur activation cost
I CompetitiveB Achieve viable delay, energy, enduranceB Scale to further improve metrics
Benjamin C. Lee et al. 4 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Memory ScalingCharge MemoryResistive Memory
PCM Deployment
B Deploy PCM on the memory bus
B Begin by co-locating PCM, DRAM
B Begin by deploying in low-power platforms
Benjamin C. Lee et al. 5 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Outline
I MotivationB Memory ScalingB Charge MemoryB Resistive Memory
I TechnologyB Phase Change MemoryB Technology ParametersB Price of Scalability
I ArchitectureB Design ObjectivesB Buffer OrganizationB Partial Writes
Benjamin C. Lee et al. 6 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Phase Change Memory
B Store data within phase change material [Ovshinsky68]
B Set phase via current pulse
B Detect phase via resistance (amorphous/crystalline)
Benjamin C. Lee et al. 7 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
PCM Scalability
B Program with current pulses, which scale linearly
B PCM roadmap to 30nm [Raoux+08]
B Flash/DRAM roadmap to 40nm [ITRS07]
Benjamin C. Lee et al. 8 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
PCM Non-Volatility
I Atomic StructureB Program with current pulsesB Melt material at 650 ◦CB Cool material to desired phase
I Activation CostB Crystallize with high activation energyB Isolate thermal effects to target cellB Retain data for >10 years at 85 ◦C
Benjamin C. Lee et al. 9 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Technology ParametersB Survey prototypes from 2003-2008 [ISSCC][VLSI][IEDM][ITRS]
B Derive parameters for F=90nm
DensityB 9 - 12F2 using BJT
B 1.5× DRAM
EnduranceB 1E+08 writes
B 1E-08× DRAM
LatencyB 50ns Rd, 150ns Wr
B 4×, 12× DRAM
EnergyB 40µA Rd, 150µA Wr
B 2×, 43× DRAM
Benjamin C. Lee et al. 10 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Phase Change MemoryTechnology ParametersPrice of Scalability
Price of ScalabilityB 1.6× delay, 2.2× energy, 500-hour lifetime
B Implement PCM in typical DRAM architecture
Benjamin C. Lee et al. 11 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Outline
I MotivationB Memory ScalingB Charge MemoryB Resistive Memory
I TechnologyB Phase Change MemoryB Technology ParametersB Price of Scalability
I ArchitectureB Design ObjectivesB Buffer OrganizationB Partial Writes
Benjamin C. Lee et al. 12 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Design Objectives
I DRAM-CompetitiveB Reorganize row buffer to mitigate delay, energyB Implement partial writes to mitigate wear mechanism
I Area-EfficientB Minimize disruption to density trendsB Impacts row buffer organization
I Complexity-EffectiveB Encourage adoption with modest mechanismsB Impacts partial writes
Benjamin C. Lee et al. 13 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Buffer Organization
I On-Chip BuffersB Use DRAM-like buffer and interfaceB Evict modified rows into array
I Narrow RowsB Reduce write energy ∝ buffer widthB Reduce peripheral circuitry, associated area
I Multiple RowsB Reduce eviction frequencyB Improve locality, write coalescing
Benjamin C. Lee et al. 14 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Buffer Area StrategyB Narrow rows :: fewer expensive S/A’s (44T)
B Multiple rows :: more inexpensive latches (8T)
Benjamin C. Lee et al. 15 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Buffer Design SpaceB Explore area-neutral buffer designs
B Identify DRAM-competitive buffer design
Benjamin C. Lee et al. 16 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Wear Reduction
I Wear MechanismB Writes induce phase change at 650 ◦CB Contacts degrade from thermal expansion/contractionB Current injection is less reliable after 1E+08 writes
I Partial WritesB Reduce writes to PCM arrayB Write only stored lines (64B), words (4B)B Add cache line state with 0.2%, 3.1% overhead
Benjamin C. Lee et al. 17 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Partial WritesB Derive PCM lifetime model
B Quantify eliminated writes during buffer eviction
Benjamin C. Lee et al. 18 :: ISCA :: 22 June 09
MotivationTechnology
Architecture
Design ObjectivesBuffer OrganizationPartial Writes
Scalable PerformanceB 1.2× delay, 1.0× energy, >5-year lifetime
B Scaling improves energy, endurance
Benjamin C. Lee et al. 19 :: ISCA :: 22 June 09
ConclusionPaper DetailsConclusionFuture Directions
Also in the paper...
I Technology SurveyB Survey of circuit/device prototypesB PCM architectural timing, energy modelsB Scaling analysis, implications
I Buffer OrganizationB Transistor-level area modelB Buffer sensitivity analysis
I Partial WritesB Endurance modelB Bus activity analysis
Benjamin C. Lee et al. 20 :: ISCA :: 22 June 09
ConclusionPaper DetailsConclusionFuture Directions
Conclusion & Future Directions
I Memory ScalingB Fundamental limits in charge memoryB Transition towards resistive memory
I Phase Change MemoryB Scalability and non-volatilityB Competitive delay, energy, enduranceB DRAM alternative on the memory bus
I Applied Non-VolatilityB Instant start, hibernateB Inexpensive checkpointingB Safe file systems
Benjamin C. Lee et al. 21 :: ISCA :: 22 June 09
ConclusionPaper DetailsConclusionFuture Directions
PCM File System (PFS)
J.Condit et al. “Better I/O through byte-addressable, persistentmemory.” SOSP-22: Symposium on Operating System Principles,October 2009. (To Appear)
I File System PropertiesB Consistency :: COW with atomicity, orderingB Safety :: Reflect writes to PCM in O(ms), not O(s)B Performance :: Outperform NTFS on RAM disk
I Architectural SupportB Atomic 8B writes with capacitive supportB Ordered writes with barrier-delimited epochs
Benjamin C. Lee et al. 22 :: ISCA :: 22 June 09
Architecting Phase Change Memory as aScalable DRAM Alternative
Benjamin Lee†, Engin Ipek†, Onur Mutlu‡, Doug Burger†
† Computer Architecture GroupMicrosoft Research
‡ Computer Architecture LabCarnegie Mellon University
International Symposium on Computer Architecture22 June 2009
Benjamin C. Lee et al. 23 :: ISCA :: 22 June 09