Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n...

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Apr. 20, 2001 VLSI Test: Bushnell-Agraw al/Lecture 31 1 Lecture 31 System Test Definition Functional test Diagnostic test Fault dictionary Diagnostic tree System design-for-testability (DFT) architecture System partitioning Core test-wrapper DFT overhead Summary

Transcript of Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n...

Page 1: Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.

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Lecture 31System TestLecture 31

System Test

Definition Functional test Diagnostic test

Fault dictionary Diagnostic tree

System design-for-testability (DFT) architecture System partitioning Core test-wrapper DFT overhead

Summary

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A System and Its Testing

A System and Its Testing

A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions.

Functional test verifies integrity of system: Checks for presence and sanity of subsystems Checks for system specifications Executes selected (critical) functions

Diagnostic test isolates faulty part: For field maintenance isolates lowest replaceable unit

(LRU), e.g., a board, disc drive, or I/O subsystem For shop repair isolates shop replaceable unit (SRU), e.g.,

a faulty chip on a board Diagnostic resolution is the number of suspected faulty

units identified by test; fewer suspects mean higher resolution

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System Test ApplicationsSystem Test Applications

A

Application Functional test Diagnostic test Resolution

Manufacturing Yes LRU, SRU

Maintenance Yes

Field repair LRU

Shop repair SRU

LRU: Lowest replaceable unitSRU: Shop replaceable unit

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Functional TestFunctional Test

All or selected (critical) operations executed with non-exhaustive data.

Tests are a subset of design verification tests (test-benches).

Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage.

Examples: Microprocessor test – all instructions with random

data (David, 1998). Instruction-set fault model – wrong instruction is

executed (Thatte and Abraham, IEEETC-1980).

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Gate-Level DiagnosisGate-Level Diagnosis

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:

T1 = 010T2 = 011T3 = 100T4 = 110

Logic circuitKarnaugh map

(shaded squares are true outputs)

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Gate Replacement Fault

Gate Replacement Fault

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:

T1 = 010 (pass)T2 = 011 (fail)

T3 = 100 (pass)T4 = 110 (fail)

Faulty circuit(OR replaced by AND)

Karnaugh map(faulty output shown in red)

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Bridging FaultBridging Fault

e

da

bc T3

T1T2

T4a

b

cStuck-at fault tests:

T1 = 010 (pass)T2 = 011 (pass)T3 = 100 (fail)

T4 = 110 (pass)

Faulty circuit(OR bridge: a, c)

Karnaugh map(red squares are faulty outputs)

a+c

a+c

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Fault Test syndrome t1 t2 t3 t4

No fault

a0, b0, d0

a1

b1

c0

c1, d1, e1

e0

Fault DictionaryFault Dictionary

0

0

1

0

0

1

0

0

0

0

0

1

0

1

0

0

0

1

0

1

0

0

1

0

0

0

0

1

a0 : Line a stuck- at-0

ti = 0, if Ti passes = 1, if Ti fails

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Diagnosis with Dictionary

Diagnosis with Dictionary

Fault Test syndrome Diagnosis t1 t2 t3 t4

OR AND 0 1 0 1 e0

OR-bridge (a,c) 0 0 1 0 b1

OR NOR 1 1 1 1 c1, d1, e1, e0

Dictionary look-up with minimum Hamming distance

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Diagnostic TreeDiagnostic Tree

T4

T1

T2

T3

No faultfound

T3

T2

b1

a1

c1, d1, e1

a0, b0, d0

e0

c0

Pass: t4=0

Fail: t4=1

a0, b0, d0, e0

a1, c1, d1, e1

OR AND

OR bridge(a,c)

OR NOR

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System Test: A DFT Problem

System Test: A DFT Problem

Given the changing scenario in VLSI: Mixed-signal circuits System-on-a-chip Multi-chip modules Intellectual property (IP) cores

Prepare the engineer for designing testable, i.e., manufacturable, VLSI systems.

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Conventional Test:In-Circuit Test (ICT)Conventional Test:In-Circuit Test (ICT)

A bed-of-nails fixture provides direct access to each chip on the board.

Advantages: Thorough test for devices; good interconnect test.

Limitations: Works best when analog and digital functions are

implemented on separate chips. Devices must be designed for backdriving protection. Not applicable to system-on-a-chip (SOC).

Disadvantages: High cost and inflexibility of test fixture. System test must check for timing.

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PCB vs. SOCPCB vs. SOC

Tested parts In-circuit test (ICT) Easy test access Bulky Slow High assembly cost

High reliability Fast interconnects Low cost Untested cores No internal test access Mixed-signal devices

PCB SOC

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Core-Based DesignCore-Based Design

Cores are predesigned and verified but untested blocks: Soft core (synthesizable RTL) Firm core (gate-level netlist) Hard core (non-modifiable layout, often

called legacy core) Core is the intellectual property of vendor

(internal details not available to user.) Core-vendor supplied tests must be applied to

embedded cores.

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Partitioning for TestPartitioning for Test

Partition according to test methodology: Logic blocks Memory blocks Analog blocks

Provide test access: Boundary scan Analog test bus

Provide test-wrappers (also called collars) for cores.

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Test-Wrapper for a Core

Test-Wrapper for a Core

Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core.

Test-wrapper provides: For each core input terminal

A normal mode – Core terminal driven by host chip An external test mode – Wrapper element observes core

input terminal for interconnect test An internal test mode – Wrapper element controls state of

core input terminal for testing the logic inside core For each core output terminal

A normal mode – Host chip driven by core terminal An external test mode – Host chip is driven by wrapper

element for interconnect test An internal test mode – Wrapper element observes core

outputs for core test

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A Test-WrapperA Test-Wrapper

Wrappertest

controller

Scan chain

Sca

n c

hain

Sca

n c

hain

to/from TAP

from/toExternalTest pins

Wrapperelements

Core

Fun

ctio

nal

core

in

pu

ts

Fun

ctio

nal

core

ou

tpu

ts

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Overhead of Test AccessOverhead of Test Access

Test access is non-intrusive. Hardware is added to each I/O signal of block

to be tested. Access interconnects are mostly local. Hardware overhead is proportional to:

(Block area) – 1/2

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Overhead EstimateOverhead Estimate

Rent’s rule: For a logic block the number of gates Gand the number of terminals t are related by

t = K G

where 1 < K < 5, and ~ 0.5.

Assume that block area A is proportional to G, i.e.,t is proportional to A 0.5. Since test logic is addedto each terminal t,

Test logic added to terminals

Overhead = ------------------------------------------------- ~ A –0.5

A

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DFT Architecture for SOC

DFT Architecture for SOC

User defined test access mechanism (TAM)

Module

1Test

wra

pper

Testsource

Testsink

Module

NTest

wra

pper

Test access port (TAP)

Functionalinputs

FunctionaloutputsFunc.

inputs

Func.outputs

SOC inputs SOC outputsTD

I

TC

K

TM

S

TR

ST

TD

O

Instruction register control

Serial instruction data

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DFT ComponentsDFT Components

Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE.

Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE.

Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components.

Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.

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SummarySummary Functional test: verify system hardware, software,

function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage.

Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree.

SOC design for testability: Partition SOC into blocks of logic, memory and analog

circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog

test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures.