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APPENDIX C: The Windows XP Workstation and Cadence Tools Introduction This appendix is intended to introduce the reader to the computing equipment available in the lab. At the time of this writing, this includes a Windows XP x64 PC, Microsoft Word, Cadence Design Entry CIS, and Cadence AMS Simulator. The following sections describe the process used to enter schematic logic diagrams into the PC and run logic simulations on the schematics. Windows XP x64 The PC will normally be powered up. By pressing Ctrl-Alt-Del, a login window will appear. To login, select UMN.EDU (Kerberos), and enter your X500 ID and password in the appropriate fields. Once logged in, your “My Documents” and “Desktop” folders will be accessible from any workstation in the lab. Microsoft Word The lab reports for this lab can easily be created using Microsoft Word. Cadence Design Entry CIS This tool provides the primary means of entering schematic logic diagrams into the PC. Once entered, these schematics can be simulated with varying inputs to allow for closer examination.

Creating a New Project Projects provide a way to group schematics and simulation profiles together. To create a project, open Cadence Design Entry CIS from the Start menu (Start->All Programs->Cadence…->Design Entry CIS). The following chooser may appear. If so, select “Allegro PCB Design CIS XL,” and click “OK.”

Once Design Entry has started, a new project can be created by selecting File->New->Project.

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For this lab, projects should be “Analog or Mixed A/D.” The New Project dialog also requires a destination location for the project files. Be sure to select a location you will remember.

In the following dialog box, select “Create a blank project.”

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Adding Parts to a Schematic Most of the components on a schematic are obtained from the “place part” dialog. Once the newly created schematic is selected, this dialog can be reached as shown:

If this is your first project, you may need to load part libraries. The standard libraries for this lab are “74LS,” “analog,” and “source.” These may be found in

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C:\Cadence\SPB_16.0\tools\capture\library\pspice, and may be loaded with the “add library” button in the “place part” dialog.

To place a part on the schematic, locate it in a library, click “OK,” and then place as many as necessary on the schematic page by clicking the left mouse button. Parts may be wired together with the “place wire” tool. This tool is available under the “place” menu and on the tool palette on the right side of the application screen.

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In the above figure, a simple circuit has been created with a voltage source, a logic gate, and an output. The voltage source and ground parts are available in the “source” library.

Analog Simulation

Simulating a circuit Once a schematic has been entered, it may be simulated by means of Cadence AMS Simulator. If a Design Entry project is properly configured, AMS Simulator may be easily launched from Design Entry. The following steps outline this configuration. Creating a netlist

A netlist is a text-based representation of a circuit. In this lab, it describes the circuit created in Design Entry in a way that AMS Simulator understands. To create a netlist, select “Create Netlist” from the “PSpice” menu. If this step incurs errors, use the Session Log window to diagnose and correct them.

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Creating a Simulation Profile

In order to simulate a circuit, AMS Simulator requires instructions regarding how to run the simulation and what properties to measure. These instructions are given in the form of a simulation profile. To create a simulation profile, select “New Simulation Profile” from the “PSpice” menu.

In the Simulation Settings Window, a few types of simulations will be available. A summary of the options follows.

• The “Bias Point” option attempts to determine a steady state for the circuit. • The “Time Domain (Transient)” option simulates the circuit for a given time period, sampling

the circuit state throughout the period. This can result in readout like one might see on an oscilloscope.

• The AC and DC Sweep options allow the user to select a voltage source in the circuit and observe the effects of varying its output.

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Running a Simulation

To run a simulation, select “Run” from the “PSpice” menu or press the “Run” button on the toolbar.

Example Bias Point Simulation

What follows is the result of a Bias Point simulation. Note the numbers in solid red boxes; these represent analog and digital signals in the circuit. Also note that the digital “0” lacks a “V” following it, because it is a digital signal.

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Example Time Domain Simulation

In the following circuit, the VDC source from the previous example has been replaced with VPULSE source. It has been configured with a 5V, 0.5 Hz, 50% duty cycle output.

The VPULSE parameters are

V1: initial value V2: pulsed value TD: delay time TR: rise time TF: fall time PW: pulse width PER: period

The associated simulation profile is shown below.

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The output of this simulation, with appropriate traces were added, shows both analog and digital signals in the time domain. To add a trace in this window, select “Add Trace” from the “Trace” menu, or press the “insert” key. In the “Add Trace” dialog, select each signal to be displayed on the plot.

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Digital Simulation

Rather than doing a simulation using analog signals, the simulation can be done using logic (digital) signals. In this case, the inputs to the circuit need to be digital sources. An example, is given in the circuit below. Notice the Probes placed on the schematic. Lines with Probes on them are automatically shown in the trace window when the circuit is simulated.

The input is a digital stimulus (DSTM1). This part is available in the Source library; it is called STIM1 where the 1 indicates a source 1 line wide. When this part is placed on a schematic, it is entitled DSTM1 for the first placement, DSTM2 for the second placement, etc. This source can be programmed to generate a particular input pattern. Double clicking the part opens the following Property Editor window:

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When first opened, COMMAND1 is 0s 0 meaning that the output is 0 at time 0s. The output can be changed at other times by adding additional commands. The window above has commands for changing the output to 1 at 40ns and back to 0 at 140ns. If a clock input is needed for a circuit, use the part DigClock in the Source library rather than the one above. To prepare for a simulation are first Create a Netlist and next create a new Simulation Profile. The Simulation Analysis type is “Time Domain (Transient)”; see the menu below. Be sure to set the Run Time to an appropriate value.

In addition to selecting the simulation type to “Time Domain (Transient)”, the Category should be set to Gate-level Simulation. The latter is chosen under the Options menu; see below. Note that the gate propagation delay can be chosen as Minimum, Typical, Maximum or Worst-Case.

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Then the simulation can be Run. The simulation trace for the preceding example is shown below.

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