Apollo3 Blue Plus MCU Datasheet - Ambiq Micro...- 14 bit ADC at up to 1.2 MS/s, 15 selectable input...

Apollo3 Blue Plus MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A3P-0p3p0 Page 1 of 999 2019 Ambiq Micro, Inc.All rights reserved.


Doc. ID: DS-A3P-0p3p0Revision 0.3.0October 2019

IMPORTANT NOTICE:This datasheet includes content which is accurate to the

extent possible, but is preliminary and certain content may not be fully validated.



DS-A3P-0p3p0 Page 2 of 999 2019 Ambiq Micro, Inc. All rights reserved.

FeaturesUltra-low supply current:

- 6 µA/MHz executing from FLASH or RAM at 3.3 V- 1 µA deep sleep mode (BLE Off) with RTC at 3.3 V

High-performance ARM Cortex-M4 Processor- 48 MHz nominal clock frequency, with 96 MHz high perfor-

mance TurboSPOT™ Mode- Floating point unit- Memory protection unit- Wake-up interrupt controller with 32 interrupts

Integrated Bluetooth1 5 low-energy module- RF sensitivity: -93 dBm (typical)- TX: 3 mA @ 0 dBm, RX: 3 mA- Tx peak output power: 4.0 dBm (max)

Ultra-low power memory:

- Up to 2 MB of flash memory for code/data- Up to 768 KB of low leakage RAM for code/data- 16 kB 2-way Associative/Direct-Mapped Cache

Ultra-low power interface for on- and off-chip sensors:- 14 bit ADC at up to 1.2 MS/s, 15 selectable input channels

available- Voltage Comparator- Temperature sensor with +/- 3ºC accuracy after calibration

ISO7816 Secure interfaceFlexible serial peripherals:

- 1x 2/4/8-bit and 2x 2/4-bit SPI master interfaces (MSPIs)- 6x I2C/SPI masters for peripheral communication- I2C/SPI slave for host communications- 2x UART modules with 32-location Tx and Rx FIFOs- PDM for mono and stereo audio microphone- 1x I2S slave for PDM audio pass-through

Rich set of clock sources:- 32.768 kHz XTAL oscillator- Low frequency RC oscillator – 1.024 kHz- High frequency RC oscillator – 48/96 MHz- RTC based on Ambiq’s AM08X5/18X5 families

Wide operating range: 1.755-3.63 V, –40 to 85°CCompact package:

- 5.3 x 4.3 x 0.8 mm, 108-ball BGA with 74 GPIO

1. The Bluetooth® word mark and logos are registered trademarks owned by the Bluetooth SIG, Inc. and any use of such marks is under license. Other trademarks and trade names are those of their respec-tive owners.

Applications

DescriptionThe Apollo MCU Family is an ultra-low power, highly integrated microcontroller platform based on Ambiq Micro’s patented Sub-threshold Power Optimized Technology (SPOT™) and designed for battery-powered and portable, mobile devices. The Apollo3 Blue Plus MCU sets a new standard in energy efficiency for bat-tery-powered devices with an integrated ARM Cortex-M4 proces-sor with Floating Point Unit and TurboSPOT™ increasing the computational capabilities of the ARM Cortex M4F core to 96MHz while lowering the active power consumption to




Table of Content

1. Apollo3 Blue Plus MCU Package Pins .............................................................................. 491.1 Pin Configuration ....................................................................................................... 491.2 Pin Connections ......................................................................................................... 49

2. System Core ....................................................................................................................... 733. MCU Core Details ............................................................................................................. 75

3.1 Interrupts .................................................................................................................... 763.2 Memory Map ............................................................................................................. 793.3 Memory Protection Unit (MPU) ................................................................................ 833.4 System Busses ............................................................................................................ 843.5 Power Management ................................................................................................... 85

3.5.1 Cortex-M4 Power Modes .................................................................................. 853.5.2 System Power Modes ........................................................................................ 863.5.3 Power Control ................................................................................................... 89

3.6 Debug Interfaces ...................................................................................................... 1073.6.1 Debugger Attachment ..................................................................................... 1073.6.2 Instrumentation Trace Macrocell (ITM) ......................................................... 1073.6.3 Trace Port Interface Unit (TPIU) .................................................................... 1073.6.4 Faulting Address Trapping Hardware ............................................................. 107

3.7 ITM Registers .......................................................................................................... 1083.7.1 Register Memory Map .................................................................................... 1093.7.2 ITM Registers ................................................................................................. 111

3.8 MCUCTRL Registers .............................................................................................. 1373.8.1 Register Memory Map .................................................................................... 1383.8.2 MCUCTRL Registers ..................................................................................... 140

3.9 Memory Subsystem ................................................................................................. 1733.9.1 Features ........................................................................................................... 1743.9.2 Functional Overview ....................................................................................... 1743.9.3 Flash Cache ..................................................................................................... 1753.9.4 SRAM Interface .............................................................................................. 193

4. Security ............................................................................................................................ 1954.1 Functional Overview ................................................................................................ 1954.2 Secure Boot .............................................................................................................. 1954.3 Secure OTA ............................................................................................................. 1954.4 Secure Key Storage .................................................................................................. 1964.5 External Flash Inline Encrypt/Decrypt .................................................................... 196

5. DMA ................................................................................................................................ 1975.1 Functional Overview ................................................................................................ 197

5.1.1 General Usage ................................................................................................. 1975.1.2 Auto Power Down .......................................................................................... 1985.1.3 Priority ............................................................................................................ 1985.1.4 Hardware Handshake / Hardware Triggering ................................................. 198

6. BLE Module .................................................................................................................... 1996.1 Functional Overview ................................................................................................ 199

6.1.1 Introduction ..................................................................................................... 199




6.1.2 Main Features ................................................................................................. 1996.2 Functional Description ............................................................................................. 200

6.2.1 Data Transfers ................................................................................................. 2006.3 BLEIF Registers ...................................................................................................... 201

6.3.1 Register Memory Map .................................................................................... 2026.3.2 BLEIF Registers ............................................................................................. 204

7. MSPI Master Module ....................................................................................................... 2377.1 Functional Overview ................................................................................................ 2377.2 Configuration ........................................................................................................... 2387.3 PIO Operations ........................................................................................................ 2397.4 DMA Operations ...................................................................................................... 2407.5 Execute in Place (XIP) Operations .......................................................................... 241

7.5.1 XIPMM Operation .......................................................................................... 2417.5.2 Optimized XIP Addressing ............................................................................. 2417.5.3 Micron XIP Support ........................................................................................ 242

7.6 Command Queueing (CQ) ....................................................................................... 2427.6.1 Command Queue Data Format ....................................................................... 2427.6.2 CQ Interrupts .................................................................................................. 2437.6.3 Pausing CQ Operations ................................................................................... 2447.6.4 Using the CQ Index registers .......................................................................... 2457.6.5 MSPI and IOM Intercommunication .............................................................. 246

7.7 Data Scrambling ...................................................................................................... 2467.8 Auto Power Down ................................................................................................... 2467.9 Pad Configuration and Enables ................................................................................ 246

7.9.1 Internal Pin Muxing Options .......................................................................... 2487.9.2 MSPI Pin Timing Board/Package Considerations .......................................... 249

7.10 MSPI Registers ...................................................................................................... 2507.10.1 Register Memory Map .................................................................................. 2517.10.2 MSPI Registers ............................................................................................. 254

8. I2C/SPI Master Module ................................................................................................... 2888.1 Functional Overview ................................................................................................ 288

8.1.1 Main Features ................................................................................................. 2898.2 Functional Description ............................................................................................. 289

8.2.1 Power Control ................................................................................................. 2898.2.2 Clocking and Resets ........................................................................................ 2898.2.3 FIFO ................................................................................................................ 2928.2.4 Data Alignment ............................................................................................... 2928.2.5 Transaction Initiation ...................................................................................... 2948.2.6 Command Queue ............................................................................................ 295

8.3 Programmer’s Reference ......................................................................................... 2988.4 Interface Clock Generation ...................................................................................... 2988.5 Command Operation ................................................................................................ 2998.6 FIFO ......................................................................................................................... 3008.7 I2C Interface ............................................................................................................ 300

8.7.1 Bus Not Busy .................................................................................................. 3008.7.2 Start Data Transfer .......................................................................................... 301




8.7.3 Stop Data Transfer .......................................................................................... 3018.7.4 Data Valid ....................................................................................................... 3018.7.5 Acknowledge .................................................................................................. 3018.7.6 I2C Slave Addressing ..................................................................................... 3018.7.7 I2C Offset Address Transmission ................................................................... 3028.7.8 I2C Write Operation with Address Offset ...................................................... 3028.7.9 I2C Read Operation with Address Offset ....................................................... 3038.7.10 I2C Write Operation with No Address Offset .............................................. 3038.7.11 I2C Read Operation with No Address Offset ............................................... 3048.7.12 Holding the Interface with CONT ................................................................ 3048.7.13 I2C Multi-master Arbitration ........................................................................ 304

8.8 SPI Operations ......................................................................................................... 3048.8.1 SPI Configuration ........................................................................................... 3048.8.2 SPI Slave Addressing ...................................................................................... 3058.8.3 SPI Write with Address Offset ....................................................................... 3058.8.4 SPI Read with Address Offset ........................................................................ 3058.8.5 SPI Write with No Address Offset ................................................................. 3068.8.6 SPI Read with No Address Offset .................................................................. 3068.8.7 SPI 3-wire Mode ............................................................................................. 3078.8.8 Complex SPI Operations ................................................................................ 3078.8.9 SPI Polarity and Phase .................................................................................... 307

8.9 Apollo3 Blue Plus MCUBit Orientation .................................................................. 3088.10 SPI Flow Control ................................................................................................... 3088.11 Minimizing Power ................................................................................................. 3108.12 IOM Registers ........................................................................................................ 311

8.12.1 Register Memory Map .................................................................................. 3128.12.2 IOM Registers ............................................................................................... 317

9. I2C/SPI Slave Module ..................................................................................................... 3549.1 Functional Overview ................................................................................................ 3549.2 Local RAM Allocation ............................................................................................ 3549.3 Direct Area Functions .............................................................................................. 3559.4 FIFO Area Functions ............................................................................................... 3589.5 Rearranging the FIFO .............................................................................................. 3599.6 Interface Interrupts ................................................................................................... 3609.7 Command Completion Interrupts ............................................................................ 3619.8 Host Address Space and Registers ........................................................................... 3619.9 I2C Interface ............................................................................................................ 361

9.9.1 Bus Not Busy .................................................................................................. 3629.9.2 Start Data Transfer .......................................................................................... 3629.9.3 Stop Data Transfer .......................................................................................... 3629.9.4 Data Valid ....................................................................................................... 3629.9.5 Acknowledge .................................................................................................. 3629.9.6 Address Operation .......................................................................................... 3639.9.7 Offset Address Transmission .......................................................................... 3639.9.8 Write Operation .............................................................................................. 3649.9.9 Read Operation ............................................................................................... 364




9.9.10 General Address Detection ........................................................................... 3659.10 SPI Interface .......................................................................................................... 365

9.10.1 Write Operation ............................................................................................ 3659.10.2 Read Operation ............................................................................................. 3669.10.3 Configuring 3-wire vs. 4-wire SPI Mode ..................................................... 3669.10.4 SPI Polarity and Phase .................................................................................. 366

9.11 Bit Orientation ....................................................................................................... 3679.12 Wakeup Using the I2C/SPI Slave .......................................................................... 3679.13 IOSLAVE Registers .............................................................................................. 367

9.13.1 Register Memory Map .................................................................................. 3689.13.2 IOSLAVE Registers ..................................................................................... 369

9.14 Host Side Address Space and Register .................................................................. 3819.14.1 Host Address Space and Registers ................................................................ 381

10. PDM/I2S Module ........................................................................................................... 38610.1 Features .................................................................................................................. 38610.2 Functional Overview .............................................................................................. 386

10.2.1 PDM-to-PCM Conversion ............................................................................ 38710.2.2 Clock Generation .......................................................................................... 38710.2.3 Clock Switching ............................................................................................ 38810.2.4 Operating Modes ........................................................................................... 38910.2.5 FIFO Control and Interrupts ......................................................................... 39010.2.6 Digital Volume Gain ..................................................................................... 39010.2.7 Low Pass Filter (LPF) ................................................................................... 39110.2.8 High Pass Filter ............................................................................................. 391

10.3 I2S Slave Interface ................................................................................................. 39110.4 PDM Registers ....................................................................................................... 392

10.4.1 Register Memory Map .................................................................................. 39310.4.2 PDM Registers .............................................................................................. 394

11. GPIO and Pad Configuration Module ........................................................................... 40811.1 Functional Overview .............................................................................................. 40811.2 Pad Configuration Functions ................................................................................. 40811.3 General Purpose I/O (GPIO) Functions ................................................................. 415

11.3.1 Configuring the GPIO Functions .................................................................. 41511.3.2 Reading from a GPIO Pad ............................................................................ 41511.3.3 Writing to a GPIO Pad .................................................................................. 41511.3.4 GPIO Interrupts ............................................................................................. 415

11.4 Pad Connection Summary ..................................................................................... 41611.4.1 Output Selection ........................................................................................... 41611.4.2 Output Control .............................................................................................. 41611.4.3 Input Control ................................................................................................. 41811.4.4 Pull-up Control ............................................................................................. 41811.4.5 Analog Pad Configuration ............................................................................ 418

11.5 Module-specific Pad Configuration ....................................................................... 41811.5.1 Implementing IO Master Connections .......................................................... 41811.5.2 MSPI Connection .......................................................................................... 42411.5.3 Implementing IO Slave Connections ............................................................ 425




11.5.4 Implementing Counter/Timer Connections .................................................. 42611.5.5 Implementing UART Connections ............................................................... 42811.5.6 Implementing Audio Connections ................................................................ 43411.5.7 Implementing GPIO Connections ................................................................. 43611.5.8 Implementing CLKOUT Connections .......................................................... 43611.5.9 Implementing 32kHz CLKOUT Connections ............................................. 43611.5.10 Implementing ADC Connections ................................................................ 43611.5.11 Implementing Voltage Comparator Connections ...................................... 43711.5.12 Implementing the Software Debug Port Connections ............................... 43811.5.13 Fast GPIO .................................................................................................. 439

11.6 FASTGPIO Registers ............................................................................................ 43911.6.1 Register Memory Map .................................................................................. 43911.6.2 FASTGPIO Registers ................................................................................... 440

11.7 GPIO Registers ...................................................................................................... 44211.7.1 Register Memory Map .................................................................................. 44311.7.2 GPIO Registers ............................................................................................. 446

12. Clock Generator and Real Time Clock Module ............................................................ 61212.1 Clock Generator ..................................................................................................... 612

12.1.1 Functional Overview ..................................................................................... 61212.1.2 Low Frequency RC Oscillator (LFRC) ....................................................... 61312.1.3 High Precision XT Oscillator (XT) .............................................................. 61412.1.4 High Frequency RC Oscillator (HFRC) ....................................................... 61512.1.5 HFRC Auto-adjustment ................................................................................ 61612.1.6 TurboSPOT Mode Support ........................................................................... 61712.1.7 Frequency Measurement ............................................................................... 61712.1.8 Generating 100 Hz ........................................................................................ 618

12.2 CLKGEN Registers ............................................................................................... 61812.2.1 Register Memory Map .................................................................................. 61912.2.2 CLKGEN Registers ...................................................................................... 620

12.3 Real Time Clock .................................................................................................... 63612.3.1 RTC Functional Overview ............................................................................ 63612.3.2 Calendar Counters ......................................................................................... 63612.3.3 Calendar Counter Reads ............................................................................... 63612.3.4 Alarms ........................................................................................................... 63712.3.5 12/24 Hour Mode .......................................................................................... 63712.3.6 Century Control and Leap Year Management .............................................. 63712.3.7 Weekday Function ........................................................................................ 638

12.4 RTC Registers ........................................................................................................ 63812.4.1 Register Memory Map .................................................................................. 63812.4.2 RTC Registers ............................................................................................... 639

13. Counter/Timer Module .................................................................................................. 64613.1 Functional Overview .............................................................................................. 64613.2 Counter/Timer Functions ....................................................................................... 647

13.2.1 Single Count (FN = 0) .................................................................................. 64813.2.2 Repeated Count (FN = 1) .............................................................................. 64813.2.3 Single Pulse (FN = 2) .................................................................................... 649




13.2.4 Repeated Pulse (FN = 3) ............................................................................... 64913.2.5 Single Pattern (FN = 4) ................................................................................. 65013.2.6 Repeat Pattern (FN = 5) ................................................................................ 65113.2.7 Continuous (FN = 6) ..................................................................................... 65113.2.8 Alternate Pulse (FN = 7) ............................................................................... 652

13.3 Creating 32-bit Counters ........................................................................................ 65213.4 Creating a Secondary Output with CMPR2/3 ........................................................ 65313.5 Generating Dual Patterns ....................................................................................... 65313.6 Synchronized A/B Patterns .................................................................................... 65413.7 Triggering Functions .............................................................................................. 654

13.7.1 Initiating a One-shot Operation .................................................................... 65413.7.2 Terminating a Repeat Operation ................................................................... 65413.7.3 Complex Patterns with Triggers ................................................................... 65513.7.4 Dual Edge Triggers ....................................................................................... 65513.7.5 Trigger Controlled Inversion ........................................................................ 655

13.8 Clocking Timer/Counters with Other Counter/Timer Outputs .............................. 65513.9 Global Timer/Counter Enable ................................................................................ 65513.10 Power Optimization by Measuring HCLK ......................................................... 65513.11 Generating the Sample Rate for the ADC .......................................................... 65613.12 Software Generated Serial Data Stream ............................................................. 65613.13 Software Generated PWM Audio Output ........................................................... 65613.14 Stepper Motors Driven by Pattern Generation ................................................... 65613.15 Pattern-based Sine Wave Examples ................................................................... 657

13.15.1 PWM-based Pulse Trains ........................................................................... 65713.15.2 Pattern-based Pulse Trains ......................................................................... 65813.15.3 Selecting the Optimal Method ................................................................... 658

13.16 CLR and EN Details ........................................................................................... 65813.17 NOSYNC Function ............................................................................................. 65913.18 Counter Functions ............................................................................................... 659

13.18.1 Counting External Edges ........................................................................... 65913.18.2 Counting Buck Converter Edges ............................................................... 660

13.19 Interconnecting CTIMERs .................................................................................. 66013.20 Pad Connections from the Timer/Counter .......................................................... 66113.21 CTIMER Registers ............................................................................................. 663

13.21.1 Register Memory Map ................................................................................ 66413.21.2 CTIMER Registers ..................................................................................... 666

14. System Timer Module ................................................................................................... 75514.1 Functional Overview .............................................................................................. 75514.2 STIMER Registers ................................................................................................. 756

14.2.1 Register Memory Map .................................................................................. 75714.2.2 STIMER Registers ........................................................................................ 758

14.3 ............................................................................................................................... 77515. Watchdog Timer Module ............................................................................................... 776

15.1 Functional Overview .............................................................................................. 77615.2 WDT Registers ...................................................................................................... 777

15.2.1 Register Memory Map .................................................................................. 777




15.2.2 WDT Registers ............................................................................................. 77816. Reset Generator Module ................................................................................................ 784

16.1 Functional Overview .............................................................................................. 78416.2 External Reset Pin .................................................................................................. 78416.3 Power-on Event ...................................................................................................... 78516.4 Brown-out Events .................................................................................................. 78516.5 Software Reset ....................................................................................................... 78616.6 Software Power On Initialization .......................................................................... 78616.7 Watchdog Expiration ............................................................................................. 78616.8 RSTGEN Registers ................................................................................................ 786

16.8.1 Register Memory Map .................................................................................. 78616.8.2 RSTGEN Registers ....................................................................................... 787

17. UART Module ............................................................................................................... 79317.1 Features .................................................................................................................. 79317.2 Functional Overview .............................................................................................. 79317.3 Enabling and Selecting the UART Clock .............................................................. 79417.4 Configuration ......................................................................................................... 79417.5 Transmit FIFO and Receive FIFO ......................................................................... 79517.6 UART Registers ..................................................................................................... 795

17.6.1 Register Memory Map .................................................................................. 79517.6.2 UART Registers ............................................................................................ 797

18. ADC and Temperature Sensor Module ......................................................................... 80918.1 Features .................................................................................................................. 80918.2 Functional Overview .............................................................................................. 810

18.2.1 Clock Source and Dividers ........................................................................... 81018.2.2 Channel Analog Mux .................................................................................... 81018.2.3 Triggering and Trigger Sources .................................................................... 81118.2.4 Voltage Reference Sources ........................................................................... 81118.2.5 Eight Automatically Managed Conversion Slots .......................................... 81118.2.6 Automatic Sample Accumulation and Scaling ............................................. 81218.2.7 Sixteen Entry Result FIFO ............................................................................ 81418.2.8 DMA ............................................................................................................. 81618.2.9 Window Comparator ..................................................................................... 817

18.3 Operating Modes and the Mode Controller ........................................................... 81818.3.1 Single Mode .................................................................................................. 81918.3.2 Repeat Mode ................................................................................................. 82018.3.3 Low Power Modes ........................................................................................ 820

18.4 Interrupts ................................................................................................................ 82118.5 Voltage Divider and Switchable Battery Load ...................................................... 82218.6 ADC Registers ....................................................................................................... 822

18.6.1 Register Memory Map .................................................................................. 82318.6.2 ADC Registers .............................................................................................. 824

19. Voltage Comparator Module ......................................................................................... 85219.1 Functional Overview .............................................................................................. 85219.2 VCOMP Registers ................................................................................................. 852

19.2.1 Register Memory Map .................................................................................. 853




19.2.2 VCOMP Registers ........................................................................................ 85420. Voltage Regulator Module ............................................................................................. 859

20.1 Functional Overview .............................................................................................. 85920.2 SIMO Buck ............................................................................................................ 85920.3 BLE/Burst Buck ..................................................................................................... 860

20.3.1 BLE/Burst Buck Ton Adjustment ................................................................. 86020.3.2 BLE/Burst Buck zero length detect .............................................................. 861

21. Electrical Characteristics ............................................................................................... 86221.1 Absolute Maximum Ratings .................................................................................. 86221.2 Recommended Operating Conditions .................................................................... 86421.3 Current Consumption ............................................................................................. 86421.4 Power Mode Transitions ........................................................................................ 86621.5 Clocks/Oscillators .................................................................................................. 86621.6 Bluetooth Low Energy (BLE) ................................................................................ 86721.7 Analog-to-Digital Converter (ADC) ...................................................................... 86821.8 Buck Converter ...................................................................................................... 87121.9 Power-On RESET (POR) and Brown-Out Detector (BOD) ................................. 87321.10 Resets .................................................................................................................. 87421.11 Voltage Comparator (VCOMP) .......................................................................... 87521.12 Multi-bit SPI (MSPI) Interface ........................................................................... 87521.13 Inter-Integrated Circuit (I2C) Interface .............................................................. 87621.14 Serial Peripheral Interface (SPI) Master Interface .............................................. 87721.15 Serial Peripheral Interface (SPI) Slave Interface ................................................. 87921.16 PDM Interface ...................................................................................................... 88121.17 I2S Interface ......................................................................................................... 88121.18 Universal Asynchronous Receiver/Transmitter (UART) .................................... 88121.19 Counter/Timer (CTIMER) ................................................................................... 88221.20 Flash Memory ...................................................................................................... 88221.21 General Purpose Input/Output (GPIO) ................................................................ 88221.22 Serial Wire Debug (SWD) ................................................................................... 884

22. Package Mechanical Information .................................................................................. 88522.1 BGA Package ......................................................................................................... 88522.2 Reflow Profile ........................................................................................................ 885

23. Appendix 1. FLASH OTP 0 Customer Info Space (Info0) ........................................... 89223.1 Flash OTP INSTANCE0 INFO0 Words ............................................................... 892

23.1.1 Register Memory Map .................................................................................. 89323.1.2 Flash OTP INSTANCE0 INFO0 Words ...................................................... 898

24. Ordering Information ..................................................................................................... 99725. Document Revision History ........................................................................................... 998




List of Figures

Figure 1. Apollo3 Blue Plus MCU BGA Pin Configuration Diagram - Top View .................... 49 Figure 2. Block Diagram for the Ultra-Low Power Apollo3 Blue Plus MCU ........................... 73 Figure 3. ARM Cortex-M4 Vector Table for Apollo3 Blue Plus MCU ..................................... 77 Figure 4. Block Diagram for Flash and OTP Memory Subsystem ........................................... 173 Figure 5. Block Diagram for Apollo3 Blue Plus MCU with Flash Cache ............................... 175 Figure 6. Block diagram for the Flash Memory Controller ...................................................... 191 Figure 7. Block diagram for the SRAM Interface .................................................................... 193 Figure 8. Secure Boot Flow ...................................................................................................... 195 Figure 9. Secure OTA Flow ...................................................................................................... 196 Figure 10. Block Diagram for the BLE Module ....................................................................... 199 Figure 11. Block Diagram for the MSPI Master Module ......................................................... 237 Figure 12. MSPI Interface Diagram ......................................................................................... 249 Figure 13. Block Diagram for the I2C/SPI Master Module ..................................................... 288 Figure 14. Clocking Structure for IOM Module ....................................................................... 290 Figure 15. IO_CLK Generation ................................................................................................ 291 Figure 16. Direct Mode 5-byte Write Transfer ......................................................................... 293 Figure 17. Direct Mode 5-byte Read ........................................................................................ 293 Figure 18. Register Write Data Fetches ................................................................................... 295 Figure 19. IOM Pause Example ............................................................................................... 296 Figure 20. CQ Pause Bit Fetching ............................................................................................ 297 Figure 21. I2C/SPI Master Clock Generation ........................................................................... 299 Figure 22. Basic I2C Conditions ............................................................................................... 300 Figure 23. I2C Acknowledge .................................................................................................... 301 Figure 24. I2C 7-bit Address Operation ................................................................................... 302 Figure 25. I2C 10-bit Address Operation ................................................................................. 302 Figure 26. I2C Offset Address Transmission ........................................................................... 302 Figure 27. I2C Write Operation with Address Offset ............................................................... 303 Figure 28. I2C Read Operation with Address Offset ................................................................ 303 Figure 29. I2C Write Operation with No Address Offset ......................................................... 303 Figure 30. I2C Write Operation with No Address Offset ......................................................... 304 Figure 31. SPI Normal Write Operation (Single-byte Offset Address) .................................... 305 Figure 32. SPI Normal Read Operation .................................................................................... 306 Figure 33. SPI Raw Write Operation ........................................................................................ 306 Figure 34. SPI Raw Read Operation ......................................................................................... 306 Figure 35. SPI Combined Operation ......................................................................................... 307 Figure 36. SPI CPOL and CPHA .............................................................................................. 308 Figure 37. Flow Control at Beginning of a Write Transfer ...................................................... 309 Figure 38. Flow Control at Beginning of a Raw Read Transfer ............................................... 309 Figure 39. Flow Control in the Middle of a Write Transfer ..................................................... 310 Figure 40. Flow Control in the Middle of a Read Transfer ...................................................... 310 Figure 41. Block diagram for the I2C/SPI Slave Module ......................................................... 354 Figure 42. I2C/SPI Slave Module LRAM Addressing ............................................................. 355 Figure 43. I2C/SPI Slave Module FIFO ................................................................................... 359 Figure 44. Basic I2C Conditions ............................................................................................... 362




Figure 45. I2C Acknowledge .................................................................................................... 363 Figure 46. I2C 7-bit Address Operation ................................................................................... 363 Figure 47. I2C 10-bit Address Operation ................................................................................. 363 Figure 48. I2C Offset Address Transmission ........................................................................... 364 Figure 49. I2C Write Operation ................................................................................................ 364 Figure 50. I2C Read Operation ................................................................................................. 364 Figure 51. SPI Write Operation ................................................................................................ 365 Figure 52. SPI Read Operation ................................................................................................. 366 Figure 53. SPI CPOL and CPHA .............................................................................................. 366 Figure 54. Block Diagram for PDM Module ............................................................................ 386 Figure 55. Stereo PDM to PCM Conversion Path .................................................................... 387 Figure 56. PDM Clock Timing Diagram .................................................................................. 387 Figure 57. PDM Clock Source Switching Flow ....................................................................... 389 Figure 58. I2S Interface Data Format Timing .......................................................................... 392 Figure 59. I2S Interface Setup and Hold Timing Diagram ....................................................... 392 Figure 60. Block diagram for the General Purpose I/O (GPIO) Module .................................. 408 Figure 61. Pad Connection Details ........................................................................................... 417 Figure 62. Block diagram for the Clock Generator and Real Time Clock Module .................. 612 Figure 63. Apollo3 Blue Clock Tree ........................................................................................ 613 Figure 64. Block diagram for the Real Time Clock Module .................................................... 636 Figure 65. Block Diagram for One Counter/Timer Pair ........................................................... 646 Figure 66. Counter/Timer Operation, FN = 0 ........................................................................... 648 Figure 67. Counter/Timer Operation, FN = 1 ........................................................................... 648 Figure 68. Counter/Timer Operation, FN = 2 ........................................................................... 649 Figure 69. Counter/Timer Operation, FN = 3 ........................................................................... 650 Figure 70. Counter/Timer Operation, FN = 4 ........................................................................... 650 Figure 71. Counter/Timer Operation, FN = 5 ........................................................................... 651 Figure 72. Counter/Timer Operation, FN = 4 ........................................................................... 652 Figure 73. Counter/Timer Operation, FN = 7 ........................................................................... 652 Figure 74. Complex Operations with CMPR2 and CMPR3 ..................................................... 653 Figure 75. Dual Pattern Generation .......................................................................................... 654 Figure 76. Triggered One-Shot Patterns ................................................................................... 654 Figure 77. Terminated Repeat Patterns ..................................................................................... 655 Figure 78. Creating a Sine Wave .............................................................................................. 657 Figure 79. PWM-based Pulse Train .......................................................................................... 658 Figure 80. Pattern-based Pulse Train ........................................................................................ 658 Figure 81. CLR and EN Operation ........................................................................................... 659 Figure 82. CTIMER Interconnection ........................................................................................ 660 Figure 83. Block Diagram for the System Timer .................................................................... 755 Figure 84. Block diagram for the Watchdog Timer Module .................................................... 776 Figure 85. Block diagram for the Reset Generator Module ...................................................... 784 Figure 86. Block diagram of circuitry for Reset pin ................................................................. 785 Figure 87. Block Diagram for the UART Module .................................................................... 793 Figure 88. Block Diagram for ADC and Temperature Sensor ................................................. 809 Figure 89. Scan Flowchart ........................................................................................................ 819 Figure 90. Switchable Battery Load ......................................................................................... 822




Figure 91. Block diagram for the Voltage Comparator Module ............................................... 852 Figure 92. Block Diagram for the Voltage Regulator Module ................................................. 859 Figure 93. BLE/Burst Buck Ton Adjustment Diagram ............................................................ 861 Figure 94. External Components for SIMO Buck .................................................................... 871 Figure 95. External Components for BLE Buck ....................................................................... 872 Figure 96. I2C Timing .............................................................................................................. 876 Figure 97. SPI Master Mode, Phase = 0 ................................................................................... 877 Figure 98. SPI Master Mode, Phase = 1 ................................................................................... 878 Figure 99. SPI Slave Mode, Phase = 0 ..................................................................................... 880 Figure 100. SPI Slave Mode, Phase = 1 ................................................................................... 880 Figure 101. Serial Wire Debug Timing .................................................................................... 884 Figure 102. BGA Package Drawing ......................................................................................... 885 Figure 103. Reflow Profile ....................................................................................................... 886




List of Tables

Table 1: Pin List and Function Table.......................................................................................50Table 2: MCU Interrupt Assignments .....................................................................................78Table 3: ARM Cortex-M4 Memory Map ................................................................................79Table 4: MCU System Memory Map ......................................................................................79Table 5: MCU Peripheral Device Memory Map .....................................................................81Table 6: PWRCTRL Register Map..........................................................................................90Table 7: SUPPLYSRC Register ..............................................................................................91Table 8: SUPPLYSRC Register Bits .......................................................................................91Table 9: SUPPLYSTATUS Register .......................................................................................92Table 10: SUPPLYSTATUS Register Bits .............................................................................92Table 11: DEVPWREN Register.............................................................................................92Table 12: DEVPWREN Register Bits .....................................................................................93Table 13: MEMPWDINSLEEP Register ................................................................................94Table 14: MEMPWDINSLEEP Register Bits .........................................................................94Table 15: MEMPWREN Register ...........................................................................................96Table 16: MEMPWREN Register Bits ....................................................................................96Table 17: MEMPWRSTATUS Register..................................................................................98Table 18: MEMPWRSTATUS Register Bits ..........................................................................98Table 19: DEVPWRSTATUS Register ...................................................................................99Table 20: DEVPWRSTATUS Register Bits ...........................................................................99Table 21: SRAMCTRL Register ...........................................................................................100Table 22: SRAMCTRL Register Bits ....................................................................................100Table 23: ADCSTATUS Register .........................................................................................101Table 24: ADCSTATUS Register Bits ..................................................................................101Table 25: MISC Register .......................................................................................................102Table 26: MISC Register Bits................................................................................................102Table 27: DEVPWREVENTEN Register..............................................................................104Table 28: DEVPWREVENTEN Register Bits ......................................................................104Table 29: MEMPWREVENTEN Register ............................................................................105Table 30: MEMPWREVENTEN Register Bits.....................................................................105Table 31: ITM Register Map .................................................................................................109Table 32: STIM0 Register .....................................................................................................111Table 33: STIM0 Register Bits ..............................................................................................111Table 34: STIM1 Register .....................................................................................................111Table 35: STIM1 Register Bits ..............................................................................................111Table 36: STIM2 Register .....................................................................................................112Table 37: STIM2 Register Bits ..............................................................................................112Table 38: STIM3 Register .....................................................................................................112Table 39: STIM3 Register Bits ..............................................................................................112Table 40: STIM4 Register .....................................................................................................113Table 41: STIM4 Register Bits ..............................................................................................113Table 42: STIM5 Register .....................................................................................................113Table 43: STIM5 Register Bits ..............................................................................................113Table 44: STIM6 Register .....................................................................................................114




Table 45: STIM6 Register Bits ..............................................................................................114Table 46: STIM7 Register .....................................................................................................114Table 47: STIM7 Register Bits ..............................................................................................114Table 48: STIM8 Register .....................................................................................................115Table 49: STIM8 Register Bits ..............................................................................................115Table 50: STIM9 Register .....................................................................................................115Table 51: STIM9 Register Bits ..............................................................................................115Table 52: STIM10 Register ...................................................................................................116Table 53: STIM10 Register Bits ............................................................................................116Table 54: STIM11 Register ...................................................................................................116Table 55: STIM11 Register Bits ............................................................................................116Table 56: STIM12 Register ...................................................................................................117Table 57: STIM12 Register Bits ............................................................................................117Table 58: STIM13 Register ...................................................................................................117Table 59: STIM13 Register Bits ............................................................................................117Table 60: STIM14 Register ...................................................................................................118Table 61: STIM14 Register Bits ............................................................................................118Table 62: STIM15 Register ...................................................................................................118Table 63: STIM15 Register Bits ............................................................................................118Table 64: STIM16 Register ...................................................................................................119Table 65: STIM16 Register Bits ............................................................................................119Table 66: STIM17 Register ...................................................................................................119Table 67: STIM17 Register Bits ............................................................................................119Table 68: STIM18 Register ...................................................................................................120Table 69: STIM18 Register Bits ............................................................................................120Table 70: STIM19 Register ...................................................................................................120Table 71: STIM19 Register Bits ............................................................................................120Table 72: STIM20 Register ...................................................................................................121Table 73: STIM20 Register Bits ............................................................................................121Table 74: STIM21 Register ...................................................................................................121Table 75: STIM21 Register Bits ............................................................................................121Table 76: STIM22 Register ...................................................................................................122Table 77: STIM22 Register Bits ............................................................................................122Table 78: STIM23 Register ...................................................................................................122Table 79: STIM23 Register Bits ............................................................................................122Table 80: STIM24 Register ...................................................................................................123Table 81: STIM24 Register Bits ............................................................................................123Table 82: STIM25 Register ...................................................................................................123Table 83: STIM25 Register Bits ............................................................................................123Table 84: STIM26 Register ...................................................................................................124Table 85: STIM26 Register Bits ............................................................................................124Table 86: STIM27 Register ...................................................................................................124Table 87: STIM27 Register Bits ............................................................................................124Table 88: STIM28 Register ...................................................................................................125Table 89: STIM28 Register Bits ............................................................................................125Table 90: STIM29 Register ...................................................................................................125




Table 91: STIM29 Register Bits ............................................................................................125Table 92: STIM30 Register ...................................................................................................126Table 93: STIM30 Register Bits ............................................................................................126Table 94: STIM31 Register ...................................................................................................126Table 95: STIM31 Register Bits ............................................................................................126Table 96: TER Register .........................................................................................................127Table 97: TER Register Bits ..................................................................................................127Table 98: TPR Register..........................................................................................................127Table 99: TPR Register Bits ..................................................................................................127Table 100: TCR Register .......................................................................................................128Table 101: TCR Register Bits................................................................................................128Table 102: LOCKAREG Register .........................................................................................129Table 103: LOCKAREG Register Bits..................................................................................129Table 104: LOCKSREG Register..........................................................................................129Table 105: LOCKSREG Register Bits ..................................................................................129Table 106: PID4 Register ......................................................................................................130Table 107: PID4 Register Bits ...............................................................................................130Table 108: PID5 Register ......................................................................................................130Table 109: PID5 Register Bits ...............................................................................................131Table 110: PID6 Register ......................................................................................................131Table 111: PID6 Register Bits ...............................................................................................131Table 112: PID7 Register ......................................................................................................131Table 113: PID7 Register Bits ...............................................................................................132Table 114: PID0 Register ......................................................................................................132Table 115: PID0 Register Bits ...............................................................................................132Table 116: PID1 Register ......................................................................................................132Table 117: PID1 Register Bits ...............................................................................................133Table 118: PID2 Register ......................................................................................................133Table 119: PID2 Register Bits ...............................................................................................133Table 120: PID3 Register ......................................................................................................133Table 121: PID3 Register Bits ...............................................................................................134Table 122: CID0 Register ......................................................................................................134Table 123: CID0 Register Bits...............................................................................................134Table 124: CID1 Register ......................................................................................................134Table 125: CID1 Register Bits...............................................................................................135Table 126: CID2 Register ......................................................................................................135Table 127: CID2 Register Bits...............................................................................................135Table 128: CID3 Register ......................................................................................................135Table 129: CID3 Register Bits...............................................................................................136Table 130: MCUCTRL Register Map ...................................................................................138Table 131: CHIPPN Register.................................................................................................140Table 132: CHIPPN Register Bits .........................................................................................140Table 133: CHIPID0 Register................................................................................................141Table 134: CHIPID0 Register Bits ........................................................................................141Table 135: CHIPID1 Register................................................................................................141Table 136: CHIPID1 Register Bits ........................................................................................141




Table 137: CHIPREV Register..............................................................................................142Table 138: CHIPREV Register Bits ......................................................................................142Table 139: VENDORID Register ..........................................................................................142Table 140: VENDORID Register Bits...................................................................................142Table 141: SKU Register .......................................................................................................143Table 142: SKU Register Bits ...............................................................................................143Table 143: FEATUREENABLE Register .............................................................................143Table 144: FEATUREENABLE Register Bits......................................................................144Table 145: DEBUGGER Register .........................................................................................144Table 146: DEBUGGER Register Bits..................................................................................145Table 147: DMASRAMWRITEPROTECT2 Register..........................................................145Table 148: DMASRAMWRITEPROTECT2 Register Bits ..................................................145Table 149: ADCPWRDLY Register......................................................................................145Table 150: ADCPWRDLY Register Bits ..............................................................................146Table 151: ADCCAL Register ..............................................................................................146Table 152: ADCCAL Register Bits .......................................................................................146Table 153: ADCBATTLOAD Register .................................................................................147Table 154: ADCBATTLOAD Register Bits .........................................................................147Table 155: ADCTRIM Register ............................................................................................147Table 156: ADCTRIM Register Bits .....................................................................................148Table 157: ADCREFCOMP Register....................................................................................148Table 158: ADCREFCOMP Register Bits ............................................................................148Table 159: XTALCTRL Register ..........................................................................................149Table 160: XTALCTRL Register Bits...................................................................................149Table 161: XTALGENCTRL Register..................................................................................150Table 162: XTALGENCTRL Register Bits ..........................................................................150Table 163: MISCCTRL Register ...........................................................................................151Table 164: MISCCTRL Register Bits ...................................................................................151Table 165: BOOTLOADER Register....................................................................................152Table 166: BOOTLOADER Register Bits ............................................................................152Table 167: SHADOWVALID Register .................................................................................153Table 168: SHADOWVALID Register Bits .........................................................................153Table 169: SCRATCH0 Register ..........................................................................................153Table 170: SCRATCH0 Register Bits ...................................................................................154Table 171: SCRATCH1 Register ..........................................................................................154Table 172: SCRATCH1 Register Bits ...................................................................................154Table 173: ICODEFAULTADDR Register ..........................................................................154Table 174: ICODEFAULTADDR Register Bits ...................................................................155Table 175: DCODEFAULTADDR Register.........................................................................155Table 176: DCODEFAULTADDR Register Bits .................................................................155Table 177: SYSFAULTADDR Register ...............................................................................155Table 178: SYSFAULTADDR Register Bits ........................................................................156Table 179: FAULTSTATUS Register ...................................................................................156Table 180: FAULTSTATUS Register Bits ...........................................................................156Table 181: FAULTCAPTUREEN Register ..........................................................................157Table 182: FAULTCAPTUREEN Register Bits ...................................................................157




Table 183: DBGR1 Register..................................................................................................158Table 184: DBGR1 Register Bits ..........................................................................................158Table 185: DBGR2 Register..................................................................................................158Table 186: DBGR2 Register Bits ..........................................................................................158Table 187: PMUENABLE Register ......................................................................................159Table 188: PMUENABLE Register Bits ...............................................................................159Table 189: TPIUCTRL Register............................................................................................159Table 190: TPIUCTRL Register Bits ....................................................................................159Table 191: OTAPOINTER Register......................................................................................160Table 192: OTAPOINTER Register Bits ..............................................................................160Table 193: SRAMMODE Register........................................................................................161Table 194: SRAMMODE Register Bits ................................................................................161Table 195: KEXTCLKSEL Register .....................................................................................162Table 196: KEXTCLKSEL Register Bits..............................................................................162Table 197: SIMOBUCK3 Register........................................................................................162Table 198: SIMOBUCK3 Register Bits ................................................................................163Table 199: SIMOBUCK4 Register........................................................................................163Table 200: SIMOBUCK4 Register Bits ................................................................................164Table 201: BLEBUCK2 Register ..........................................................................................165Table 202: BLEBUCK2 Register Bits...................................................................................165Table 203: FLASHWPROT0 Register ..................................................................................166Table 204: FLASHWPROT0 Register Bits...........................................................................166Table 205: FLASHWPROT1 Register ..................................................................................166Table 206: FLASHWPROT1 Register Bits...........................................................................166Table 207: FLASHWPROT2 Register ..................................................................................167Table 208: FLASHWPROT2 Register Bits...........................................................................167Table 209: FLASHWPROT3 Register ..................................................................................167Table 210: FLASHWPROT3 Register Bits...........................................................................167Table 211: FLASHRPROT0 Register ...................................................................................168Table 212: FLASHRPROT0 Register Bits ............................................................................168Table 213: FLASHRPROT1 Register ...................................................................................168Table 214: FLASHRPROT1 Register Bits ............................................................................168Table 215: FLASHRPROT2 Register ...................................................................................169Table 216: FLASHRPROT2 Register Bits ............................................................................169Table 217: FLASHRPROT3 Register ...................................................................................169Table 218: FLASHRPROT3 Register Bits ............................................................................169Table 219: DMASRAMWRITEPROTECT0 Register..........................................................170Table 220: DMASRAMWRITEPROTECT0 Register Bits ..................................................170Table 221: DMASRAMWRITEPROTECT1 Register..........................................................170Table 222: DMASRAMWRITEPROTECT1 Register Bits ..................................................170Table 223: DMASRAMREADPROTECT0 Register............................................................171Table 224: DMASRAMREADPROTECT0 Register Bits ....................................................171Table 225: DMASRAMREADPROTECT1 Register............................................................171Table 226: DMASRAMREADPROTECT1 Register Bits ....................................................171Table 227: DMASRAMREADPROTECT2 Register............................................................172Table 228: DMASRAMREADPROTECT2 Register Bits ....................................................172




Table 229: CACHECTRL Register Map...............................................................................177Table 230: CACHECFG Register..........................................................................................178Table 231: CACHECFG Register Bits ..................................................................................178Table 232: CTRL Register.....................................................................................................179Table 233: CTRL Register Bits .............................................................................................179Table 234: NCR0START Register ........................................................................................181Table 235: NCR0START Register Bits.................................................................................181Table 236: NCR0END Register ......................................................................

Apollo3 Blue Plus MCU Datasheet - Ambiq Micro...- 14 bit ADC at up to 1.2 MS/s, 15 selectable input...

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Transcript of Apollo3 Blue Plus MCU Datasheet - Ambiq Micro...- 14 bit ADC at up to 1.2 MS/s, 15 selectable input...