Apollo Space Mission Historical Document

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Approved: Date: 6

APOLLO GUIDANCE AND NAVIGATION PROGR

Approved: DIR C OR

INSTRUMENTATION LABORATORY

To be published in the IEEE Transactions

on Electronic Computers

E-1880

A CASE HISTORY OF

THE AGC INTEGRATED LOGIC CIRCUITS

Eldon C. Hall

December 1965

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ACKNOWLEDGEMENT

This report was prepa red under DSR Project 55-238,sponsored Manned Spacecraft Center of the National

Aeronautics and Space Administra tion through Contract NAS

9-4065.

The publication of this does not constitute ap-

proval by the National Aeronautics and Space Administration

of the findings or the conclusions contained therein. is

published only for the exchange and stimulation of ideas.

ii


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E-1880

ACASE HISTORY

OF THE AGC INTEGRATED LOGIC C I R C U I T

ABSTRACT

A case h i s t o r y of t h e i n t e g r a t ed c i r c u i t u se d f o r t h e

lo g i c i n th e Apol lo Guidance Cir cu i t i s given. Achieving t h e

re qui re d goa ls of low weigh t, volume, and power coupled wi th

e xt re me h i gh r e l i a b i l i t y n e c e s s i t a t e d t h e u s e of o n e s i n g l e ,

s imp le in t eg ra ted c i r c u i t f o r a l l l o g i c f u nc t io n s. A b r i e f

d e s c r i p t i o n of th e evo lu t ion of t he computer des ign i s given

along wi th a genera l d is cuss ion of some of the engineering and

design problems which arise w i t h t h e u s e o f a s t an d a rd ized

semicon du ctor mo n o l i th i c in t eg ra ted c i r c u i t .

The f l i g h t q u a l i f i c a t i o n p r oc ed ur e is d esc r ib ed .

A f t e r t h e q u a l i f i e d s u p p l i e r s l i s t has been formed, each l o t

sh ipped from any qua l i f i ed su ppl ie r i s exposed t o a sc r een

and burn- i n p rocedu re fo llowed b y f a i lu r e an a l y s i s o f

g e n e r a t e d f a i l u r e s . The l o t i s accepted or r e j e c t e d o n t h e

basis of the number of f a i l u r e s g en e ra ted and th e ty p es of

fa i l u r e modes genera ted . The r e l i a b i l i t y h is t o r y o f t h e NOR

Gate i s giv en showing di f fe r e nc e s among vendor s, showing

dif fer enc es among l o t s shipped from a s i n g l e v en do r , and

updat ed f i e l d f a i l u r e r a t e s .

by Eldon C. HallDecember 1965

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TABLE OF CONTENTS

Sec t ion

I INTRODUCTION

ENGINEERING ASPECTS OF THE COMPUTER

R E L I A B I L I T Y

R ELI AB I LI TY HI STQR Y DATA

V SUMMARY

3

7

20

28

32

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SECTION I

INTRODUCTION

M il i t a r y and s p ace o b j ec t i v e s r eq u i r e t h e ve r y l a t e s t

i n t echno log ic a l deve lopment coup led wi th r e l i a b i l i t y goa ls

t h a t r e q u i r e s u c c e ss f u l o p er a t i on f o r s e v e r a l y e a r s . A

compromise must o f t e n be made between the use of new tech-

nology and h igh r e l i a b i l i t y ob jec t ive s . With jud ic ious p lann ing

t h i s compromise can be i n s t i t u t e d e f f e c t i ve l y . For example,

in tegra ted c i rcu i t s us ing p lanar t echno logy have made new

obje c t iv es poss ib le by reduc ing t he s i ze and weight o f a system

w h i le i n t r od u c ing an imp o rt ant f u tu r e r e l i ab i l i t y g a in .

The i n h er e n t r e l i a b i l i t y g a i n s must be implemented i n

th e des ign s ta ges of th e computer. Hence t he decis ion t o u se

o ne s imp le s i n g l e l o g i c e l em en t f o r t h e l o g i c i n the

Guidance Computer. This re su lt e d i n hig h volume procurement

o f t h e i n t eg r a t ed c i r c u i t f rom m u l t i p l e s o u r ce s, so t h a t t h e

n eed ed h ig h r e l i ab i l i t y co u ld be developed and proven within

a sho r t per iod of t i m e .

The s ta nda rdi zat ion approach, which is p a r t i c u l a r l y

adap tab le t o d i g i t a l computers , has been demonst rated w i t h

th e Po l a r i s f l ig h t computer and extended wi th in te gra te d

c i r c u i t s t o th e Apollo Guidance Computer. Both computers were

designed t o use a th r ee inpu t NOR G ate a s t h e o n ly l o g i c element.

A l l log ic func t io ns a r e genera ted by in te rconn ec t ing the t h r e e

in p u t NOR Gate w i th no ad d i t i o n a l l o g i c b lo ck s , r e s i s t o r s , or

cap ac i t o r s . A t f i r s t g la nc e, it appears tha t us ing on ly one

type o f lo g i c b lock g re a t ly increases th e number of blocks re-

qui red f o r ' t h e computer. But , by jud i c iou s ly se le c t in g and

o r g an i z in g t h e l o g i c f u n c t i o n s it is quick ly apparen t tha t f ew

addi t ion a l b locks a r e necessary. The few addi t ional u n i t s

r e q ui r e d a r e g r e a t l y c o u n te r b al an ce d by t h e i n cr e as e d r e l i a b i l i t y

gain dur ing both t he manufactur ing of components and fa br ic at io n

of t h e components i nt o modules.


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The lo g i c e lement u t i l i z ed i n th e Apol lo Guidance

Computer is t h e t h r e e i n pu t NOR Gate as shown in Fig. 1. A t

t h e t i m e t h a t t he d eci s io n was made t o u s e i n t e g r a t e d c i r c u i t s ,

t h e NOR Gate, a s shown, was th e only device ava i l ab le i n la rg e

q u a n t i t i e s . The s im p l i c i t y of t h e c i r cu i t a ll ow ed s ev e r a l manu-

f ac tu r e r s t o p ro du ce i n t e r ch ang eab l e dev i ce s so t h a t r e a s o n ab l e

compe tit i on was ass ure d. Because of rec en t pro ces s development

i n i nt e g ra t e d c i r c u i t s , t h e NOR Gate has been ab le t o remain

compet i t ive on b a s i s of speed, power and noise immunity.

T h i s c i r c u i t i s used a t 3 V and b u t is r a te d a t and

Unpowered temperature rating i s 150C. The b a s i c

s i m p l i c i t y o f the t h r e e i n p ut g a t e a i d s a n e f f e c t i v e s c r e en i n g

process . A l l t r a n s i s t o r s a n d r e s i s t o r s can be t e s t e d t o i n s u re

product uniformity . The s i m p li c i t y o f t h e c i r c u i t a l s o a id s i n

th e qu ick de te c t i on and d iagnos ing of i n s i d i ou s f a i l u r e s w it h ou t

exte ns ive probing a s r equir ed with more complicated c i r cu i t s .

One ad d i t i o n a l i n t eg r a t ed c i r c u i t used i n t h e A po ll o

Guidance Computer is the memory sen se am pl if ie r. A s seen in

Fig. 2 , t h e c i r c u i t is con sid era bly more complex than th e

NOR Gate. The exper ience with t h i s more complicated ci r c u i t

has been comparable with t he l og ic ga te . However, s i nc e it

i s a l o w usage i t e m t h e r e is a v a i l a b l e less information of

h i s t o r i c i n t e re s t , t h a t is, r e l i a b i l i t y i n f o r m a t i o n s u c h a s

f a i l u r e rates and modes of f a i l u r e s . The b a l an ce of t h i s r e p or t

r e l a t e s t o h i s t o r y o f t h e l o g i c g a te .

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rI

I

I

IIIIIII

I

IIIIIIII

IIIIII

III

I

I

I

II

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1

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5 .


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SENSE AMPLIFIER CIRCUIT

S E N S ELINEINPUT

REFERENCEVOLTAGE

I

+ VOLTS

I

INTEGRATED CIRCUIT

I

I

I

I

I

I

II

I

OUTPUT


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SECTION

ENGINEERING ASPECTS O F THE APOLLO COMPUTER

Figure 3 p i c t u r e s the Block Apollo Guidance Computer.

Th is v e r s io n d i f f e r s from th e Block I Computer i n t h a t the

memory, i ns t ru c t io n and input ou tp ut was inc rea se d. The Block

Computer a l s o us es a d u a l g a t e i n a f l a t pa cka ge r a t h e r than

the s i n g l e ga t e i n a TO-47 used i n Block I . Fig u res 4 and 5

i l l u s t r a t e th e p ackaging t ech n iqu es used in the Block

comput er. The Block l o g i c s t i c k s a r e made us i ng t h e f l a t

package welded t o mul t i l ayer in te rcon nect ion boards . The

modules a r e in te rconnecte d us ing a t r a y which is wired by

machine w i r e wrap technique as shown i n F ig . 6 . Two i d e n t i c a l

Displa y and keyboards a s shown i n Fig. 7 provide t h e man machine

i n t e r f a c e w i t h the computer. Table I i s a general summary of

the Block c ompute r c h a r a c t e r i s t i c s .

Since the l o g i c d e s i g n of the compu te r was r e s t r i c t ed t o

a s i ng le type of ga t e , a method t o p rov ide fan- in and fan- out

expansion w a s provided a s shown i n F ig . 8 . Also, methods that

w e r e used t o provide int erc onn ect ion s between l og ic and memory

c i r c u i t s and c o nn e ct i on s t o ou ts id e world a r e shown i n F i g . 9.

A l l high f requency in format ion t r an sf er between t he computer

and per i fe ra l equ ipment i s accomplished w i t h t ransform er coupled

c i r c u i t s as shown i n t h e to p view. The second row i s the t y p e

o f c i r c u i t used in t h e memory in t e r f a ces and f o r l o w frequency

DC l e v e l ty p e s ig n a l s . The r ece iv e r is shown on the r i g h t .

The bottom r o w p ro v id es l o w f requency DC l e v e l i n p u t s .

I n t e r e s t i n g and s u b t l e p ro bl em s a r i s e w i t h the use o f

i n t eg r a te d c i r c u i t s . To i l l u s t r a t e , F i g . ( a ) d e p i c t s a

v er y d e s i ra b l e c i r c u i t t h a t c an be used t o d r i v e l o n g cables

for ground test equipment while requir ing no power drain from

t he a i rb orne equ ipment . Figure 10 (b) shows the same c i r c u i t

but includes some of the paras i t i c d i o d e s n o t u s u a l l y repre-

s e n t ed i n t h e i n t e g r a t e d c i r c u i t . When p o i n t ( x ) rises above

2 v o l t s , d i od e c a p a c i t o r coupling occurs th rough th e r e s i s t o r

s u b s t r a t e which a c t i v a t e s the u n u s e d t r a n s i s t o r s . T h i s coupl ing

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Figure 3

8


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W

MODULE MOUNTING FRAME ANDMULTILAYER BOARDMICROLOGIC ASSEMBLED

TO FINAL WELDING

Figure 4


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10


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11


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Figure

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AGC CHARACTER I CS

Word LengthNumber SystemMemory Cycle TimeFixed Memory RegistersErasable Memory RegisterNumber of Normal Instructions

Interrupt OptionsAddition TimeMultiplication TimeDouble Precision Addition TimeDouble Precision Multiplication Subroutine

increment TimeNumber of CountersPower ConsumptionWeightSize

nterrupt, I ncrement, etc.

Time

15 Bits 1 ParityOne's Complement11.736,864 Words2,048 Words

1010

23.446.835.1575

11.729

Watts +58 Pounds (Computer Only)1.0 Cubic Foot (Computer Only)

Table I.


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LOGIC DESIGN

SYMBOL FOP POWER NOT CONNECTED

0

OUTPUT

0

0

0

H I G H FAN OUT GATE

HIGH FAN I N GATE

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i s a feedback path which slows up th e pu ls e rise times. The

rise time w i l l be a f u n c t i o n o f t h e g a in of t h e unused t r a n s i s t o r

and a l s o a f u nc t i o n o f r ep e t i t i o n r a t e of th e d r ive which tends

t o t u r n t h e t r a n s i s t o r s o f f a t hi gh r e p e t i t i o n rates. Connecting

a l l u nused i n p u ts t o t h e emitter (OV) w i l l preven t o r minimize

the feedback thus speeding up the pu lse response. Another

i n t e re st i ng and much dis cuss ed problem is t h a t o f no i s e i n

l o g i c c i r c u i t s us in g i n t eg r a t ed c i r c u i t s . I t i s w e l l known

t h a t a l l d i g i ta l computer s have no ise prob lems and the re a re

w e l l known design techniques which when properly applied w i l l

minimize these p ro bl ems . I n t h e e l e c t r i c a l d es ig n a s w e l l a s

t h e mechanical d es ign there a r e t r a de o f f s t ha t must be made

i n o r d e r t o meet a l l o f t h e ground r u l e s placed on the computer

des igner . Noise i s o ne of t h e ma jo r co n s t r a in t s t h a t must be

cons idered dur ing the design. One m u s t co n s ide r b o th s e l f

induced and ex te rn al ly induced nois e. Although t h e cause is

d i f f e r e n t f o r b ot h t y pe s , the e f f e c t is u s u a l l y the same and

can be i l l u s t r a t e d by F ig . 11. From t h i s f ig ure it i s seen

how s w it chin g cu r r en t s i n t h e c i r c u i t g ro un d p l an e can cau s e

v o lt a ge t r a n s i e n t s t h a t w i l l er roneous ly switch t h e t r a n s i s t o r s

shown. These ground cur r en t s can a l so be induced from the

o u t s id e e i t h e r b y con du ct ed o r r ad i a t ed i n t e r f e r en ce . To

maximize the immunity of the computer the des igner should ,

1. S e l e c t c i r c u i t s t h a t ha ve maximum immunity:

t h e r e is abou t a f ac to r of 2 r ea l izab le be tween

the worst and best i n t e g r a t e d c i r c u i t s .

2 . Provide good ground pla ne s and s ig na l pat hs.

3 . Provide proper s h i e ld in g , g ro un ding and f i l t e r i n g

of t h e computer, and a l l i n t e r f a c e wires.

Obviously one must compromise here a l s o , o th e r w i se t h e

p r o t e c t i o n as w e l l as t h e magni tude of the no ise would cont inue

t o e s c u l a t e . I n the c h o i c e o f t h e NOR Gate, the Apollo Computer

may have sa cr if ic ed some nois e immunity f o r s im pl ic it y and

av a i la b i l i ty . Tes t ing o f th e f in i she d computer has shown th a t

i t s s u s c e p t i b i l i t y is much lower than the limits s p e c i f i e d i n

MIL-1-26600 which is t h e s p e c i f i c a t i o n f o r e l e ct r om a gn e ti c

c o m p at i b i l it y . I n f a c t , i n o rd e r t o l o c a t e a r e a s o f wea kness,

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18


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spark d i scharges have been used dur ing te s t in g .

r a d i a t i o n s u s c e p t i b i l i t y tests do n ot g en e r a t e l ev e l s

enough t o i nd uce comp uter f a i l u r e . I n f a c t , MIL-1-26600

i s weak in o ther a rea s when app l ied t o d i g i t a l computer s. For

example, a power tr an si e nt between a power i n p u t l i n e and case

is notor ious fo r induc ing t roub l es and loca t ing areas of weak-

n es s , a l t ho ug h t h i s test is n o t a requirement of t h e MIL spec.

The Apollo computer has been subj ect ed t o and passed t he se

more s t r ingent tests.

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SECTION

R ELI AB I LI TY

Bec ause o f t h e h i g h r e l i a b i l i t y a p p l i c a t i on o f the

Apol lo Gu idance Computer , t he r e l i a b i l i t y a s su rance o f t h e

i n t eg r a te d c i r c u i t s w i l l be disc usse d. The procedu res have

been p rev ious ly r epo r t ed i n deta i l , b u t w i l l be summarized

h e r e .

I t became immediately obvious that small-sample

stress t e s t i n g c o ul d n o t g u a r an t e e t h a t e ac h pu rc ha se d lo t

would meet t h e Apo llo i n t e g r at e d c i r c u i t f a i l u r e rate r equ i re-

ments . The MIL-S-19500D s t a t i s t i c a l sampl ing procedure was both

n o t a p p l i c a b l e n or p r a c t i c a l . F ur th er mo re , a s lo ng as a l l

f a i l u r e modes w e r e no t com ple t e ly s c reenab l e , one-hundred

p e r c en t s c re e ni ng a l o n e was n o t s u f f i c i e n t t o a t t a i n the

r e qu i re d h ig h r e l i a b i l i t y g oa l s. A s t u d y of t h e v a r i ou s

f a i l u r e modes o f i n t e g r a t e d c i r c u i t s c r e a t e d t h e dilemma

whereby some of t h e f a i l u r e modes were e a s i l y s c re e ne d by

s t andard s c reen ing t echn iques and o th e r s on ly occas iona l l y

d e t e c t e d . N o assurance could be made with any reasonable

c o nf i de n ce t h a t t h e d e v i c e s wi t h t h e s e t ro ub le so me d e f e c t s

had been removed from t h e l o t . T o overcome t h i s problem,l o t a c c e p t a n c e cri ter ia w e r e establ ished which would

i d e n t i f y w i t h h i g h c o nf i d e nc e t h o s e l o t s i n w hich i n s i d i o u s

f a i l u r e modes were not p reva len t and scre ening had been

adequat e . P rovid ing an e f fe c t i v e f a i l u r e mode de t ec t i o n

syst em, t h e p rocedure f o r l o t acceptance i s based on

hundred pe rcen t nondes t ruc t i ve tests and sample d e s t r u c t i v e

t e s t i n g . A l l t h e f a i l u r e s g e ne ra te d f rom t h e t e s t i n g are

complete ly analyzed . The f a i lu re s are t h e n c l a s s i f i e d b y

grou ps and compared t o the acceptance criteria. must

be emphasized that the l o t is a c ce p te d o r r e j e c t e d n o tonly because o f th e number o f f a i l u r e s b u t a l so on whether

the f a i l u r e modes genera t ed were nonsc reenab l e o r i n s id ious

and long t i m e dependent .

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i

The Apollo Guidance and Navigation Specification,

ND 1002248, is th e c e nt r a l document on which each procured

l o t q u a l i f i c at i o n i s based. document sp ec if ie s th e

p ro ce du re s re q ui r ed f o r l o t a c c ep ta nc e r e s u l t i n g i n f l i g h tq u a l i f i e d p a r t s . I n p a r t i c u l a r , ND 1002248 , spec i f i es t he

d e t a i l s o f:

1.

2.

3 .

4.

5 .

6 .

7.

The operational and environmental stress tes t

procedures and sequence r e f e rr e d t o a s

the screen and burn- in procedure. The sc reen

and burn- in procedure was des igned t o de te ct

fa i l u r e modes which could occur d ur ing t h e normal

stress and environmental app l i ca t i on of t h e

device.

The e l ec t r ic a l parameter tests t o be performeddur ing the screen and burn- in procedure. The

tests as d e f i n ed were determined during the

engineer ing eval uat ion and were chosen t o

de te c t f a i l u r es and as su re p roper computer

D ef in i t i o n s o f f a i l u r e s . F a i l u r e s h av e b een

d e fi n ed a s c a t a s t r o p h i c , s e v e r a l c a t e g o r i e s of

non- ca tas troph ic, induced, and inspec t i on fa i l u r es .

Al loca t ion o f f a i l u r es . The cond i t i ons are def ined

f o r removal from the screen and burn- in procedureo f f a i l u r e s which a r e t o be f or wa rd ed t o f a i l u r e

a n a l y s i s .

Classes of fa i l u re modes. Fa i l ur e modes ar e

c l a s s i f i e d a c co rd i ng t o s c r e e n a b i l i t y and

d e t e c t a b i l i t y .

Maximum acceptable number of f a i l u r e s p e r c l a s s of

f a i l u r e mode f o r a l l 100% e l e c t r i c a l parameter

test s t a t i o n s .

Maximum acc ep ta bl e number of f a i l u r e s f o r non-

e l e c t r i c a l tests and a l l sample electrical para-meter tests.

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8 .

9.

10.

To

The r e p o r t r e q ui r e d f o r e ac h f l i g h t q u a l i f i e d l o t .

The report must co n ta in th e co mp le te h i s to ry o f

t h e l o t w it h t h e s p e c i f i c d a t a a nd a n a l y s i s r e q u ir e d

or f l i g h t q u a l i f i c a t i o n .

D at a and f a i l e d p a r t s s t o r a g e . I n o r d e r t o a s s u r e

t r a c e a b i l i t y and f u t u r e a n a l y s i s sh ou ld f i e l d

f a i l u r e s oc c u r , t h e co n d i t io n s of d a t a and f a i l e d

p a r t s s t o r a ge a r e g iv en .

Contra c tua l requ i rements t o implement l o t

f i c a t i o n .

a s s i s t t h e u n d e rs t and ing o f th e l o t accep tan ce p ro-

cedures , a genera l d is cuss i on of th e semiconductor pa r t vendor

s e l e c t i o n and f l i g h t q u a l i f i c a t i o n p r oc ed ur e s w i l l be given

a s performed f o r t he Apollo Guidance and Navigation Computer.

The process begins w i t h an assessment of t he vendor ' s

a b i l i t y t o s u p pl y d e v i c e s , t h e i n s t i t u t i o n of component

s t an d a rd iza t i o n i n d es ig n s , and th e p r e l im in a ry s tu dy of

device f a i l u r e A block diagram of t h i s p r e l i m i n a r y

evaluation which precludes any production procurement is

g iv en in F ig . 1 2 . The qual i f ica t ion procurements which

s u pp ly p a r t s f o r t h e q u a l i f i c a t i o n t e s t i n g and e n g in e er i ng

ev a lu a t io n s e s t ab l i sh ed th e man u fac tu re r ' s d ev ice p ro cess in g .

One of t h e i n d i r e c t r e su l t s o f t h e i n i t i a l p ro cu re me nt s i s

th e ear ly de te c t io n of new fa i l u r e modes. The conclus ionso f th e f a i l u r e an a ly ses a r e th en f ed b ack t o th e man ufactu re r

who i n t u r n a t t em p ts c o r r e c t i v e a c t i o n . T hi s c y c l i c p ro ce du re

is continued u n t i l th e most obvious problems have been el i minat ed

Ad d i t io n a l ly , t h e e a r ly d e tec ted f a i l u r e modes cou pled wi th p as t

e x pe r i en c e a r e u t i l i z e d t o d es i gn the q u a l i f i c a t i o n t e s t i n g .

The formal ized qua l i f i ca t i on t es t i ng beg ins when th e

v en d o r s h av e su p p l i ed d ev ices r ep re sen ta t iv e of t h e i r f i n a l i z e d

manufactur ing process. It is e x tr e me ly i m po rt a nt t h a t a l l

q u a l i f i c a t i o n a n d e n g i n e e r i n g t e s t i n g be performed on devices

f ab r i ca ted f ro m th e i d en t i ca l p ro cess u sed t o su pp ly compu terp ro d u ct io n d ev ices . The q u a l i f i c a t io n tests s u b j e c t t h e

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2 3 .


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dev ices from var ious vendors t o th e extremes of and, t o a

l im i ted ex ten t , beyond usage cond i t ions in an a t tempt t o

de te ct f a i l u r e modes which could occur i n normal app l ica t ions .

The engineer ing evalua t ion s a re performed s imultaneous ly

w i t h t h e q u a l i f i c a t i o n p ro ced u re s t o d e t er m in e d ev i ce s peed ,

ca pa bi l i ty , noi se immunity , and ope ra t in g temperature

range. From t h i s eva lua ti on, t h e optimum computer design is

developed. I t is a t t h i s t i m e t h a t tests ar e conducted t o

d e te r min e t h e e l ec t r i c a l p a ram ete rs w hich w i l l insure p roper

dev ice opera t ion i n every usage mode and t o es ta bl is h the

l o g i ca l d e s ig n rules f o r the computer.

The qua l i f i ca t i on and eng ineer ing eva lua t ions de te rmine

tho se vendors who a re cap able of supplyin g the semiconductor

pa r t and who do no t ex h i b i t any g ross r e l i a b i l i t y prob lems .

T h e q u a l i f i c a t i o n tests a l on e a r e i n s u f f i c i e n t t o d et er mi ne

t h e a b i l i t y o f a vendor t o c o n t r o l h i s p r oc e s s, b u t l a r g e

volume da ta fed back f rom screen and

burn- i n s u p p l i e s ex t en s iv e vend or h i s t o r y .

U t i l i z i n g the data generated dur ing the eng ineer ing

ev a lu a t i o n s an d q u a l i f i c a t i o n tests, t h e s p e c i f i c a t i o n c o n t r o l

document (SCD) is prepared . The SCD is the document t o which

p r o d u c t i o n p a r t s are boug ht. Based on the q u a l i f i c a t i o n by

vendors, the q u a l i f i e d s u p p l i e r s l i s t is formed which

s p e c i f i e s th e vendors from whom the produc t ion par t s s h a l l

be procured.

Once the SCD and QSL have been released, produc t ion

procurement may begin. Figu re 13 pi ct ur es the genera l f low

o f p a r t s an d d a t a as r e qu i re d f o r f l i g h t q u a l i f i c a t i o n . The

devices procured by l o t s proceed through the screen and

i n test sequence.

Upon of screen and burn- in, the l o t is s t o r e d

u n t i l f a i l u r e a na l y si s is completed. A l l f a i l e d u n i t s are

ca ta logued , ana lyzed , and c l as s i f i ed t o complete the l o t

assessment, followed by a w r i t t e n r e p o r t . I f t h e l o t

passed , a l l the d e v ic e s t h a t pa ss ed a l l tests can be i d e n t i-

f i e d as a f l i g h t q u a l i f i ed p a r t w i t h a new p a r t number and

24 .


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25

I


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s e n t f o r produ cti on usage. Only t h e semiconductor p a r t w i t h

t h e f l i g h t q u a l i f i c a t i o n p a r t number c a n be used i n f l i g h t

q u a l i f i ed compu te r a s semb l i es . From fa i l u r e an a ly s i s , r e j ec ted

p a r t s p ro ce ed t o reject s t o ra ge where they w i l l be a v a i l a b l e

f o r f u t u r e s t ud y i f re q u ir e d . I n the e ve nt t h a t t h e l o t

fa i l ed because o f c i rcumstances no t comple te ly def ined th rough

f a i l u r e c l as s i f i c a t i on , t h e l o t can be f l i g h t q u a l i f i e d b y

waiver . The waiver must be au thor ized by NASA and w i l l

accompany the computer. c e r t a i n l i m i t e d c as e s , p a r t s f rom

a f a i l e d l o t may be r e su bmi t t ed f o r r e sc r een in g .

The accumulated d at a from t h e scr een and burn- in pro-

cedure (Fig . 14) and f a i l u r e a n a l y s i s are u t i l i z e d t o f u r t h e r

ev a lu a te t h e v en do r p ro d u c t io n ca p a b i l i t y and h i s d ev ice

q u a l i t y and r e l i a b i l i t y . T h i s i n t u r n a f f e c t s a v e n do r ' s

c o nt i nu e d s t a t u s as a q u a l i f i e d s u p p l i e r .

2 6 .


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S SEQUENCE

FailuresRemoved

Visual I

1

failures toAnalysis Electrical Test

1

I Thermal Cycle(Sample

I I

Centrifuge

Failures to

Analysis Test

Life hrs

Failures toAnalysis Electrical Test To Lot

Figure 14


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SECTION I V

RELIABILITY HISTORY AND DATA

The r e l i a b i l i t y h is t o r y of t h e NOR Gate w i l l exemplify

some of t h e d i f f i c u l t i e s encoun t ered and succes ses ach ieved i n

b u i l d in g a d i g i t a l c omputer u t i l i z i n g i n t e gr a t e d c i r c u i t s .

Table is a summary o f t he r e l i a b i l i t y da t a fo r the

NOR Gate accumulated up t o October 1964. This d a t a h a s b e e n

p r e v i o us l y d is c u ss e d i n d e t a i l2

b u t is presen t ed he r e t o show

th e extreme di ff er en ce s among manufacturers . The e l e c t r i c a l

f a i l u r e d e f i n i t i o n s d u ri n g s c r e e n and bu r n- in were any in-

operab l e dev i ces or any dev i ce exceeding t h e e l e c t r i ca l

sp ec i f ica t io ns . The percentages inc lud e approximate ly 0 .05

t o combined i nduced f a i l u re s and t e s t i n g e r ro r s . The

i n i t i a l q u a l i f i c a t i o n r e s u l t s a r e a l s o i n cl ud ed i n T able

where t he f a i l u re de f i n i t i on was an i noperab l e dev ice . The

extreme di ff er en ce s among the manufacturers is a l so r e f l e c t e d

i n t he f a i l u re modes genera t ed du r ing bo th the i n i t i a l q ua l i f i-

ca t io n and scree n and burn- in. For the d a t a i n T a b le

Manufacturer A r a re ly e xh ib i t ed t h e nonsc reenab l e, and /o r

long- t ime dependent f a i l u r e modes while both Manufacturers

B and C c o n s i s t e n t l y d i d . The i n op e r ab l e f a i l u r e s g e n er a t ed

a t computer us e cond i t ions fo r Manufacturers B and C were of

th e nonscreenable , long- t ime dependent f a i l u r e modes.

I t is i n t e r e s t i n g t o n o t e t h a t the same dev i ces used t o

genera t e the data of Vendor A of Table have s i nc e exh ib i t ed a

f i e l d f a i l u r e r a t e of h o ur s a t 90% conf idence a s of 3

30 September 1965 w i t h o ne o p e r a t i o n a l f a i l u r e . The same

devices of Vendors B and C have not improved their f a i l u r e

r a t e s b e ca u se a d d i t i o n a l f a i l u r e s h av e oc c ur r ed .

The more s u b t l e d i f f e r e n c e s i n q u a l i t y and r e l i a b i l i t y

may be obse rved i n va r i a t i o ns of l o t s shipped from one manu-

f a c t u r e r . The d a t a of F i g. 1 5 i n d i c a t e s the num er i ca l va r i a t i ons

2 8 .


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OCT 64

A

B

C

P R E QUALIFICATIONFAILURES

5

26

58

& BURN-INFAILURES

TOTAL

3 . 8

5.0

2nd & 3rd

0.3

1.7

FAILURE RATES AT US ECONDITIONS

90% CONFIDENCE

0.005% hrs (0 FAILURES)

hrs (2 FAILURES)

1.8% (26 FAILURES)

SEPT VENDOR A- ( 1 FAILURE)

VENDOR C-N O IMPROVEMENT

Table


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-3

0

0 0 0 0

0

30


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f o r t h e NOR Gate from one qu al if ie d manufacturer. Here, only

th e i n o pe r abl e f a i l u r e s a r e p lo t t e d and i n du ced f a i l u r e s and

te s t in g e r ro r s have been e l imina ted from th e da ta . These

NOR Gates were exposed t o t he scr een and burn-

in procedure a sshown i n Fig. Each poi nt in Fig . 15 rep res ent s a shipment

l o t of t o 5000 NOR Gates. Figur e 15 (a ) shows th e per-

c e n t c a t a st r o p h i c f a i l u r e s a t t h e incoming e l e c t r i c a l tests.

Figure 15 (b) shows th e percen t c a tas t roph i c f a i l u r es which

were g ene r at ed a f t e r s t r e s s in g w i th i ncoming ca t a s t r o p h i c

fa i l u r es removed. There a r e fewer po i n t s p lo t te d i n F ig . 15

(b) than i n Fig. 15 ( a ) , since some lo ts n ot u se d f o r f l i g h t

hardware w e r e not exposed t o screen and burn- in . There was

no buying o f th e th re e inpu t NOR Gate between June and October

1964, so t h a t t h e l i n e p ro du ci ng t h e i n t e g r a t e d c i r c u i t wastemporar i ly d iscont inued. A s a r e su l t when t he p roduc t ion

l i n e was r e in s t a t ed , s ev e r a l lo ts a f t e r October 1964 indic ated

a new region of i ns ta bi l i ty . A t t h a t time rapid feedback t o

th e manufacturer from th e cus tomers resu l t ed i n subsequent

decrease o f c a tas t roph i c f a i lu re s dur ing the sc reen and burn-

in p rocedure .

31 .


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SECTION V

SUMMARY

Controversy still e x i s t s w i t h r e s p ec t t o t h e d e c i s io n

made i n th e des ign o f t h e Guidance Computer. I n p a r t i c u l a r

s t an d a rd iza t io n of lo g ic g a te s i s claimed t o have many di sadv an-

t ag es . B ut , a s a result o f s t a n d a r d i z a t i o n t h e NOR Gates o f t h e

Apo llo Computer h as been ab le to e s t ab l i s h th e r e l i ab i l i t y wi th

o p e r a ti n g f a i l u r e r a t e s l owe r t h an e v er b e f o r e r e a l i z e d .

T o dat e , four tee n Block I computers have been bu i l t

and a r e i n f i e l d use f o r f l i g h t s i m ul a ti o n, s p a c e cr a f t i n t e g r a t i o ntest , an d v a r io u s q u a l i f i ca t io n tests. These computers have

accumulated 38,442.0 hours of oper at in g time as o f 30 September 1965.

The f i r s t prototype computer was opera t in g i n Ju ly 1963 wi th th e

R ay th eo n b u i l t f l i g h t co mp u te r o p e ra t in g i n January 1964.

32.


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REFERENCES:

1. J. P ar t r i d g e , E.C. H a l l , L.D. Hanley, "The Appl ica t ion

of F ai lu re Analys is i n Procur ing and Screening of

I n t eg r a t ed p r e s en t ed a t the Fourth Annual

Symposium of P h ys i cs of F a i l u r e i n E l ec t r o n i c s ,

November 1 6 , 1965.

2 . J. P ar t r i d g e , L.D. Hanley, E.C. H a l l , "Progress

R ep or t on A t t a in ab l e R e l i a b i l i t y o f I n t eg r a t ed

Ci rcu i t s f o r Sys tems Microe lec t ron ics

and Large Systems, Edited by Wiley, Spandorfer1965.

33 .


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4

E- 1880

DISTRIBUTION LIST

Internal

Adams

J . Arnow (Lincoln)

R.

P. F. Siraco

A. Boyce

R. Boyd

R. Byers

G. Cherry

N. CluettE. Copps

W. Coleman

R. Crisp

G. Cushman

J. Dahlen

J.

E. Duggan

J.

R. Euvard

J. B. FeldmanP.

S. Felix

J. Flanders

J. Fleming

L.

J. Gilmore

F. Grant

D. Grief

Eldon Hall (100)

W.Heintz

T. Hemker

E. Hickey

D. Hoag

F. Houston

L. B. Johnson

M. Johnston

B. Katz

A. Koso

M. Kramer

W. KupferA. Laats

D. Ladd

J. L a r se n

L. Larson

J.

T. J.

T. M.

D. Lickly

R.

MartinageG.

J.

R.

R. Millard

Jam es Mi l l er

John Miller

R. Mudgett

J. Nevins

J.

E. OlssonW. Pat terson

M.

M. Richter

J. Rhode

K. Samuelian

Sarmanian

G. Schmidt

W. Schmidt

R. Scholten

E. Schwarm

J. SciegiennyN. S e a r s

J.

W.

T. Shuck

J. Sitomer

W. Stameris

J. Stone

J. Suomala

W. Tanner

R. Ther r i enW. Toth

M. Trageser

R. Weatherbee

R, White

L. Wilk

M. Wolff

R.

W. Wrigley

D. Yankovich

Apollo LibraryL i b r a r y (6 )


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External

W. RhineNASA

I,. Holdridge (NAA

T. Heuermann

AC Electronics

Kollsman

Raytheon

Major H. Wheeler

MSC:National Aeronaut ics and Space AdministrationManned Spacecraft CenterApollo Document Distribution OfficeHouston, Texa s 77058

National Aeronautics and Space AdministrationLangley Research Ce nterHampton, VirginiaAttn: Mr. A. T.

GAEC:Grumman Aircraft Engineering CorporationData Operations and Services, Plant 25Bethpage, Long Isl and, New YorkAttn: Mr. E. Stern

NAA :North Ame ri can Aviation, Inc.Space and Information S ystem s Division12214 BoulevardDowney, CaliforniaAttn: Apollo Data Requi reme nts

Dept. 41-096-704

NAA RASPO:NASA Resident Apollo Space craf t Pr og ra m OfficeNorth Ame ri can Aviation, Inc.Space and Information Syst ems DivisionDowney, Cali fornia 90241

National Aer onautics and Space AdministrationResident Apollo Spacecraft Program Officer

Dept. 32-31AC Electr onics Division of Ge nera l MotorsMilwaukee 1, WisconsinAttn: Mr. W. Swingle

ACSP RASPO:

(25

+

(18 +


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External

ACSP RASPO:Mr. Pe te r sonBureau of Naval Weapon sc Raytheon CompanyFoundry AvenueWaltham, Massachusetts

M r . S. SchwartzDOD, DCASD, Ga rden Ci ty60 5 Stewart AvenueGarden City, L. I . , N.Attn: Quality Ass ura nce

D. R. KohlsAFPROAC Electr onics Division of General Motors

Milwaukee 1, Wisconsin 53201

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