Aoyama Gakuin University - mstl.atl.calpoly.edu
Transcript of Aoyama Gakuin University - mstl.atl.calpoly.edu
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Int’l Collaborator: Aoyama Gakuin University
UCI Satellite (UCISAT)UCI Satellite (UCISAT)Mission: Launch UCISAT-1 into LEO to capture Earth images with CMOS payload
Aoyama Gakuin University Team
UC Irvine Team
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Subsystems:• *Attitude Control (ADCS)• Communications• C&DH• Payload (CMOS)• Power• Structures
UCI Satellite (UCISAT)UCI Satellite (UCISAT)
Specs:• 1200 baud, 437.405 MHz downlink • 1/2 wavelength dipole antenna • 350g Aluminum structure (6061/7075)• 5 triple-junction Emcore solar cells• 2 3.7 V Li-Ion batteries• Low-power magnetic torquer panels• Thermistors for thermal monitoring
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UCI Satellite (UCISAT)UCI Satellite (UCISAT)Status:• On-board communications
manufactured & tested• Ground station assembled and
operational• CMOS capturing and storing
images• Power PCB layout on next rev• ADCS and C&DH hardware
undergoing simulations/testingbefore design is finalized
Launch:Seeking launch aboard Dnepr III in late 2008
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UCISAT-1Failure Recovery SystemPresented by Juan Osuna
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Recovery-Oriented Computing
» Murphy’s law: “Whatever can go wrong, will go wrong”
» Software has not evolved to deal with our world: Computers crash, servers go down, data is lost…that is reality.
» Recovery Design Space:Availability = MTTF / (MTTF + MTTR)Decreasing MTTR increases system
availability
» Building systems that recover effectively from failures may be more viable than aiming for systems that never fail.
» Recovery is not immune to failures either!
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UCISAT-1 Failure Recovery Subsystem
» Diagnostics» Diagnostics will check for functionality
of subsystems (sensors, power subsystem, camera etc)
» Crash recovery and firmware crash detection» Watchdog timer resets uC in case of a
firmware lock up » Software crash incidence statistics kept in
microcontroller’s internal EEPROM
» On-orbit firmware updates» Satellite capable of receiving firmware
updates» Firmware update stored temporarily in
external memory
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On-Orbit Firmware Updates
RX/TX
Serial EEPROM
128KB
ApplicationFlash
Section120KB
Boot FlashSection
8KB
Internal EEPROM
4KB
1
1
3
2 4
uCAtmega128
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On-Orbit Firmware Updates
» Status» Successfully able to update
microcontroller firmware via serial port» New firmware loaded using X-modem
protocol (temporary implementation for testing purposes only)
» Testing performed» Simulated power failures/glitches during
firmware download into microcontroller’s internal flash
» Work to be done» Firmware signature/checksum verification» Implement immunity to power
failures/glitches and communication disruptions during firmware upload into external EEPROM
» Implement 2nd line of defense
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UCISAT-1Development Using Programmable Logic DevicesPresented by Tom Wypych
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Programmable Logic Devices
Overview» Programmable logic devices are discrete
components which contain a collection of gate elements
» Gate elements are arranged along network grid lines, and can be dynamically connected to create a user-specified circuit system upon startup at the time of device start up
» Circuit connection map is stored, loaded, and run by way of a system-programmed firmware
Application» Complexity of the logic design is limited only
by the abilities of the programmer» For nearly every design there exists a device
well suited to perform the intended tasks» The most helpful design using PLD capabilities is
the asynchronous parallel event processor
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Programmable Logic Applications
PLDs can be used for three categories of tasks:
1. Ease of Development: A single PLD can be substituted for many individual hardwired logic components. Fewer system components means a simpler hardware design.
2. High Speed Co-processing: A PLD can be used to to interface with simpler microcontrollers to perform intensive and repetitive DSP tasks. This provides an efficient use of resources in restrictive operating environments (such as a CubeSat)
3. Custom End-to-End Device Solutions: PLDs can be used to create custom hardware devices with a minimum usage of microcontroller resources and a minimum of system components
…or all three simultaneously!
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PLD Coding
Entire firmware can be synthesized from logic diagrams
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PLD Coding
» Symbolic coding is easy for beginners, there are limits to complexity from human error
» VHDL or Verilog can be used to tap the abilities of a modern programming language (function calls, element reusability, shared state variables, iterative procedures)
output wire [7:0] C,input wire [7:0] B,input wire [7:0] A,input wire clock
always @(posedge clock)begin C = A + B;end
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PLD Case Examples
» Conventional design techniques requires many devices statically configured at the time of board and back plane design
» This process limits flexibility from a completed design, and can stress the limited resources of a small sat environment
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PLD Case Examples
» Many CubeSat designs employ communications between multiple design subsystems. Using an interfacing back plane can allow for system-to-system communications
» Conventional back planes require extensive arbitration protocols or device interfaces hardwired into the back plane board
» Using a Programmable Logic Device new data interfaces can be dynamically created during development updates
» Dynamic interface reconfiguration allows for errors in hardware design to be corrected in software
Case Example: Back Plane
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» Programmable Logic Devices can be used to implement the design of high bandwidth devices otherwise infeasible to implement with conventional processors because of resource limitations.
» A softmodem is just such an example; modem devices require constant and intensive processing attention infeasible with a simple micro controller
» Using a PLD type device, the entire modem can be implemented using nothing more than the PLD and some analog conversion hardware
PLD Case Examples
Case Example: Softmodem
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PLD Case Examples
» New CPLD based design requires no knowledge of interfacing protocols or modes of operation at the time of hardware design
» Hardware components are consolidated and synthesized within the CPLD (and generally perform better than their discrete counterparts)
» The entire mode of operation of the CPLD can be reprogrammed dynamically in seconds
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Programmable Logic Device Usage
» Many offerings are available in the form of PLDs, CPLDs, and FPGAs from Xilinx and Altera
» Devices can be programmed graphically or using higher level code (Verilog or VHDL)
» From a hardware perspective, most small devices are single chip solutions, minimally requiring only power and data lines to your other devices to operate
» Optionally, interfaces can be added to program the device on the bench, or in-orbit as a slave device to a microcontroller (like Juan’s firmware updates example)
What does it take to use a Programmable Logic Device?
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Advisors: Professors Benjamin Villac, Derek Dunn-Rankin,
and A.K. Hayashi
References / AcknowledgementsReferencesThe Berkeley/Stanford Recovery-Oriented Computing Projecthttp://roc.cs.berkeley.edu/
Procyon AVRlibC-Language Function Library for Atmel AVR Processors Written by Pascal Stanghttp://hubbard.engr.scu.edu/embedded/avr/avrlib/
Open Coreshttp://www.opencores.orgAcknowledgements
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QUESTIONS?