“Why Embedded Die?” - NMI · PCB /SMT manufacturing processes • Large panel size 12 x 18”...
Transcript of “Why Embedded Die?” - NMI · PCB /SMT manufacturing processes • Large panel size 12 x 18”...
© 2016 Microsemi Corporation. Company Proprietary 1
Power Matters.TM
“Why Embedded Die?” Piers Tremlett Microsemi 22/9/16
Power Matters.TM 2 © 2016 Microsemi Corporation. Company Proprietary
This presentation:
• Outlines our journey to make miniaturised SiP modules
• Compares :
– Embedded Die Technology (EDT)
– With Fan Out Wafer Level Packages (FOWLP)
• Why Microsemi developed an embedded die process
Introduction
Deca
Technologies
StJude
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Pacemakers
StJude
Medical
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Doctor Patient
Microsemi’s Radio Communication Module
Now an Internet
of Things device
WiFi
3 metre
range
Microsemi RF
module
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Miniaturization • Patient comfort, aesthetics and wound healing
Wireless Telemetry • Remote monitoring and communication
Low power • 8 – 10 year life on one battery = fewer operations
Lower cost • Needed to increase sales
• Only 1 in 9 patients in emerging markets requiring pacemakers
receive one
These drivers are very similar to mobile phones!
Market Drivers for “Hidden” medical devices
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Access to High Density die packaging
Pacemaker vs mobile phone packaging requirements
• Lower volumes (2000 x smaller, 1M / year)
Off shore subcontractors Don’t want these smaller volumes This limits access to high density packaging eg 2.5D, TSV
Hence Microsemi have created a miniaturised SiP process
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Miniaturising Microsemi’s radio module
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2009 Miniaturisation Concept
Place the die under the SMT components
Could we embed the die in the PCB?
Our target
Size: 9mm x 20mm
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Embedded die packaging from EU SHIFT project
Cross section of a PCB
Early Embedded Die
Embedded die
PCB
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Embedded die Radio Module
The result: • 4.5mm x 5.5mm
Our target
Size: 9mm x 20mm
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Fan Out Wafer Level Package (FOWLP) and
Embedded Die Technology(EDT) compared
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Although single die packages exist (eg GaN Systems)
Microsemi make SiP packages • And SiP also makes a good case study for the virtues of EDT
Existing EDT products
Texas Instruments
TPS82674SIPT
DC/DC step-down power
supply
GaN Systems
GS66506T
650V transistor
Microsemi
ZL70323
RF transceiver
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System in a Package (SiP) as a case study
Images courtesy of TI
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What SiP is good for
Modularising and simplifying complex products • eg mobile phones, pacemakers
Physical shape is important • Track length / impedance (RF/ high speed digital)
• Miniaturisation
• Power
When you opt for a SiP • Smaller
• BOM component count reduction
• It’s a functional, tested, working block
• Less design support/ easier customer implementation
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What package format for a SiP?
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Any package can be used if space requirements are low • From PCB with pins
• To BGA packages
Where space is a premium • Fan Out Wafer Level Package
• Embedded die
What package format for a SiP?
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Uses Semiconductor & Packaging processes: • Wafer carrier
• Uses moulding compound
• RDL with tracks >2um
• Made with a mask aligner and mask
Additional passive SMT components are not common, limited types.
FOWLP
Source: Yole and
Infineon
The Murata GRU
series' copper
plated
terminations are
designed for
copper via
connection
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PCB /SMT manufacturing processes
• Large panel size 12 x 18” or 18” x 24”
• Woven glass re-enforced PCB laminates
• Laser direct imaging (“software” mask)
• Wet etching and plating with
>75um wide tracks (but 15 – 50um thick)
• Optimised for adding SMT components
Embedded die technology
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Large master panels
300 radio modules in one panel
Embedded Die Process
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Positives • High density tracking
• Slim
• Very suited to high tracking density single die and multi die
Areas for consideration • Moulding compound / silicon die interface is a point of stress
• Limited capability for passive components
Many high volumes suppliers
FOWLP Deca Technologies
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Positives • Rugged and reliable
• Capable of more current carrying – thicker tracks
• More adapted to additional SMT components (eg reflowed)
• Easy to provide several layer of die
Areas for consideration • Less track resolution
• Often requires additional processing of the die
– Eg RDL
Suppliers tend to be used to low volume • fast turn around, lower NRE
EDT
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SiP : FOWLP and EDT
System in a
Package
Requirement for
functional circuit
block
FOWLP
Semiconductor
and Packaging
industry processes
Dense tracks / pins
Slim
2D only (except PoP)
eg digital?
EDT
PCB and SMT
industry processes
Reflowable SMT components
Higher reliability spec.’s
Higher current / thermals
eg analogue?
RF and power?
Deca
Technologies
Covergence
Eg LDI, large
panels
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EDT suppliers
Competencies:
- Functional test
- Die placement
- SMT
PCB industry
Embedded die
COB / SMT
industry
Convergence
Competencies:
- Substrate manufacturing
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The design flexibility of EDT
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Embedded Die Offers Design Flexibility
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Design Flexibility: - Layering
Heat sinking • to solderable Cu pad
Short interconnect • Low parasitics>low inductance
• Favours: power packages, RF
Miniaturisation
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No Fixed Tooling
Odd shapes and sizes
• 250mm embedded sensor ring
Any package foot print • Also top components
Low NRE – no fixed tooling eg moulds • Lower costs at lower volumes
Fast turnarounds
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Heterogeneous Component Mix
Any termination • SMT
• Edge connectors
• Soldered wires
Any components • Microelectronics
• SMT
• Through hole
From: • single die packages
• many die
• to System in a Package 3 x 3 die
package
Wire bonded embedded die
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summary
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• Low costs at lower volumes, fast turnaround
• Great design flexibility
– Miniaturisation
– Any size and any shape
– Single die to System in a Package
• Rugged and reliable
• Tends to suit:
– lower track density
– lower pin counts
– analogue circuits eg RF, power
Embedded die offers
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Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
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Thank You Piers Tremlett
Microsemi