5820 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013

Analysis of Bandwidth–Unit-Vector-DistortionTradeoff in PLL During Abnormal Grid Conditions

Abhijit Kulkarni, Student Member, IEEE, and Vinod John, Senior Member, IEEE

Abstract—Phase-locked loops (PLLs) are necessary in applica-tions which require grid synchronization. Presence of unbalanceor harmonics in the grid voltage creates errors in the estimatedfrequency and angle of a PLL. The error in estimated angle hasthe effect of distorting the unit vectors generated by the PLL.In this paper, analytical expressions are derived which determinethe error in the phase angle estimated by a PLL when thereis unbalance and harmonics in the grid voltage. By using thederived expressions, the total harmonic distortion (THD) and thefundamental phase error of the unit vectors can be determinedfor a given PLL topology and a given level of unbalance anddistortion in the grid voltage. The accuracy of the results obtainedfrom the analytical expressions is validated with the simulationand experimental results for synchronous reference frame PLL(SRF-PLL). Based on these expressions, a new tuning method forthe SRF-PLL is proposed which quantifies the tradeoff betweenthe unit vector THD and the bandwidth of the SRF-PLL. Usingthis method, the exact value of the bandwidth of the SRF-PLLcan be obtained for a given worst case grid voltage unbalanceand distortion to have an acceptable level of unit vector THD. Thetuning method for SRF-PLL is also validated experimentally.

Index Terms—Converters, harmonic distortion, phase-lockedloops (PLLs).

I. INTRODUCTION

PHASE-LOCKED loops (PLLs) are invariably required ingrid-connected power converters as in distributed genera-

tion systems, active power filters, unity power factor rectifiers,etc. Different PLL topologies are proposed for single-phase[1]–[3] and three-phase systems [4]–[14]. The abnormalities ingrid voltage such as unbalance and harmonics will create errorsin the estimated frequency and phase angle of the PLL [15],[16]. These errors are manifested as distortions in unit vectors.

Many new PLL topologies are proposed to have better per-formance in the presence of unbalance and harmonics in thegrid voltage.

PLL structures with loop filters [4]–[6] are considered to at-tenuate or eliminate selected harmonics and negative sequencecomponents. In [7] and [8], prefilters that are placed before thestationary to synchronous frame transformation are used whichextract the grid voltage positive sequence fundamental and theninput it to a synchronous reference frame PLL (SRF-PLL)topology. Moving-average-filter-based structures are proposed

Manuscript received June 18, 2012; revised October 10, 2012; acceptedNovember 20, 2012. Date of publication January 4, 2013; date of currentversion June 21, 2013.

The authors are with the Department of Electrical Engineering, IndianInstitute of Science, Bangalore 560012, India (e-mail: abhijitk@ee.iisc.ernet.in;vjohn@ee.iisc.ernet.in).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2012.2236998

in [9] and [10] wherein zero-crossing detection is used to makethe system frequency adaptive. In [11] and [12], PLL structuresbased on enhanced PLLs are explained for better performance.PLL with in-loop lead compensator is proposed in [13].

A feature of most of the high-performance PLLs is thatthey have an equivalent SRF-PLL embedded in them. Thehigh-performance PLLs provide reduced unit vector THD buthave higher complexity and might require a high-end digitalcontroller for implementation. It is known that SRF-PLL canprovide better performance [15], [16] at lower bandwidth. How-ever, the exact tradeoff in the relationship between bandwidthof SRF-PLL and unit vector distortion has not been studied.

In the literature, there has not been an attempt to quantify thelevels of distortions in the unit vectors due to grid voltage unbal-ance and harmonics. Analytical quantification of the unit vectordistortion is important as it gives a performance evaluationparameter to compare various PLLs. In this paper, analyticalexpressions are derived which determine the error in the phaseangle estimated by the PLL, for a given level of unbalance anddistortion in the input grid voltage. By using these expressions,the THD of the unit vectors and the fundamental phase errorcan be easily estimated for a given PLL structure and any giveninput.

Based on the expressions derived for unit vector distortions,a new tuning method for the classical SRF-PLL is proposed inthis paper. From the derived expressions, the unit vector THD isplotted versus the bandwidth of SRF-PLL for a given worst caseinput voltage with unbalance and harmonics. Using this plot,the bandwidth of SRF-PLL can be selected for a certain limitingvalue of the unit vector distortion. Conventionally, the SRF-PLL tuning was done heuristically as indicated in [15] to obtainadequate performance. It must be noted that this proposed newtuning method based on the derived analytical expressions is anovel systematic approach.

Simulations and experiments are performed on SRF-PLL forvarious cases of input voltage with high levels of distortion andunbalance to verify the accuracy of the analytical expressions.The amount of unit vector distortion calculated from the analyt-ical expressions is found to agree with the result obtained fromthe simulation and experiments.

The tuning method for the SRF-PLL is also verified experi-mentally and agrees well with the analytical result.

The overall contributions of this paper can be summarized asfollows.

1) Analytical expressions are derived to compute the unitvector magnitude distortion and fundamental phase errorin a PLL when the input voltage has unbalance andharmonics.

0278-0046/$31.00 © 2013 IEEE

KULKARNI AND JOHN: ANALYSIS OF TRADEOFF IN PLL DURING ABNORMAL GRID CONDITIONS 5821

Fig. 1. Three-phase SRF-PLL structure.

2) Based on the derived analytical expressions, a new tuningmethod for the SRF-PLL is proposed which gives the nu-merical value of the bandwidth of the SRF-PLL requiredto have an acceptable level of unit vector distortion for agiven worst case input voltage.

3) The accuracy of the analytical expressions and the tuningmethod for the SRF-PLL is validated through simulationand experimental results.

The contents of this paper are organized as follows. Section IIgives a review of design of SRF-PLL and the performance ofthe same during unbalance and harmonics in the grid voltage.In Section III, the analytical expressions are derived to calculatethe unit vector magnitude distortion and phase error. Section IVcontains the proposed method of tuning of SRF-PLL based onthe equations derived in Section III. Section V includes thecomparison between the analytically computed results and thesimulation and experimental results to prove the validity ofthe derived expressions and the tuning method for SRF-PLL.Conclusion is given in Section VI.

II. REVIEW OF SRF-PLL

A. Design

SRF-PLL is a popular three-phase PLL topology which givesexcellent performance under ideal grid conditions. The methodused in SRF-PLL essentially involves rotating frame transfor-mation of three-phase voltages, the angle of the transformationbeing synchronized with the grid voltage phase angle. Thetransformation is done in such a way that the resulting d-axisvoltage is zero in steady state. A proportional integral controlleris used to achieve that. Fig. 1 shows the structure of SRF-PLLfrom which the control diagram for its design can be derived.Note that sin θ′ and cos θ′ are defined as the unit vectors ofthe PLL.

Rotating reference frame transformation from stationaryα−β frame is given by

vd + jvq =(vα + jvβ)e−jθ′

(1)

⇒ vd =Vm sin(θ′ − θ) (2)

vq =Vm cos(θ′ − θ) (3)

where vα = −Vm sin(θ) and vβ = Vm cos(θ), with θ = ωt. Forθ′ = θ, vd = 0, and for small (θ′ − θ) it can be assumed thatvd ≈ Vm(θ′ − θ). From Fig. 1 and the equations above, thesmall signal control block diagram for the SRF-PLL is shownin Fig. 2.

Fig. 2. Small-signal control block diagram of the three-phase SRF-PLL.

The design of PI controller is done using symmetric optimummethod [17]. This is because the open loop transfer functionG(s) given hereinafter in (4) has poles at origin. In (4), Ts is thesampling time and K and T are the PI controller parameters asshown in Fig. 2

G(s) = KVm

(1 + sT

sT

)(1

1 + sTs

)1

s. (4)

As per the symmetric optimum method, the PI controllerparameters are derived as in

T =α2BTs (5)

K =1

VmαBTs. (6)

The bandwidth and phase margins are functions of αB and aregiven by

bandwidth =1

αBTS(rad/s) (7)

phase margin = tan−1

[αB − 1/αB

2

]rad. (8)

Larger αB implies lesser bandwidth and higher phase mar-gin. Hence, for larger αB , the SRF-PLL will better attenuatethe effects of unbalance and harmonics, but the response willbe slower [15], [16].

In this paper, the effect of bandwidth of the PLL on theunit vector distortions is analyzed and quantified. This novelanalysis is used to tune the SRF-PLL bandwidth in a systematicmanner for a given worst case input level with unbalance andharmonics.

B. Performance of SRF-PLL When Grid Voltage HasUnbalance and Harmonics

For the case when grid voltage has unbalance alone, due tothe presence of negative sequence component, the output of thedq transformation will have a ripple at twice the fundamentalfrequency. Depending on the PLL bandwidth, this ripple getsattenuated but propagates throughout the loop and causes errorsin estimated frequency and angle θ′. This results in distortionsin the output unit vectors.

The presence of harmonics in the grid voltage also resultsin a sinusoidal ripple in the vd which propagates finally asdistortions in the unit vectors. For example, a positive sequence

5822 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013

Fig. 3. Waveforms of sine unit vector u1 (Ch1, scale: 1 div = 1 p.u.) and theoutput of PI controller Δω (Ch2, scale: 1 div = 2π × 50 rad/s) for fault inphase-b and no harmonics in the grid voltage.

kth harmonic will introduce a dominant ripple at (k − 1)thmultiple of fundamental frequency.

The distortion in the unit vectors can be modeled as bothamplitude and phase errors. The amplitude error is indicated bythe THD of the unit vectors, and the phase error is the errorin terms of phase difference in tracking of the fundamentalpositive sequence of the input voltage. The occurrence of theseis discussed in the following.

The presence of unbalance and harmonics in input voltagecauses a ripple in the estimated frequency and, hence, the angle.Let the estimated angle with distortion be

θ′ = ωt+ f. (9)

f contains all the sinusoidal error terms. For example, in thecase of only the unbalance, f will be a sinusoidal componentwith a frequency of 2ω. The sine unit vector is defined as

u1 = sin(θ′). (10)

Substituting (9) in (10), the following equations canbe written assuming f to be small such that cos(f) ≈ 1and sin(f) ≈ f :

u1 = sin(ωt+ f) ≈ sin(ωt) + cos(ωt)f. (11)

As f contains frequencies such as 2ω and higher, it can bededuced from (11) that the unit vector will have harmonics. Inparticular, if the case is only of unbalance, then f is a sinusoidat 2ω, and this would result in a dominant third harmonic in theunit vector. Also, in this case, there will be an additional termat frequency ω which would slightly change the magnitude offundamental and change the phase of the same with respect tothe positive sequence fundamental. This is the reason for theexistence of fundamental phase error.

Fig. 3 shows the distorted sine unit vector and the output ofthe PI controller in an SRF-PLL for the case with normalizedsinusoidal input (va, vb, and vc) and phase-b voltage reduced tozero to emulate a single line-to-ground fault. The bandwidth ofthe SRF-PLL is 300 Hz.

To derive analytical expression for magnitude distortion, theerror function f is to be determined. Once f is known, all the

frequency components of the unit vector can be evaluated, andhence, its THD can be determined.

III. DERIVATION OF ANALYTICAL EXPRESSIONS

QUANTIFYING UNIT VECTOR DISTORTIONS

Analytical expressions for computing the error function f inthe case of unbalance and in the case of harmonics are derivedin this section. Based on these derivations, it is explained howto compute the THD of the unit vectors. The final part of thissection includes the derivation of fundamental phase error.

A. Magnitude Distortion During Unbalance

Let the given 3− φ voltages be va, vb, and vc which havea known amount of unbalance. The stationary reference frametransformation gives the signals vα and vβ as

vα =2

3

(va −

vb + vc2

), vβ =

1√3(vb − vc). (12)

Let

vα = V1 sin(ωt+ φ1), vβ = V2 sin(ωt+ φ2) (13)

where φ1 and φ2 are defined with respect to va. Note that va,vb, and vc do not contain any harmonics.

Let

θ′ = ωt+ f. (14)

The error function is defined in (15). It is to be noted that, dueto unbalance, f appears as a sinusoid at twice the fundamentalfrequency ω. The aim is to determine the parameters a and φ inthe equation shown hereinafter

f = a sin(2ωt+ φ). (15)

vd is computed by equating the real parts of (1) as

vd = vα cos(θ′) + vβ sin(θ′). (16)

Substituting for vα and vβ from (13) and θ′ from (14), theexpression for vd is obtained as

vd = V1 sin(ωt+ φ1) cos(ωt+ f)

+ V2 sin(ωt+ φ2) sin(ωt+ f). (17)

Expanding (17), vd can be written as

vd =V1

2[sin(2ωt+ φ1) cos(f) + cos(2ωt+ φ1) sin(f)]

+V1

2[sin(φ1) cos(f)− cos(φ1) sin(f)]

+V2

2[cos(φ2) cos(f) + sin(φ2) sin(f)]

− V2

2[cos(2ωt+ φ2) cos(f)− sin(2ωt+ φ2) sin(f)] .

(18)

KULKARNI AND JOHN: ANALYSIS OF TRADEOFF IN PLL DURING ABNORMAL GRID CONDITIONS 5823

The term cos(f) = 1− (f2/2!) + (f4/4!)− · · · is approx-imated to 1, and sin(f) = f − (f3/3!) + (f5/5!)− · · · is ap-proximated to f . This is acceptable because the amplitude ofthe error function f is small and first-order approximation givesquite acceptable results as shown in later sections.

After removing the dc terms and using the approximationsfor cos(f) and sin(f), the ripple in vd at frequency 2ω can beobtained from (18) as

vd2 ≈ V1

2[sin(2ωt+ φ1)− a cos(φ1) sin(2ωt+ φ)]

+V2

2[a sin(φ2) sin(2ωt+ φ)− cos(2ωt+ φ2)] (19)

or

vd2 = ε1 sin(2ωt+ φ1) + ε2 cos(2ωt+ φ2) + ε3 sin(2ωt+ φ)(20)

where

ε1 =V1

2, ε2 = −V2/2

ε3 = a [− cos(φ1)V1/2 + sin(φ2)V2/2] . (21)

The component vd2 is then subtracted from zero and givento the PI controller, and a loop filter for topologies containingloop filter then gets integrated as can be seen from Fig. 2.Thus, there will be net magnitude change and phase shift tothe component given in (20). The output of the integrator is thesame as the error function defined initially. Thus, the knowledgeof the net phase shift and magnitude change that a PLL can giveto the component vd2 can be used to obtain the original errorfunction f .

Let the overall magnitude gain and phase shift be m andx, respectively, at the frequency 2ω. Then, f is obtained byapplying this gain and phase shift to all the terms of (20)

f = m [ε1 sin(2ωt+ φ1 + x) + ε2 cos(2ωt+ φ2 + x)

+ ε3 sin(2ωt+ φ+ x)] . (22)

Equating (22) with (15), the following final expressions canbe obtained:

φ = arctan

[α+ βν

αν − β

]− x

a =m [ε1 cos(φ1 + x)− ε2 sin(φ2 + x)]

cos(φ)−m cos(φ+ x) [− cos(φ1)V1/2 + sin(φ2)V2/2]

(23)

where

α = cos(x) + [ε1 cos(φ1) + ε2 sin(φ2)]m

β = sin(x)

ν =ε1 cos(φ1 + x)− ε2 sin(φ2 + x)

ε1 sin(φ1 + x) + ε2 cos(φ2 + x). (24)

Using (23), (24), and (21), the error function due to unbal-ance in grid voltage can be estimated.

Hence, for a given input unbalance represented by the volt-ages in (13), the value of the distortion in the unit vectorrepresented by a in (23) can be obtained in terms of themagnitude gain m and phase shift x of the PLL, which arefunctions of the PLL bandwidth.

This method applies to any PLL structure provided that itsfrequency response is known. Also, for PLLs with prefilters,instead of three-phase voltage signals, the vα and vβ can bespecified depending on the attenuation to the negative sequencecomponent, and the result can then be evaluated by starting thecomputations from (13).

B. Magnitude Distortion in the Presence of Harmonics

Again, let the angle output of PLL be θ′ defined as

θ′ = ωt+ f. (25)

The error function f is a sinusoidal harmonic term of orderk + 1 or k − 1 depending on whether the kth harmonic ingrid occurs as a negative sequence or as a positive sequence,respectively. The derivation is done assuming that the harmonicsequence is known. This approach is followed here as, usually,the sequence magnitude of the harmonics is known. For exam-ple, during the normal operation, the fifth harmonic in the gridvoltage appears as a negative sequence.

Let kth harmonic occur as positive sequence as given here-inafter

vαk = Vk sin(kωt+ γ), vβk = −Vk cos(kωt+ γ). (26)

Here, γ indicates the zero crossing of the harmonic relative tothe fundamental phase-a voltage va. Normally, its value wouldbe zero or π. The error function is defined as

f = ak sin ((k − 1)ωt+ φk) . (27)

Again, the aim is to determine ak and φk. The ripple invd at the frequency (k − 1)ω is affected by the followingcomponents of the input voltage:

1) the kth harmonic component;2) the positive sequence fundamental.

Let the fundamental positive sequence voltage in α−β station-ary reference frame be defined as

v1+(α) =V1+ sin(ωt+ δ)

v1+(β) = − V1+ cos(ωt+ δ). (28)

The angle δ in (28) is again defined with respect to va.Considering kth harmonic voltage alone and using the defi-

nition for vd from (16) and for θ′ from (25), the first componentof vd can be obtained as

v′d,k−1 =Vk [sin(kωt+ γ) cos(ωt+ f)

− cos(kωt+ γ) sin(ωt+ f)]

=Vk sin ((k − 1)ωt+ γ − f)

≈Vk sin ((k − 1)ωt+ γ)

− [Vkak sin ((k − 1)ωt+ φk)

× cos ((k − 1)ωt+ γ)] . (29)

5824 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013

Similarly, considering the positive sequence fundamentalalone, the second component of vd can be obtained as

vd,k−1 =V1+ [sin(ωt+ δ) cos(ωt+ f)

− cos(ωt+ δ) sin(ωt+ f)]

= −V1+ sin(f − δ)

≈ −V1+ cos(δ)ak sin ((k − 1)ωt+ φk)

+ V1+ sin(δ). (30)

Thus, the net (k − 1)th harmonic in vd using (29) and (30) isgiven hereinafter

vd,k−1 = vd,k−1 + v′d,k−1

= − V1+ cos(δ)ak sin ((k − 1)ωt+ φk)

+ Vk sin ((k − 1)ωt+ γ) . (31)

The dc and the higher frequency terms in v′d,k−1 and vd,k−1 aredropped while substituting in (31) as the frequency of interest isonly (k − 1)ω. Now, let the overall magnitude gain and phaseshift due to subtraction from zero, due to PI controller, loopfilter if any, and the integrator be mk−1 and xk−1, respectively,for the frequency of (k − 1)ω. Then, f is given by

f = mk−1 [−V1+ cos(δ)ak sin ((k − 1)ωt+ φk + xk−1)

+ Vk sin ((k − 1)ωt+ γ + xk−1)] . (32)

Comparing this with (27), the final expressions for the phaseand amplitude of f can be solved to be

φk = arctan

[α− β cot(xk−1 + γ)

β + α cot(xk−1 + γ)

]

ak =Vkmk−1 cos(xk−1 + γ)

cos(φk) +mk−1V1+ cos(δ) cos(φk + xk−1)(33)

where

α =1 +mk−1V1+ cos(δ) cos(xk−1)

β =mk−1V1+ cos(δ) sin(xk−1). (34)

Thus, using (33) and (34), the error function due to positivesequence kth harmonic in grid voltage can be evaluated.

Hence, for a given level of positive sequence harmonics asspecified in (26) and the fundamental positive sequence voltageas specified in (28), ak can be determined which represents thedistortion in unit vector. The resulting value of ak depends onmk−1 and xk−1 which are functions of PLL bandwidth.

If the harmonic occurs as a negative sequence, the sameexpressions can be used by replacing k − 1 with k + 1. Themagnitude and phase changes due to the PLL frequency re-sponse will be different as the negative sequence harmonic willresult in an error function at a frequency of (k + 1)ω.

C. Computation of THD

With θ′ = ωt+ ak sin((k − 1)ωt+ φk), the sine unit vectoris given by

u1 = sin (ωt+ ak sin ((k − 1)ωt+ φk))

≈ sin(ωt) + ak cos(ωt) sin ((k − 1)ωt+ φk)

= sin(ωt) +ak2

sin(kωt+ φk)

+ak2

sin ((k − 2)ωt+ φk) . (35)

From (35), it can be seen that a positive sequence kth harmonicin grid voltage results in (k − 2) and kth harmonics in unitvector, with magnitude given by ak/2. Similarly, a negativesequence kth harmonic in grid voltage results in (k + 2) andkth harmonics in unit vectors. Thus, by making use of theexpressions derived for unbalance and the expressions derivedfor harmonics, the overall THD can be computed using (35)and doing a vector addition if a particular harmonic occurs dueto multiple sources, to determine the net resulting individualharmonic magnitude.

To illustrate the approach, consider the case when the inputhas some unbalance and fifth harmonic occurring as bothpositive and negative sequence. Unbalance results in a domi-nant third harmonic component. The positive sequence of fifthharmonic gives rise to distortions at third and fifth harmonics,whereas the negative sequence of fifth harmonic gives rise todistortions at fifth and seventh harmonics. Thus, the unit vectorwill have distortions at 3ω, 5ω, and 7ω. The net distortionat 3ω will be due to the combined effect from fundamentalunbalance and positive sequence fifth harmonic, while the netdistortion at 5ω will be due to the combined effect from positivesequence and negative sequence fifth harmonic. The net effectcan be calculated by doing a vector sum of the individualsinusoids.

D. Comments on Accuracy of the Expressions

The expressions provide acceptable accuracy for THD as ver-ified by the time-domain simulations and experimental results.However, the following points are to be noted.

1) The expression derived for harmonic case does not con-sider the interaction with the negative sequence funda-mental. This will affect the accuracy only when there is asevere unbalance in fundamental voltage.

2) The interaction between a kth harmonic and another mthharmonic is ignored as it involves the product of twosmall signals.

3) The accuracy becomes higher as the bandwidth of thePLL is reduced. This is because the linear approximationsto sin(f) and cos(f) will be more accurate in that case.

E. Computation of Fundamental Phase Error

It was mentioned in Section II using (11) that fundamen-tal phase error can exist when an additional term appears atfundamental frequency. This term can appear due to unbalanceor due to the presence of third harmonic as a positive sequence.

KULKARNI AND JOHN: ANALYSIS OF TRADEOFF IN PLL DURING ABNORMAL GRID CONDITIONS 5825

Fig. 4. Calculation of phase error ψ due to unbalance and positive sequencethird harmonic.

This is because both unbalance and positive sequence thirdharmonic result in an error function periodic at 2ω which resultsin the extra fundamental component in (11).

For clarity, the following equation is reproduced:

u1 = sin (ωt+ a sin(2ωt+ φ))

≈ sin(ωt) + a cos(ωt) sin(2ωt+ φ)

= sin(ωt) +a

2sin(ωt+ φ)︸ ︷︷ ︸+

a

2sin(3ωt+ φ). (36)

For a given grid unbalance and third harmonic positivesequence, the effective a and φ can be computed using (23) and(33). Then, the phase error ψ can be found out as shown in thevector diagram in Fig. 4 illustrating the first and second termsin (36).

This shows that the PLL can have phase error in trackingthe positive sequence in the presence of unbalance or positivesequence third harmonic. Again, the bandwidth of the PLL willdetermine whether the phase error is excessive or not.

IV. NEW TUNING METHOD FOR SRF-PLL

In the literature, reduction in SRF-PLL bandwidth [15],[16] is suggested to overcome the problems due to unbalanceand harmonics in grid voltage. However, the tradeoff in thereduction in bandwidth to give an acceptable performance hasnot been quantified analytically. Depending on a worst casegrid disturbance in terms of unbalance or harmonics and anacceptable limit on unit vector THD, it is possible to ob-tain a bandwidth of the PLL using the relations derived inSection III. Thus, reduced bandwidth SRF-PLL can be usedwith the complete knowledge of the worst case distortions in theunit vectors. This may be preferable when the PLL implementa-tion along with the main control of the power converter requiresmore resources in the digital controller than is available. Usingreduced bandwidth SRF-PLL is advantageous in such cases asit consumes less resources.

To illustrate this tuning method, four cases of input voltagequality are considered. The values used in these cases are basedon the limit on the voltage unbalance and THD at point ofcommon coupling [18], [19]. They are listed as follows:

1) balanced fundamental but with a 2% THD;2) balanced fundamental but with a 5% THD;3) 5% unbalance in fundamental and 2% THD;4) 5% unbalance in fundamental and 5% THD.

The unbalance was created by giving a sag to 85% in phase-bwhich corresponds to a voltage unbalance factor [20] of closeto 5%. The harmonics were kept in the usual sequence, i.e.,zero sequence for third, negative for fifth, and so on in all the

aforementioned four cases. For the case of 5% THD, the thirdharmonic was set to be 3.6% of the fundamental. The remainingodd harmonics were kept such that

Vn/Vn+2 = (n+ 2)/n (37)

where n is the harmonic order. For the case of 2% THD of theinput voltage, the third harmonic was set to be 1.49%, and theremaining harmonics were scaled as per (37).

For each of the aforementioned cases, the THD was com-puted using the equations derived in Section III. The steps in thecalculation which make use of the analytical expressions, PLLcharacteristics, and the input voltage are outlined as a flowchartin Fig. 5. The method shown in the flowchart is used toevaluate the THD and phase error for a range of PLL bandwidthvalues.

The acceptable limit of unit vector THD was set to 1%. Theplot of bandwidth versus unit vector THD for the four cases isshown in Fig. 6. To obtain the THD-versus-bandwidth plot, theparameter αB which is related to bandwidth by (7) is varied,and for each value of αB , the THD is computed, as indicated inFig. 5. For satisfactory performance in all the aforementionedcases, the bandwidth should be set around 40 Hz.

Tuning with respect to phase error is not required as the phaseerror is usually negligible and, also, the bandwidth chosenfor an acceptable lower THD automatically ensures that thephase error is insignificant. Fig. 7 shows the phase-error-versus-bandwidth plot for the case of fault in phase-b.

A designer can use this method for any other worst casequality in the input voltage using the flowchart in Fig. 5. Usingthe expressions for unit vector distortions, the designer canobtain the plot of unit vector THD versus bandwidth for theworst case input voltage quality that can be expected in an ap-plication. Then, depending on the acceptable level of unit vectorTHD, the bandwidth can be chosen from the bandwidth–THDtradeoff plot. The bandwidth can then be set by designing thePI controller gains as explained in Section II.

The method is not limited to an SRF-PLL. For any other PLLtopology, whose frequency response is known, plots similar tothose in Fig. 6 can be obtained, and a suitable bandwidth can bechosen.

V. SIMULATION AND EXPERIMENTAL RESULTS

Simulation and experiments are performed on the SRF-PLLto validate the following:

1) the accuracy of the derived analytical expressions for theunit vector distortion;

2) the new tuning method for SRF-PLL.The simulation is done in MATLAB Simulink with the inputunbalance and harmonics generated using the sine generationblocks. The fast Fourier transform (FFT) of the outputs iscaptured by the Powergui block of the MATLAB Simulink.

The hardware implementation of the SRF-PLL is done us-ing an Altera EP1C12Q240C8 field-programmable gate array(FPGA) board. The implementation is based on the blockdiagram of the SRF-PLL shown in Fig. 1. The input voltagefor the PLL with unbalance and harmonics is generated within

5826 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013

Fig. 5. Flowchart of the method to compute the unit vector THD and phase error for a given input voltage and for a given PLL bandwidth.

Fig. 6. Bandwidth-versus-unit-vector-THD tradeoff plot used for tuning ofthe SRF-PLL.

the FPGA board itself using sine lookup tables. The output unitvectors from the digital to analog converters are captured inTektronix TDS1002 oscilloscope. The scope is used to obtainthe harmonic spectrum of the unit vectors by running the FFToperation.

A. Verifying the Accuracy of the Analytical Expressions

To verify the accuracy of the unit vector distortion calculatedusing the analytical expressions, the following ten cases of

Fig. 7. Bandwidth-versus-phase-error tradeoff plot of the SRF-PLL wheninput phase-b is faulted.

input voltage are considered. These cases contain high levelsof unbalance and distortion.

1) Cases 1–6 have balanced fundamental. The harmoniccontents are 10% third, 8% fifth, and 5% seventh, occur-ring as follows:a) All negative sequence;b) Negative, negative, positive sequence respectively,c) Negative, positive, positive sequence respectively,d) Negative, positive, negative sequence respectively,

KULKARNI AND JOHN: ANALYSIS OF TRADEOFF IN PLL DURING ABNORMAL GRID CONDITIONS 5827

TABLE ICOMPARISON OF DISTORTION IN THE UNIT VECTORS COMPUTED FROM ANALYSIS, SIMULATION, AND EXPERIMENT FOR THE HIGH LEVELS OF

UNBALANCE AND HARMONICS IN THE GRID VOLTAGE AS INDICATED IN CASES 1–10 FOR AN SRF-PLL WITH A BANDWIDTH OF 300 Hz

e) Positive, positive, negative sequence respectively,f) All positive sequence.

2) Case 7 has 25% sag in phase-c with 10% and 6% fifthand seventh harmonics occurring as negative and positivesequence harmonics, respectively.

3) Case 8 has 50% sag in phase-b with 10% second harmonicoccurring as positive sequence harmonic.

4) Case 9 has 5% unbalance in fundamental with 5% fifthharmonic and 3% seventh harmonic, both as positivesequence.

5) Case 10 has balanced fundamental with 10% second har-monic and 8% fifth harmonic both as negative sequenceand 6% seventh harmonic as positive sequence.

The analytical expressions are used to compute the individualharmonic magnitudes and the overall THD. The SRF-PLLis designed to have a bandwidth of 300 Hz. As mentionedin Section III, the accuracy of the expressions is higher forlower bandwidths. This is because, at the lower bandwidths(< 100 Hz), the PLL attenuates the harmonics well and theassumptions made during the derivations will be more appli-

cable. Thus, it is important to check the accuracy for higherbandwidths, and hence, a high bandwidth of 300 Hz is chosen.

Table I lists the individual harmonic magnitudes. In bothsimulation and experiments, the same set of voltages are givenas input to the SRF-PLL. The magnitudes of the harmonicsobtained in simulation and experiment are also indicated inTable I. It can be observed from the table that the values arein agreement.

Fig. 8 gives a comparison between the THDs computed usingthe analytical expressions and experimental and simulationresults. Again, it can be observed that the error in THD is verysmall. The maximum error between analytical and simulationresults was found to be around 0.8% in unit vector THD, whichoccurred for Case 10.

Fig. 9(a) and (b) shows the sine unit vector and the outputof the PI controller of the SRF-PLL for Cases 3 and 7, re-spectively, to illustrate the distortion in unit vector and errorin frequency estimation.

Ideally, the simulation result will give the most accurateresult as there are no approximations involved in it. Thenonequality of the simulation and experimental results can

5828 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 12, DECEMBER 2013

Fig. 8. Comparison of THD obtained using theoretical, simulation, and ex-perimental results corresponding to high levels of distortion and unbalance inthe input voltage.

Fig. 9. Waveforms of sine unit vector u1 (Ch1, scale: 1 div = 1 p.u.)and the output of PI controller Δω (Ch2, scale: 1 div = 2π × 50 rad/s) for(a) Case 3 and (b) Case 7.

be attributed to the accuracy limitation of the oscilloscope inmeasuring the individual harmonics and the errors arising dueto the quantization of the signals in the FPGA.

B. Verifying the New Tuning Method for SRF-PLL

The new tuning method for SRF-PLL is based on the plotof unit vector THD and the SRF-PLL bandwidth. This plot isobtained by using the analytical expressions derived for a givenworst case level of input voltage. The analytically obtained

Fig. 10. Comparison of analytically and experimentally obtained plots ofunit vector THD versus bandwidth for SRF-PLL. The condition used for thetuning of SRF-PLL bandwidth is when the input voltage has 5% unbalance and2% THD.

Fig. 11. Waveforms of SRF-PLL for a bandwidth of 40 Hz and input voltagewith 5% unbalance and 2% THD. [CH4: enable signal; CH2: ω (scale: 1 div =2π × 50 rad/s); CH3: vd (scale: 1 div = 0.5 V); CH1: sine unit vector u1

(scale: 1 div = 5 V); horizontal scale: 1 div = 10 ms].

plots are shown in Fig. 6 for four cases of possible worst casevoltages.

Fig. 10 shows the comparison between the analytical andexperimental results for the tuning of SRF-PLL. It can beobserved that the THD-versus-bandwidth plots are practicallymatching. The input condition considered for this case has5% unbalance and around 2% THD. The theoretical value ofbandwidth required to have less than 1% THD in the unit vectorwas found to be about 40 Hz as mentioned in Section IV. Fig. 10shows that this is indeed the case in experimental result also.

Fig. 11 shows the unit vector vd and estimated frequencyω of the SRF-PLL for a step change in the input voltageset. The enable signal shown gives a step change to the inputvoltage by adding 5% unbalance and 2% harmonic distortion.The oscillations in vd and the estimated frequency ω can beobserved once the enable signal is made high. The bandwidthof SRF-PLL was kept at 40 Hz, and it can be observed that,even though there is a ripple in the estimated frequency, it issmall such that the unit vector distortion is less than 1%. Thevd can be observed to settle in about 12 ms which is what isexpected for a bandwidth of 40 Hz.

KULKARNI AND JOHN: ANALYSIS OF TRADEOFF IN PLL DURING ABNORMAL GRID CONDITIONS 5829

As the plots obtained are in agreement as shown in Fig. 10,the designers can tune the SRF-PLL by obtaining the unit-vector-THD-versus-bandwidth plot analytically.

VI. CONCLUSION

In this paper, analysis of distortions in unit vectors in a three-phase PLL due to unbalance and harmonics in grid voltage hasbeen presented. The magnitude distortion in terms of THD andthe phase error in tracking the positive sequence fundamentalare quantified. Based on the analytical results, a new tuningmethod for the design of SRF-PLL has been proposed. Thismethod is based on selecting the bandwidth of the SRF-PLL fora given worst case input voltage quality and an acceptable levelof unit vector distortions at that input. The analysis will alsohelp to compare various other PLL topologies in terms of theworst case distortion they can produce corresponding to a giveninput voltage. This paper includes simulation and experimentalresults validating the accuracy of the analytical computationsand the new tuning method for the SRF-PLL.

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Abhijit Kulkarni (S’05) received the B.Tech. degreein electrical and electronics engineering from the Na-tional Institute of Technology Calicut, Calicut, India,in 2009 and the M.E. degree in electrical engineer-ing from the Indian Institute of Science, Bangalore,India, in 2011 where he is currently working towardthe Ph.D. degree in the Department of ElectricalEngineering.

His current research interests include powerelectronics for renewable energy systems, grid-connected power converters, and power quality

issues.

Vinod John (S’92–M’00–SM’09) received theB.Tech. degree in electrical engineering from theIndian Institute of Technology Madras, Chennai,India, the M.S.E.E. degree from the University ofMinnesota, Minneapolis, and the Ph.D. degree fromthe University of Wisconsin, Madison.

He was with GE Global Research, Niskayuna, NY,and Northern Power Systems, VT, working in re-search and development positions. He is currently anAssistant Professor with the Department of ElectricalEngineering, Indian Institute of Science, Bangalore,

India. His primary areas of interests are in power electronics and distributedgeneration, power quality, high-power converters, and motor drives.