Analysis and Design of Analog Integrated Circuits Lecture ... · Variation on a Theme: Enhanced...
Transcript of Analysis and Design of Analog Integrated Circuits Lecture ... · Variation on a Theme: Enhanced...
M.H. Perrott
Analysis and Design of Analog Integrated CircuitsLecture 8
Cascode Techniques
Michael H. PerrottFebruary 15, 2012
Copyright © 2012 by Michael H. PerrottAll rights reserved.
M.H. Perrott
Review of Large Signal Analysis of Current Mirrors
M2M1
I1
Vdd
Vss=0
I2
VTH+ΔV1 VTH+ΔV2
Vds2 > Vdsat2
I2 μnCox
W2L2
12 (VGS2-VTH)2(1+λ2Vds2)
ΔV2
I1 μnCoxW1L1
12 (VGS1-VTH)2(1+λ1Vds1)
ΔV1
=
ΔV1 = ΔV2But, VTH+ΔV1=VTH+ΔV2
I2 W2
L2
(1+λ2Vds2)I1 W1
L1
(1+λ1Vds1) =
Mismatchdue to Vdsdifference
Currentsetting
based ongeometry
Note: for accurate ratio, set L1 = L2
Vds2
I2
Triode
Saturation
Vdsat2
M2 in
M2 in
2
M.H. Perrott
The Issue of Vds Mismatch in Current Mirrors
Issue: Current I2 can vary significantly as a function of the drain voltage of M2- We often want a tightly controlled current set only by I1
and transistor sizes How do we improve the current mirror matching
performance?
M2M1
I1
Vdd
I2
Vds2
I2 W2 (1+λ2Vds2)
I1 W1 (1+λ1Vds1) =
Mismatch
due to Vds
difference
Current
setting
based on
geometry
Note: we are assuming L1 = L2
Vds1
3
M.H. Perrott
Cascoded Current Source
Offers increased output resistance- Reduces small signal dependence of output current on
the output voltage of the current source - From Lecture 6, we derived:
Output resistance boosted by intrinsic gain of M3, gm3ro3
But how do we reduce the influence of large signal Vdsmismatch between M1 and M2?
M1M2
Ibias
Iref
ro1
M3Vbias
Rthd3
M3Vbias
Rthd3
4
M.H. Perrott
Match Vds of Current Mirror Devices With Proper Bias
Key transistor for determining I2 is M1- Why is M2 less important? Above biasing approach provides a much closer
match between Vds1 and Vds4
I2 W1
L1
(1+λ1Vds1)I1 W4
L4
(1+λ4Vds4) =
Mismatchdue to Vdsdifference
Currentsetting
based ongeometryM1
I1
Vdd
Vss=0
I2
VTH+ΔV
W/L
W/L
M2
VTH+ΔV VTH+ΔV
VTH+ΔV
W/L
W/LM4
M3Vds2 > ΔV
Vds1 = VTH+ΔV
Vo
Recall:
I2 =W1
W4
1 + λVds11 + λVds4
I1 ≈W1
W4I1
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M.H. Perrott
The Drawback of Basic Cascode Bias Approach
Output voltage range is reduced- Now Vo must be > VTH + 2V- What will happen to the output impedance of the current
source if the output voltage is too low?- Can we improve the voltage range?
I2
V1
M1 and M2in saturation
M1 and M2in triode
M1
I1
Vdd
Vss=0
I2
VTH+ΔV
W/L
W/L
M2
VTH+ΔV VTH+ΔV
VTH+ΔV
W/L
W/LM4
M3Vds2 > ΔV
Vds1 = VTH+ΔVVTH+2ΔV
M1 in saturationM2 in triode
Vo
Vo
calculation of V1 is nontrivial
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M.H. Perrott
Improved Swing Cascode
Key idea: set size of M3 such that Vds1 = V- Assuming strong inversion for M1 and M3:
M1 and M2in saturation
Vo
no wasted voltage region
I2
Vdsat1+Vdsat2
M1 and M2in triode
M6
I1
Vdd
Vss=0 VTH+ΔV
αW/L
W/L
M5
VTH+2ΔV VTH+ΔV
VTH+ΔV
W/L
W/L
M4
M3
M1
I2
M2
VTH+ΔV
VTH+ΔV
W/L
W/L
Vds2 > ΔV
Vds1 = ΔV
Vo
2VTH+3ΔV
VTH+2ΔV
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M.H. Perrott
Alternative Implementation of Improved Swing Cascode
Set as on previous slide Note: both implementations share a common problem
M1
I1
Vdd
Vss=0
I2
VTH+ΔV
αW/L
W/L
M2
VTH+2ΔV VTH+ΔV
VTH+ΔV
W/L
W/LM4
M3Vds2 > ΔV
Vds1 = ΔV
Vo
M5 M6 M7Wp/LpWp/LpWp/Lp
I1I1
M1 and M2in saturation
Vo
no wasted voltage region
I2
M1 and M2in triode
2ΔV
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M.H. Perrott
The Issue of Current Mismatch
The improved swing approach causes a systematic mismatch between I2 and I1- Key issue: Vds1 Vds4
Can we fix this problem?
M1
I2
W/L
M2VTH+2ΔV
VTH+ΔV
M4Vds1 = ΔV
I1
Vds4 = VTH+ΔV
I2 W2 (1+λ2Vds2)I1 W1 (1+λ1Vds1)
=
Mismatchdue to Vdsdifference
W/L
Recall:
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M.H. Perrott
Techniques to Reduce Current Mismatch
Systematic mismatch between I1 and I2 is greatly reduced by using the above circuit (now Vds1 ≈ Vds4)- Note that gate bias on M2 and M3 may be provided by
previously discussed circuits Additional techniques for accurately matching I1 and I2- Set L1 = L4 >> Lmin
Note: set L2 = L3 ≈ Lmin for lower area and capacitance- Set W2/W3 = I2/I1 so that V2 = V3
M1
I2
W/L
M2VTH+2ΔV
VTH+ΔV
M4Vds1 = ΔV
I1
Vds4 = ΔVW/L
M3
VTH+ΔV
W/LW/L
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M.H. Perrott
Another Common Cascode Bias Topology
Key issue: needs two bias current branches
M1
I2
W/L
M2
VTH+2ΔV
VTH+ΔV
M4Vds1 = ΔVVds4 = ΔV
W/L
M3
VTH+ΔV
W/LW/LI1
Vdd
W/LM8
M5 M6 M7Wp/LpWp/LpWp/Lp
I1I1
W/L
W/L
W/L
W/L
W/L
M9
M10
M11
M12
M13
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M.H. Perrott
Utilizing a Simple Resistor to Achieve One Bias Branch
Issue: poly resistor is large and won’t track NMOS devices across temperature and process variations
M1
I2
W/L
M2
VTH+2ΔV
VTH+ΔV
M4Vds1 = ΔVVds4 = ΔV
W/L
M3
VTH+ΔV
W/LW/LI1
M5 M7Wp/LpWp/Lp
I1
RBΔV
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M.H. Perrott
Better Approach: Use PMOS Device In Triode Region
Much smaller, better tracking with NMOS devices than resistor
M1
I2
W/L
M2
VTH+2ΔV
VTH+ΔV
M4Vds1 = ΔVVds4 = ΔV
W/L
M3
VTH+ΔV
W/LW/LI1
M5 M7Wp/LpWp/Lp
I1
ΔVM6
Wp/Lp
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M.H. Perrott
Wilson Current Mirror
Relies on feedback in its operation Using Hybrid- analysis
- Output resistance comparable to cascode current source This circuit is rarely used these days
I1
M1
I2
M2
M3
Rthd2
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M.H. Perrott
Enhanced Cascode Current Source
Offers output resistance comparable to double cascode current source
As with Wilson mirror, analysis is tricky due to source/gate coupling- Using results shown in the following slide:
M4
M3
M1M2
Ibias IrefIbias2
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M.H. Perrott
Thevenin Resistances for CMOS Transistor Feedback Pair
RC
RB
-gmb4vs4vgs4
vs4
ro4gm4vgs4
RC
M4
M3
RA
RB
Rthd
Rths
Rthd
-gmb3vs3vgs3ro3 gm3vgs3
RA
vs3=0
Rths
M4
M3
S
D
S
D
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M.H. Perrott
Basic Cascode Amplifier
Allows improved frequency response (discussed later) Reduction to two-port will be done in several steps
Vout
RD
RG
Vin RS
Rthg1
RG
vin Av1vg1vg1
is1
RS
Rths1
Rthd11is1α
g1
s1
d1
M1
M2
M1
is2Rths2
Rthd2vout2is2α
s2
d2
M2
RD
Common Gate
General Model
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M.H. Perrott
Eliminate Middle Sections
Calculation of Gm1 same as for common source amp To reduce further, note that
Vout
RD
RG
Vin RS
Rthg1
RG
vin vg1 Rthd1m1vg1G
g1 d1
M1
M2
M1
is2Rths2
Rthd2vout2is2α
s2
d2
M2
RD
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M.H. Perrott
Resulting Two-Port Similar to Common Source Amp
Key difference: drain impedance much larger
Vout
RD
RG
Vin RS
Rthg1
RG
vin vg1
m1vg1G
g1
M1
M2
M1
Rthd2vout
d2
M2
RD
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M.H. Perrott
Slight Twist to Cascode Amplifier
What is the difference between this amplifier and basic cascode amplifier?
What are the constraints in setting Vbias? What is the maximum output voltage swing?
M2
M1
M3
Ibias
Vin
Vdd
Vss=0
iin
is1
is1
Vbias
M4
Iin
RL
Vout
ro4
gm1+gmb1
1
ro2
ro1
RL Vout
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M.H. Perrott
Constraints on Vbias and Output Range
To keep M2 and M4 in saturation
To keep M1 in saturation
VTH+ΔV1
>ΔV2
M2
M1
M3
Ibias
Vin
Vdd
Vss=0
Vbias
M4
Iin
RL
Vout
>ΔV4
>ΔV1
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M.H. Perrott
Calculation of Maximum Output Range
Minimum Vbias allows the maximum output range
Resulting output range
VTH+ΔV1
>ΔV2
M2
M1
M3
Ibias
Vin
Vdd
Vss=0
Vbias
M4
Iin
RL
Vout
>ΔV4
>ΔV1
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M.H. Perrott
Variation on a Theme: Enhanced Cascode Amplifiers
We can turn the enhanced cascode current source into an amplifier- Inject a current input at the source of M4
Key aspects of small signal analysis can be done using Thevenin method- Simply leverage Thevenin resistance formulas shown on
Slide 16
Vout
R1
RsM1
M4
Ibias2
M3
M2
Ibias1
Iin
Input Source
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M.H. Perrott
Small-Signal Analysis of Enhanced Cascode Amp
From Thevenin resistance calculations on Slide 16:- Input impedance is quite low
- Output impedance is probably determined by R1
This amplifier is useful for extracting a current signal while keeping the source voltage nearly constant
Vout
R1
RsM1
M4
Ibias2
M3
M2
Ibias1
Iin
Input Source
Vout
R1
Rs
M4
M3
Iin
Input Source
gm2
1 Rthd1Rin
Rout
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