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Why ADC?

The IEEE 802.11a standard is the wire less local area standard for the tomorrow highdemanding communication world.

Battery life the device is major problem for todays.

Every one wants to avoid the frequent recharging of the battery of the device. As a result, power consumption of the device has to low while maintaining the adequate

performance of the device.

Analog to Digital converters are the major power consumers (almost 25%) of the any device.

So in designing we have to main concentrate on ADC.


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IEEE 802.11a 802.11 Specifications are developed specifically for Wireless Local Area Networks.

802.11a operates in the 5 - 6 GHz range with data rates commonly in the 6 Mbps, 12 Mbps, or 24Mbps range.

802.11a uses the orthogonal frequency division multiplexing (OFDM) standard.

Data transfer rates can be as high as 54 Mbps.

802.11a specification is also known as Wi-Fi5.


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Aim In any wireless application, power consumption of the device is as important as its performance.

A typical transceiver chip for the 802.11a standard consumed about 800mW.

IN that nearly 25% is taken by the ADCs.

2 types 1.Pipelined ADC (less power consumption)2.Interpolating and averaging ADC (high power and fast conversation rate).

The IEEE 802.11a standard, the ADCs usually require 8-10 bits of resolution while running at40MHz

I am going to implement the 8bit interpolating ADC with 180nm technology, with less powerconsumption.


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Interpolating and Averaging ADC

Based on the architecture of the flash ADC

It uses the techniques Pre-Amplifying,Interpolating, Folding and Averaging.

Lower input capacitance is seen by the inputsignal.

Main parts 1. Sample and Hold Amplifier

2. Preamplifier

3. Interpolation Network

/Averaging Network

5. Comparator

6. Priority Encoder

Block diagram of a 3-bit interpolating ADC.


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Basic Idea

The sampled analog voltage will go to thenumber of pre-amplifying stages before thecomparison actually takes place.

In between the pre-amplifying stages beforethe comparison and digitalization actuallytakes place.

Averaging at the output of the interpolationnetwork with the passive elements canimprove the accuracy of the digitization.


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8-Bit Interpolating ADC


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Sample and Hold Circuit

Sample and hold circuits are critical in convertingthe analog voltage into the digital signals.

Behavior is analogous to the camera.

The function is like take the picture of the analogsignal and the hold its value until its value

Ignoring this component will result into seriouserrors in speed and accuracy.

Operating ModesSample Mode

Hold Mode

Aperture error

Sample and Hold Circuit and its output


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Design Constraints

VDD=1.8V

VSS=0

VIN =0V-1.8V

W/L=10-20

Frequency=5M

CLOCK

High=1.8V

Low=0

Sample time < Hold Time period

Time Period 50% Period of the input Signal


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Simulations


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Sample and Hold circuit input and ouput


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Two Stage Open Loop Comparator

The symbol and the characteristics areidentical to that of the high gain operationalamplifier.

VOUT = High When (VP - VN) = High= Low When (VP - VN) = Low

Difference is the, no need of the stabilityfor the comparator

It contains two parts differential opamp andthe current source inverter

The resolution of the comparator is defined asVin(min) = VOH-VOL


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Two Stage Open Loop Comparator Initial Conditions

Conditions initial state of V01 initial state of VoutVg1 > Vg2, i1 < Iss and i2 > 0 Vdd-Vds4(sat) < V01 < Vdd VssVg1 > > Vg2, i1 = Iss and i2 = 0 Vdd VssVg1 < Vg2, i1 > 0 and i2 < Iss Vs2 < V01 Vs2 + Vds2(sat) Eq-2 for PMOSVg1 < Vg1, i1 > 0 and i2 < Iss Vs2(Iss/2) < V01 < Vs2(Iss/2) + Vds2(sat) Eq-2 for PMOSVg2 > > Vg1, i1 = 0 and i2 = Iss Vss Eq-2 for PMOSVg2 < Vg1, i1 < Iss and i2 > 0 Vdd Vds4(sat) < Vo1 < Vdd VssVg2 < < vg1, i1 = Iss and i2 = 0 Vdd Vss 1

Vout(min) = (VDD-VT1) {1-[1-(2/1)((Vsg2-|Vth2|)/VDD-VT1)2]1/2} Eq-2


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Design of a Two Stage open loop Comparator

Design constraints for the Two Stage Open Loop Comparator, for a Linear Response------------------------------------------------------------------------------------------------------------------

Specifications: tp, CH, Vin(min), VOH, VOL, V+ICM, V-ICM, and the overdrive

Constrains: Technology, VDD, and VSS---------------------------------------------------------------------------------------------------------------------------------------|P1| = |P11| = 1/tpmk and I7 = I6 = |P11| C11 / (N+P) Choose m=1

W6/l6 = 2 I6 / (Kp(VDS6 (sat)) 2 and VSD6(sat) = VDD-VOH

W7/L7 = 2 I7 / (Kn(VDS7(sat))2 VSD7 (sat) = VOL-VSS

Guess C1 as 0.1 to 0.5 pF I5 = I7 2C1/C11 A result of choosing M1=1

W3/L3 = W4/L4 = I5/Kp(VSG3 - |VTH|)2 VSG3 = VDD- V+ICM + VTN

Gm1 = AV(0)(gds2 + gds4)(gds6 + gds7)/gm6 gm6 = (2Kpw6I6)/L6

W1/L1 = W2/L2 = gm12/K5I5 Av(0) = VOH + VOL/Vin(min)

Fine C1 and check assumptionC1 = CGD2 + CGD4 + CGS6 + CBD2 + CBD4

If C1 value is grater than the guess in step3,then increase the value of C1 and repeat steps 4 to 6

VDS5(sat) = V-ICM VGS1 VSS If VDS5(sat) is less than 100mv,increase W1/L1

__________________________________________________________________________________


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Design Constraints

VDD = 1.8V VSS = 0V Tp = 50ns Vin(min) = 1mv VOH = 1.67V VOL = 400n ICMR = 9.1-1.1V


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SimulationsOutput @High


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Output @Low


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DC Response of the Comparator


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Two Stage Opamp

Most important building block in the analog design.

The amplifiers that have sufficiently high forwardgain so that when negative feedback is applied

Symbol is like same as that of that of thecomparator.

Two TypesUn-Buffered( High output Resistance )

Buffered( Low Output Resistance )

Primary Requirement is to have an open loop gainsufficiently large when the negative feedback

applied.

It introduces a concept of compensation to getstability when the negative feedback is applied.


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Boundary Conditions and the Requirements

Boundary Conditions:

Process specification (VT, K, COX, etc)Supply voltage and rangeSupply current and rangeOperating temperature and range

Constraints:GainGain BandwidthSettling timeSlew rateInput common mode range, ICMRPower supply rejection ratio, PSRROutput Voltage swing

Output resistanceOffsetNoiseLayout Area.


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Design Procedure Of The Two Stage Opamp

SR = 10 V/usec

Av = 5000 V/V

GB = 5 MHz

CL = 100 fF

Pdiss < 0.3 mWatt

ICMR+ = 1.5 Volt ICMR- = 0.2 Volt

Design consideration:

I consider that

10uA current flows through 1st stage

20uA current flows through the next stage

TECHNOLOGY USED: 180nm technology


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Simulations


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Open Loop Frequency Response


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Priority Encoder


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Outputs


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8Bit Priority Encoder


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Thank Q

Analog to Digital Converter in Wireless Local Area Network

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