Analog to Digital Conversion - CppSimM.H. Perrott Analog to Digital Conversion Analog input is...
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M.H. Perrott Analysis and Design of Analog Integrated Circuits Lecture 23 Analog to Digital Conversion Michael H. Perrott April 25, 2012 Copyright © 2012 by Michael H. Perrott All rights reserved.
Transcript of Analog to Digital Conversion - CppSimM.H. Perrott Analog to Digital Conversion Analog input is...
M.H. Perrott
Analysis and Design of Analog Integrated CircuitsLecture 23
Analog to Digital Conversion
Michael H. PerrottApril 25, 2012
Copyright © 2012 by Michael H. PerrottAll rights reserved.
M.H. Perrott
Outline of Lecture
ADC Topologies- Flash- SAR- Pipeline- Interleaved- Sigma-Delta
Special focus on the emerging area of VCO-based ADCs
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M.H. Perrott
Analog to Digital Conversion
Analog input is typically voltage Digital output consists of bits, Dk, with values 0 or 1 Key characteristics similar to DAC
- Full scale = Vref- Resolution = Vref/2N = 1 LSB- Nonlinearity measured with INL, DNL, Monotonicity
3
D0
Vin ADCD1
DN-1
Vref18 Vref
78
000001
111D2D1D0
1 LSB
Vin
0
M.H. Perrott
Flash ADC
Fastest ADC structure (> 1 GHz)- Performs direct comparison of an input signal to a set of
voltage references using parallel comparators- Typically limited to 8-bit resolution- Relatively large area and power for higher resolution 4
A
A
IN
A
CLK
VrefN
1
1
0
Pre-Amp Comparator
N-StageResistorLadder
M.H. Perrott
SAR ADC
Leverages a DAC to sequentially compare its output values to the input voltage- Minimal analog complexity - requires only one
comparator and a capacitor DAC- Successive Approximation Algorithm (SAR) is efficient
comparison algorithm for comparing DAC to input value- Has recently become very attractive in advanced CMOS
for modest resolution (i.e., 8 to 10 bits) applications 5
VdacC
Vref
D0D1D2
C2C4C Φ0
DN-2DN-1
2N-1C 2N-2C
Vin CLKVin CLK
D0 VdacDAC
D1
DN-1
M.H. Perrott
SAR Algorithm
We can efficiently compare the DAC output to the input voltage, Vin, by successively subdividing the range from MSB to LSB- Number of comparisons ≈ number of bits
Example: 10-bit SAR ADC requires roughly 10 comparisons per sample
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Vref
Vin
GndD5=0 D4=1 D3=1 D2=0 D1=0 D0=0
M.H. Perrott
Pipeline ADC
Resolves ADC bits in several stages- Earlier stages resolve MSB bits- Calculate residue for later stages through subtraction of
MSB estimate Amplify residue so that all stages operate over similar
voltage ranges Pipeline trends
- 1-bit per stage in the past; now going to multi-bit per stage- For advanced CMOS, interleaved SAR architectures are
starting to look more attractive than pipelines7
CLK
D0 Vdac1DAC
DJ-1
Vin
ADC
K
D0 Vdac2DAC
DJ-1
Vresidue1
ADC
KVresidue2
M.H. Perrott
Vin
D0
ADCD1
DN-1
D0
ADCD1
DN-1
D0
ADCD1
DN-1
D0
ADCD1
DN-1
CLK4
CLK2
CLK1
CLK3
CLK4
CLK2
CLK1
CLK3
Interleaved ADC
Clocking several ADC structures at different clock phases allows much higher effective sample rate- Can interleave Flash, SAR, or
Pipeline ADCs Key challenges include clock
skew, mismatch between ADCs, higher input capacitance
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Sigma-Delta ADC (Discrete-Time)
Oversampled input- Clock rate is much higher than bandwidth of input
signal Noise shaped quantization noise
- Uses similar concepts as Sigma-Delta DAC considered in Lecture 22 Leads to high effective precision despite having a coarse
quantizer9
DAC
H(z)IN OUT
Multi-LevelQuantizer
clock
M.H. Perrott
Sigma-Delta ADC (Continuous-Time)
Similar to Discrete-Time, but important differences- Sampler occurs after the filtering
Allows removal of high frequency noise before sampling- Only the quantizer and DAC need to settle during each
sample Allows higher speed
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DAC
H(s)
clock
IN OUT
Multi-LevelQuantizer
M.H. Perrott
Time-to-Digital Conversion
Time
-to-
Digital
clk(t)
tin(t)
Reg
D Q
Delay
Reg
D Q
Reg
D Q
Delay Delay
clk(t)
e[k]
tin(t)
clk(t)
tin(t)
e[k]
1
1
1
0
0
Delay TDC
Characteristic
ΔtΔt
e[k]
e[k]
Quantization in time achieved with purely digital gates- Easy implementation, resolution improving with Moore’s law
How can we leverage this for quantizing an analog voltage?11
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Adding Voltage-to-Time Conversion
Analog voltage is converted into edge times- Time-to-digital converter then turns the edge times into
digitized values Key issues
- Non-uniform sampling- Noise, nonlinearity
Naraghi, Courcy, Flynn, ISSCC 2009 clk(t)
Time
-to-
Digital
out[k]Voltage
-to-
Time
tin(t)in(t)
Is there a simple implementation forthe Voltage-to-Time Converter?
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A Highly Digital ADC Implementation
A voltage-controlled ring oscillator offers a simple voltage-to-time structure- Non-uniform sampling is still an issue
We can further simplify this implementation and lower the impact of non-uniform sampling
clk(t)
Time
-to-
Digital
out[k]Voltage
-to-
Time
tin(t)in(t)
Ring Oscillator
Vtune(t)tin(t)
Reg
D Q
Delay
Reg
D Q
Reg
D Q
Delay Delay
clk(t)
out[k]
tin(t)in(t)
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Making Use of the Ring Oscillator Delay Cells
Utilize all ring oscillator outputs and remove TDC delays- Simpler implementation
TDC output now samples/quantizes phase state of oscillator
Ring Oscillator
Vtune(t)tin(t)
Reg
D Q
Delay
Reg
D Q
Reg
D Q
Delay Delay
clk(t)
out[k]
tin(t)in(t)
Ring Oscillator
Vtune(t)
Reg
D Q
Reg
D Q
Reg
D Q
clk(t)
out[k]
in(t)
tin1(t)
tin2(t)
tin3(t)
tin1(t) tin2(t) tin3(t)
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Improving Non-Uniform Sampling Behavior
Oscillator edges correspond to a sample window of the input Sampling the oscillator phase state yields sample windows
that are much more closely aligned to the TDC clk
Ring Oscillator
Vtune(t)tin(t)
Reg
D Q
Delay
Reg
D Q
Reg
D Q
Delay Delay
clk(t)
out[k]
tin(t)in(t)
Ring Oscillator
Vtune(t)
Reg
D Q
Reg
D Q
Reg
D Q
clk(t)
out[k]
in(t)
tin1(t)
tin2(t)
tin3(t)
tin1(t) tin2(t) tin3(t)
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N-Stage Ring OscillatorVtune
Ref N-bit Register
N-bit Register
N XOR Gates
Adder
Out
N-Stage Ring OscillatorVtune
Sample 1
Sample 2
Sample 4
Sample 3
Multi-Phase Ring Oscillator Based Quantizer
Adjustment of Vtune changes how many delay cells are visited by edges per Ref clock period- Quantizer output corresponds to the number of delay cells
that experience a transition in a given Ref clock period16
M.H. Perrott
More Details …
Choose large enough number of stages, N, such that transitions never cycle through a given stage more than once per Ref clock period- Assume a high Ref clock frequency (i.e., 1 GHz)
XOR operation on current and previous samples provides transition count
N-Stage Ring OscillatorVtune
Ref N-bit Register
N-bit Register
N XOR Gates
Adder
Out
101010101
010110101
111100000
Out = 4
010110101
110101010
100011111
Out = 6
101010010
011111000
110101010
Out = 5
Ref
9-Stage Ring Oscillator ValuesExample: Progression of
Vtune
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M.H. Perrott
N-Stage Ring OscillatorVtune
Ref N-bit Register
N-bit Register
N XOR Gates
Adder
Out Quantized
VCO Frequency
Quantized
VCO Phase
First Order
Difference
Sampler
VCO
1- z-1
Quantizer
First Order
Difference
Ref
Vtune Out
T
100011111
Out = 6
011111000
Out = 5
A First Step Toward Modeling
VCO provides quantization, register provides sampling- Model as separate blocks for convenience
XOR operation on current and previous samples corresponds to a first order difference operation- Extracts VCO frequency from the sampled VCO phase signal
Wismar, Wisland,Andreani, ESSCIRC 2006
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M.H. Perrott
VCO
1- z-1
Quantizer
First Order
Difference
Ref
Vtune Out
2πKv
s1- z-1
T
1
T
Vtune Out
VCO Sampler
VCO
Noise
Quantization
Noise
First Order
Difference
ff
-20 dB/dec
Output
Noise
f
20 dB/dec
VCO Kv
Nonlinearity
Corresponding Frequency Domain Model
VCO modeled as integrator and Kv nonlinearity
Sampling of VCO phase modeled as scale factor of 1/T
Quantizer modeled as addition of quantization noise
Key non-idealities:- VCO Kv nonlinearity- VCO noise- Quantization noise
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Example Design Point for Illustration
105 106 107 108-100
-80
-60
-40
-20
0
20
40
60
Frequency (Hz)
Am
plitu
de (d
B)
Simulated ADC Output Spectrum
2πKv
s1- z-1
1
T
Vtune Out
VCO Sampler
VCO
Noise
Quantization
Noise
First Order
Difference
ff
-20 dB/dec
Output
Noise
f
20 dB/dec
VCO Kv
Nonlinearity
Ref clk: 1/T = 1 GHz 31 stage ring oscillator
- Nominal delay per stage: 65 ps
KVCO = 500 MHz/V- 5% linearity
VCO noise: -100 dBc/Hz at 10 MHz offset
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SNR/SNDR Calculations with 20 MHz Bandwidth
105 106 107 108-100
-80
-60
-40
-20
0
20
40
60
Frequency (Hz)
Am
plitu
de (d
B)
Simulated ADC Output Spectrum
2πKv
s1- z-1
1
T
Vtune Out
VCO Sampler
VCO
Noise
Quantization
Noise
First Order
Difference
ff
-20 dB/dec
Output
Noise
f
20 dB/dec
VCO Kv
Nonlinearity
Conditions SNDR
Ideal 68.2 dB
VCO Thermal Noise 65.4 dB
VCO Thermal + Nonlinearity 32.2 dB
VCO Kv nonlinearity isthe key performance
bottleneck21
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Classical Analog Versus VCO-based Quantization
Much more digital implementation Offset and mismatch is not of critical concern Metastability behavior is potentially improved Improved SNR due to quantization noise shaping
A
A
IN
A
CLK
Vdd
N
1
1
0
N-Stage Ring Oscillator
N-bit Register
Pre-Amp Comparator
N-Stage
Resistor
Ladder
IN
CLK
110 01
Buffer
Vdd
Implementation is high speed, low power, low area22
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Key Performance Issues: Nonlinearity and Noise
Very hard to build a simple ring oscillator with linear Kv
Noise floor set by VCO phase noise is typically higher than for analog amplifiers at same power dissipation
N-Stage Ring OscillatorVtune
RefN-bit Register
N-bit Register
N XOR Gates
Adder
Out
Vtune
VCO Noise
Quantization Noise
f
20 dB/dec
VCO Kv Nonlinearity
Out
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VCO-based
Quantizer
Gain and
Filtering
Ref (1 GHz)
DAC
In Out
N-Stage Ring OscillatorVtune
RefN-bit Register
N-bit Register
N XOR Gates
Adder
Out
Vtune
DAC Out
Feedback Is Our Friend
Issue: must achieve a highly linear DAC structure- Otherwise, noise folding and other bad things happen …
Iwata, Sakimura, TCAS II, 1999Naiknaware, Tang, Fiez, TCAS II, 2000
Combining feedback with front end gain acts to suppress impact of quantizer noise and nonlinearity- Scale factor from input to
output is also better controlled- Structure is a continuous-time Sigma-Delta ADC
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VCO-based
Quantizer
Gain and
Filtering
Ref (1 GHz)
DAC
In Out
N-Stage Ring OscillatorVtune
RefN-bit Register
N-bit Register
N XOR Gates
DAC Out
Vtune
DAC Out
1-Bit DACs
A Closer Look at the DAC Implementation
Consider direct connection of the quantizer output to a series of 1-bit DACs- Add the DAC outputs
together
What is so special about doing this?25
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VCO-based
Quantizer
Gain and
Filtering
Ref (1 GHz)
DAC
In Out
N-Stage Ring OscillatorVtune
Vtune
DAC Out
Sample 1
Sample 2
Sample 4
Sample 3
Recall that Ring Oscillator Offers Implicit Barrel Shifting
Barrel shifting through delay elements- Mismatch between
delay elements is first order shaped
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VCO-based
Quantizer
Gain and
Filtering
Ref (1 GHz)
DAC
In Out
N-Stage Ring OscillatorVtune
RefN-bit Register
N-bit Register
N XOR Gates
DAC Out
Vtune
DAC Out
1-Bit DACs
111100000 100011111 011111000
Ref
Implicit
Barrel-Shift
DEM
Implicit Barrel Shifting Applied to DAC Elements
Barrel shifting action of quantizer transferred to 1-bit DAC elements
Miller, US Patent (2004)
- Acts to shape DAC mismatch and linearize its behavior27
M.H. Perrott
First Generation Prototype
Second order dynamics achieved with only one op-amp- Op-amp forms one integrator- Idac1 and passive network form the other (lossy) integrator- Minor loop feedback compensates delay through quantizer
Third order noise shaping is achieved!- VCO-based quantizer adds an extra order of noise shaping
DOUT
VIN
973 MHz
IDAC1 IDAC2
Vtune
VA V
B
VCO-based Quantizer & Barrel-Shift
DEM
31
Barrel-Shift
DEM
Qu
an
tize
r E
lem
en
t
Sample
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M.H. Perrott
Custom IC Implementing the Prototype
DOUT
VIN
973 MHz
IDAC1 IDAC2
Vtune
VA V
B
VCO-based Quantizer & Barrel-Shift
DEM
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Straayer, PerrottVLSI 2007
0.13u CMOS Power: 40 mW Active area: 700u X 700u Peak SNDR: 67 dB (20 MHz BW) Efficiency: 0.5 pJ/conv. step
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Measured Spectrum From Prototype
0.1 1 10 100 1000-80
-60
-40
-20
0
20
40
60
Frequency (MHz)
Am
plitu
de (d
B)
Normalized FFT, FIN = 1 MHz
SNR SNDR
20 MHz Input Bandwidth
65.7 dB66.4 dB
Distortion
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M.H. Perrott
Measured SNR/SNDR Vs. Input Amplitude (20 MHz BW)
-90 -80 -70 -60 -50 -40 -30 -20 -10 0-10
0
10
20
30
40
50
60
70
80
90SNR/SNDR vs. Amplitude, FIN = 1 MHz
Amplitude (dBFS)
SNR
/SN
DR
(dB
)
SNRSNDR Kv nonlinearity
limits SNDR to 67 dB
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Summary
ADC design is an active area of research- Many topologies possible- Much innovation is still ongoing, especially as new CMOS
fabrication processes are introduced Key topologies
- Flash- SAR- Pipeline- Sigma-Delta
VCO-based ADCs are a new area of interest- Take advantage of high speed of new CMOS processes- Leverage digital circuits- Can achieve good performance, but innovation still needed
