ANALOG ELECTRONICS

Q. Power diode is generally made froma) Siliconb) Germaniumc) Bothd) None of these

Q. When the both junction of NPN diode is reverse biased, then the diode is in which modea) Activeb) Cutoffc) Saturationd) inverted

Q. Which transistor mode gives the inverted outputa) Common Emitterb) Common Basec) Common Collectord) None of these

Q. Which coupling gives the higher gain in case of amplifiera) Capacitor couplingb) Impedance couplingc) Transformercoupling

Q. Which distortion is least objectionable in audio amplificationa) Phaseb) Frequencyc) Harmonicd) Intermediation

Q. A narrow band amplifier has a band pass nearly…………of central frequencya) 33.3%b) 10%c) 50%

Q. Phase shift oscillator consistsa) RLb) RCc) RLC

Q. Multivibrater Producesa) Sine waveb) Square wavec) Smooth waved) sawtooth

Q. Convert the 101101 Binary number into octal noa) 65b) 55c) 51d) 45

Ans: 55

Q. 10 in BCDa) 10100b) 1100c) 010111d) None of these

Ans: None of these

Q. Which PNP device has a terminal for synchronizing purposea) SCSb) Triacc) Diacd) SUS

Q. Addition of indium in semiconductor crystal makesa) PNPb) NPN

Q. Free electron exists in which banda) 1b) 2c) 3d) Conduction band

Q. Ripple factor of half wave rectifiera) 1.21b) 0.48c) 0.5

Q. Transistor that can be used in enhancement modea) NPNb) UJTc) JFETd) MOSFET

Q. Following contributes to harmonic distortion in Amplifiera) +Ve feedbackb) –Ve feedbackc) Defective active device

Q. High cutoff frequencya) CBb) CCc) CE

Q. Which is used as data selector?a) Encoderb) Decoderc) modulatord) Demodulator

Q. Read write capable memorya) RAMb) ROMc) Bothd) None of these

Q.the radix or base of hexadecimal number system is -----------a) 8b) 16c) 5d) none of these

Ans: 16

Q.the no of 1’s in the binary representation of the expression 162*9+162*7+16*5+3 area) 10b) 23c) 6d) 4

Q. the no of latches in F/F are ------- a) 1b) 2c) 3d) 4

Q.how many flip-flops are required to construct Mod -12 countera) 5b) 4c) 12d) none

Ans: 4

Q. which logic gate has the output is compliment of its input ----------a) ORb) AND

c) NOTd) X-OR

Ans: NOT

Q.no.of 2-input multiplexers needed to construct a 210 input multiplexer…….a) 12b) 31c) 20d) 16

Q.By adding inverters to the inputs and output of a AND gate we can obtain ……………a) ORb) ANDc) NOTd) X-OR

Ans: X-OR

Q.how many NAND gates are needed to realize OR gate --------------a) 1b) 2c) 3d) 4

Ans: 3

Q.which is the first integrated logic family ---------------a) RTLb) DTLc) TTL d) none of these

Q. Which logic gate has output high if and only if all inputs are low ---------?a) NORb) NANDc) X-NORd) AND

Ans: NAND

Q.According to Boolean algebra 1+A+B+C = a) Ab) A+B+C c) 1d) none of these

Ans: 1

Q. If a=0x6db7 and b=0x2ae9 then what is the value of a”b--------------a) binary number for 1001.1101?b) decimal number for 19?c) excess-3 code for 29?

Q.what is the value of A'+1 ?a) Ab) A' c) 1d) none of these

Ans: 1

Q.2 in 4 bit number one bit indicates sign of the number then the locations are froma) -8 to 8b) -7 to 7c) -16 to 16d) None

Q.Avalanche photo diode is used when compared to PIN diode bcza)larger band widthb)high sensitivityC)-------d)--------

Q.some non zero DC voltage is to RC low pass circuit then the DC voltage in the output containsa) Same as in inputb) Higher than inputc) Zerod) Slightly increases

Q.if the output of the gate is always high then the gates applied to this logic are 0,0a) NAND and EX-NORb) NAND and NORc) AND and X-NORd) OR and XOR

Ans:a

Q.Thermal Run away is not possible in FET bcz the flow ofa)minority careers b)Transconductance

c)_____d)none

Ans : minority careers

Q.which of the following is/are true about 1's and 2's compements:i)In 1's complement form. 0 has two representationsii)in 1's complement, the magnitude of lowest number is equal to the magnitude of highest numberiii)In 2's complement, 0 has two representations

a) i only b) i and iic) iii onlyd) all of these

Q.In the hybrid parameter model of a transistor reverse transfer voltage ratio and forward transfer current ratio are respectively given by:a) h11 and h21b) h12 and h11c) h21 and h11d) None of these

Q.The largest negative no can be represented with 8 bits in 2's compliment representation?a)-256b)-255c)-127d)-128

Ans: -128

Q. How many NAND gates required to implement AB+CD+EFa) 1b) 2c) 3d) 4

Ans: 4

Q. Transparent latch is seen in which type of flip flopa) SR FFb) D FFc) JK FFd) D FF

Ans: D FF

Q. Odd parity generator uses which logic?a) Digitalb) Analogc) Sequentiald) none

Q. Which type of ADC is fastest?a) SARCb) Counter typec) Intigrated typed) Flash

ANS: Flash/Parallel

Q. Which one of the following is fastest read/writable memory?a) PROMb) EEPROMc) Flashd) none

Ans: Flash

8. In array programming which one is useda) SISDb) PISDc) MISDd) None

Q.Which one of the following has high I/p impedancea) CCb) CBc) CEd) None

Q. The maximum time allowed time for each flip flop for a mod 10 synchronous counter if each flip flop delay is 25ns.a) 25 nsb) 50 nsc) 100 nsd) none

Q. The resolution for a DAC is given by 0.4% then no. of bits of DAC isa) 8- bitsb) 16- bitsc) 32- bitsd) none

Ans: 8- bits

41) The chip capacity is 256 bits, then the no.of chips required to build 1024 B memory Isa) 32b) 16c) 15d) 4

Q. Which of the following are correct?1)A flip-flop is used to store 1-bit of information2)Race around condition occurs in JK flip flop when both the inputs are 13)Master slave flip flop is used to store 2 bits of information4)A transparent latch consists of a D- flip flop

a) 1,2,3b) 1,3,4c) 1,2,4d) 2,3,4

Ans: 1,2,4

Q. output resistance of ideal OP AMP isa) 0b) 1 c) infinite d) very high

ANS: 0

Q. CMRR of an OP AMP is given as 80db and Ad is 20000.Value of Acm will bea) 4 b) 8 c) 2 d) 1

Ans: 2

Q.Si,Ge lie in ........block of periodic tablea) IIIb) Vc) IV Ad) IV B

Ans: IV A

Q.to obtain 10 mV resolution on 5 V range how many bit DAC is to be used

a) 4b) 8c) 16d) 32

Q.% resolution of a 10 bit ADCa) 1.588%b) 0.392%c) 0.0978%d) 0.0244%

Ans: 0.0978%

Q.Efficiency of half wave rectifiera) 45%b) 50%c) 86%d) 100

Digital electronics1.The number of digits in octal system isa.8b.7c.10d. none

2..The number of digits in Hexadecimal system isa.15b.17c.16d. 8

3.The number of bits in a nibble isa.16b.5c.4d.8

4.The digit F in Hexadecimal system is equivalent to ------ in decimal systema.16b.15c.17d. 8

5.Which of the following binary numbers is equivalent to decimal 10a.1000

b.1100c.1010d.1001

6.The number FF in Hexadecimal system is equivalent to ------ in decimal systema.256b.255c.240d.239

7.IC s area. analogb. digitalc. both analog and digitald. mostly analog

8.The rate of change of digital signals between High and Low Level isa. very fastb. fastc. slowd. very slow

9. Digital circuits mostly usea. Diodesb. Bipolar transistorsc. Diode and Bipolar transistorsd. Bipolar transistors and FETs

10.Logic pulsera. generates short duration pulsesb. generate long duration pulsesc. generates long and short durationd. none of above

11.What is the output state of an OR gate if the inputs are 0 and 1?a.0b.1c.3d.2

12.What is the output state of an AND gate if the inputs are 0 and 1?a.0b.1c.3d.2

13.A NOT gate has...a. Two inputs and one outputb. One input and one outputc. One input and two outputsd. none of above

14.An OR gate has...a. Two inputs and one outputb. One input and one outputc. One input and two outputsd. none of above

15.The output of a logic gate can be one of two _____?a. Inputsb. Gatesc.Statesd. none

16.Logic states can only be ___ or 0.a. 3b. 2c.1d.0

17.The output of a ____ gate is only 1 when all of its inputs are 1a. NORb. XORc. ANDd. NOT

18.A NAND gate is equivalent to an AND gate plus a .... gate put together.a. NORb. NOTc. XORd. none

19.Half adder circuit is ______?a. Half of an AND gateb. A circuit to add two bits togetherc. Half of a NAND gated. none of above

20. Numbers are stored and transmitted inside a computer ina. binary formb. ASCII code formc. decimal formd. alphanumeric form

21.The decimal number 127 may be represented bya. 1111 1111Bb. 1000 0000Bc. EEHd. 0111 1111

22.. A byte corresponds toa. 4 bitsb. 8 bitsc. 16 bitsd. 32 bits

23.A gigabyte representsa.1 billion bytesb. 1000 kilobytesc. 230 bytesd. 1024 bytes

24. A megabyte representsa. 1 million bytesb. 1000 kilobytesc. 220 bytesd. 1024 bytes

25.. A Kb corresponds toa. 1024 bitsb. 1000 bytesc.210 bytesd. 210 bits

26.A parity bit isa. used to indicate uppercase lettersb. used to detect errorsc. is the first bit in a byted. is the last bit in a byte

27. Which of these devices are two state.a. lampb. punched cardc. magnetic taped. all the above

The output impedance of of a logic pulser isa. lowb. highc. may be low or highd. none of above

28.The number of LED display indicators in logic probe are

a.1b.2c.1 or 2d.4

29.In hexadecimal number system,A is equal to decimal numbera.10b.11c.17d.18

30.Hexadecimal number F is equal to octal numbera.15b.16c.17d.18

31.Hexadecimal number E is equal to binary numbera.1110b.1101c.1001d.1111

32.Binary number 1101 is equal to octal numbera.15b.16c.17d.14

33.Octal number 12 is equal to decimal numbera.8b.11c.9d. none

34.Decimal number 10 is equal to binary numbera.1110b.1000c.1001d.1010

35.Binary number 110011011001 is equal to decimal numbera.3289b.2289c.1289d.289

36.1111+11111=a.101111

b.101110c.111111d.011111

37.Binary multiplication 1*0=a.1b.0c.10d.11

38.110012 -100012=a.10000b.01000c.00100d.00001

39.10112*1012=a.55b.45c.35d.25

40.1110112*100012=a.111101101b.111101100c.111110d.1100110

41.4 bits is equal toa. 1 nibbleb.1 bytec. 2 byted. none of above

42. which is non-volatile memorya. RAMb. ROMc. bothd. none

43. The contents of these chips are lost when the computer is switched off?a. ROM chipsb. RAM chipsc. DRAM chipsd. none of above

44.What are responsible for storing permanent data and instructions.?

a. RAM chipsb. ROM chipsc. DRAM chipsd. none of above

45. Which parts of the computer perform arithmetic calculations?a. ALUb. Registersc. Logic busd. none of above

46.How many bits of information can each memory cell in a computer chip hold?a. 0 bitsb. 1 bitc. 8 bitsd. 2 bits

47.What type of computer chips are said to be volatile?a. RAM chipsb. ROM chipsc. DRAMd. none of above

48.Which generation of computer uses more than one microprocessor?a. Second generationb. Fifth generationc.Third generationd .none of above

49.Which generation of computer developed using integrated circuits?a. Second generationb. Fifth generationc. Third generationd. none of above

50.Which generation of computer was developed from microchips?a. Second generationb. Third generationc. Fourth generationd. none of above

51.RAM can be expanded to aa. increase word sizeb. increase word numberc. increase word size or increase word numberd. none of above

52. Which memory is available in all technologiesa. PROMb. EEPROMc. ROMd. EPROM

53. Which memory does not require programming equipmenta. PROMb. EEPROMc. ROMd. EPROM

54. In CCDa. small charge is deposited for logical 1b. small charge is deposited for logical 0 or 1c. small charge is deposited for logical 0 and large charge for logical 1d. none of above

55. The internal structure of PLA is similar toa. RAMb. ROMc. both RAM or ROMd. neither RAM nor RAM

56.An output of combinational ckt depends ona. present inputsb. previous inputsc. both present and previousd .none of above

57.Which are combinational gatesa. NAND & NORb. NOT & ANDc. X-OR & X-NORd. none of above

58.. As access time is decreased, the cost of memorya. remains the sameb. increasesc. decreasesd. may increase or decrease

59. Which is correct:a. A.A=0b. A+1=Ac. A+A=A'd. A'.A'=0

60.A counter is aa. Sequential cktb. Combinational cktc. both combinational and sequential cktd. none of above

61.The parity bit isa. always 1b. always 0c.1 or 0d.none of above

62.In 2 out of 5 code,decimal number 8 isa.11000b.10100c.1100d.1010

63.In number of information bits is 11,the number of parityBits in hamming code isa.5b.4c.3d.2

64.For a 4096*8 EPROM ,the number of address lines isa.14b.12c.10d.8

65. 23.6 10=……….2a.11111.10011b.10111.10011c.00111.101d.10111.1

66.BCD number 0110011=…….10a.66b.67c.68d.69

67.The total number of input states for 4 input or gate isa.20b.16c.12d.8

68.In a 4 input OR gate,the total number of High outputs for the 16 input states area.16b.15c.13

d. none of above69.In a 4 input AND gate,the total number of High outputs for the 16 input states area.16b.8c.4d.1

70.a buffer isa. always non-invertingb.always invertingc. inverting or non-invertingd.none of above

71.An AND gate has two inputs A and B and ine inhibits input S.Output is 1 ifa.A=1,B=1,S=1b. A=1,B=1,S=0c. A=1,B=0,S=1d. A=1,B=0,S=0

72. An AND gate has two inputs A and B and ine inhibits input S.Out of total 8 input states,Output is 1 ina. 1 statesb. 2 statesc. 3 statesd. 4 states

73.In a 3 input NOR gate,the number of states in which output is 1 equalsa. 1b. 2c. 3d. 4

74.Which of these are universal gatesa. only NORb. only NANDc. both NOR and NANDd. NOT,AND,OR

75. In a 3 input NAND gate,the number of gates in which output in

1equalsa.8b.7c.6d..5

76. A XOR gate has inputs A and B and output Y.Then the output equation isa.Y=A+Bb.Y=AB+A’Bc.AB+ AB’d.AB’+A’B’

77.A 14 pin NOT gate IC has………..NOT gatesa.8b.6c.5d.4

78.A 14 pin AND gate IC has………..AND gatesa.8b.6c.4d.2

79.The first contribution to logic was made bya. George Booleb. Copernicusc. Aristotled. Shannon

80.Boolean Alzebra obeysa. commutative lawb. associative lawc. distributive lawd. commutative, associative, distributive law

81. A+(B.C)=a. A.B+Cb. A.B+A.Cc. Ad.(A+B).(A+C)

82.A.0=a. 1b. Ac. 0d. A or 1

83.A+A.B=a. Bb. A.Bc. Ad. A or B

84.Demorgan’s first theorem isa. A.A’=0b. A’’=Ac. (A+B)’=A’.B’d. (AB)’=A’+B’85. Demorgan’s second theorem isa. A.A’=0b. A’’=Ac. (A+B)’=A’.B’d. (AB)’=A’+B’

86. Which of the following is truea. SOP is a two level logicb. POS is a two level logicc. both SOP and POS are two level logicd. Hybrid function is two level logic

87.The problem of logic race occurs ina. SOP functionsb. Hybrod functionsc. POS functionsd. SOP and POS functions

88. In which function is each term known as min terma. SOPb. POSc. Hybridd. both SOP and POS

89. In which function is each term known as max terma. SOPb. POSc. Hybridd. both SOP and Hybrid

90. In the expression A+BC, the total number of min terms will bea.2b. 3c.4d. 5

91.The min term designation for ABCD isa.m0

b. m10c. m14d. m15

92. The function Y=AC+BD+EF isa. POSb. SOPc. Hybridd. none of above

93. The expression Y=∏M(0,1,3,4) isa. POSb. SOPc. Hybridd. none of above

94. AB+AB’=a. Bb. Ac.1d. 0

95. In a four variable Karnaugh map eight adjacent cells give aa. Two variable termb. single variable termc. Three variable termd. four variable term

96.A karnaugh map with 4 variables hasa. 2 cellsb. 4 cellsc. 8 cellsd.16 cells

97.In a karnaugh map for an expression having ‘don’t care terms’ the don’t carescan be treated asa. 0b. 1c. 1 or 0d. none of above

98. The term VLSI generally refers to a digital IC havinga. more than 1000 gatesb. more than 100 gatesc. more than 1000 but less than 9999 gatesd. more than 100 but less than 999 gates

99.Typical size of an IC is about

a.1”*1”b. 2”*2”c. 0.1”*0.1”d. 0.0001”*0.0001”

100.A digital clock uses…………..chipa. SSIb. LSIc. VLSId. MSI

101. Digital technologies being used now-a-days area. DTL and EMOSb. TTL, ECL, CMOS and RTLc. TTL, ECL and CMOSd. TTL, ECL, CMOS and DTL

102. A TTL circuit with totem pole output hasa. high output impedanceb. low output impedancec. very high output impedanced. any of above

103. TTL usesa. multi emitter transistorsb. multi collector transistorsc. multi base transistorsd. multi emitter or collector transistors

104. Advanced schottky is a part ofa. ECL familyb. CMOS familyc. TTL familyd. none of above

105. For wired AND connection we should usea. TTL gates with active pull upb. TTL gates with open collectorc. TTL gates without active pull up and with open collectord. any of above

106. Time delay of a TTL family is abouta. 180nsb. 50nsc. 18nsd. 3 ns

107. As compared to TTL, ECL hasa. lower power dissipation

b. lower propagation delayc. higher propagation delayd. higher noise margin

108. As compared to TTL, CMOS logic hasa. higher speed of operationb. higher power dissipationc. smaller physical sized. all of above

109. 74HCT00 series isa.NAND ICb. interface between TTL and CMOSc. inverting ICd. NOR IC

110.CD 4010 is aa. inverting bufferb. non inverting hex bufferc. NOR ICd. NAND IC

111. Current requirement of a piezo buffer is abouta. 100mAb. 20mAc. 4 mAd. 0.4 mA

112. TSL inverter hasa. one inputb. two inputsc. one or two inputsd. three inputs

113. Parallel adder isa. sequential circuitsb. combinational circuitsc. either sequential or combinational circuitsd. none of above

114. The inputs to a 3 bit binary adder are 1112 and 1102. The output will bea.101b.1101c.1111d.1110

115. A half adder can be used only for addinga. 1s

b. 2sc. 4sd. 8s

116. A 3 bit binary adder should bea. 3 full addersb. 2 full adders and 1 half adderc. 1 full adder and 2 half adderd. 3 half adders

117. when two 4 bit parallel adders are cascaded we geta. 4 bit parallel adderb. 8 bit parallel adderc. 16 bit parallel adderd. none of above

118. The widely used binary multiplication method isa. repeated additionb. add and shiftc. shift and addd. any of above

119.When microprocessor processes both positive and negative numbers, the representation used isa. 1’s complementb. 2’s complementc. signed binaryd. any of above

120. Decimal -90 =………….in 8 bit 2s complementa.1000 1000b.1010 0110c.1100 1100d.0101 0101

121. In 2’s complement addition, the carry generated in the last stage isa. added to LSBb. neglectedc. added to bit next to MSBd. added to the bit next to LSB

122. The number of inputs and outputs in a full adder area. 2 and 1b. 2 and 2c. 3 and 3d. 3 and 2

123.In a 7 segment display the segments a,c,d,f,g are lit. The

decimal numberdisplayed will bea. 9b. 5c. 4d. 2

124. In a 7 segment display the segments b and c are lit up. The decimal numberdisplayed will bea. 9b. 7c. 3d. 1

125 .A device which converts BCD to seven segments is calleda. encoderb. decoderc. multiplexerd. none of these

126. Which device use the nematic fluida. LEDb. LCDc. VF displayd. none of these

127. Which of these is the most recent devicea. LEDb. LCDc. VF displayd. a and c

128. VF glows with ………. Colour when activateda. redb. orangec. bluish greend. none of these

129. Which display device resembles vacuum tubea. LEDb. LCDc. VFd. none of these

130.Which device changes parallel data to serial dataa. decoderb. multiplexerc. demultiplexer

d. flip flop

131.A 1 of 4 multiplexer requires…… data select linea. 1b. 2c. 3d. 4

132. It is desired to route data from many registers to one register. The device needed isa. decoderb. multiplexerc. demultiplexerd. counter

133.Which device has one input and many outputsa. flip flopb. multiplexerc. demultiplexerd. counter

134.Two 16:1 and one 2:1 multiplexers can be connected to form aa. 16:1 multiplexerb. 32:1 multiplexerc. 64:1 multiplexerd. 8:1 multiplexer

135. A flip flop is aa. combinational circuitb. memory elementc. arithmetic elementd. memory or arithmetic

136. I n a D latcha. data bit D is fed to S input and D’ to R inputb. data bit D is fed to R input and D’ to S inputc. data bit D is fed to both R and S inputsd. data bit D’ is not fed to any input

137. I n a D latcha. a high D sets the latch and low D resets itb. a low D sets the latch and high D resets itc. race can occurd. none of above

138.In a positive edge triggered JK flip flopa. High J and High K produce inactive stateb. Low J and High K produce inactive statec. High J and Low K produce inactive state

d. Low J and Low K produce inactive state

139.In a positive edge triggered D flip flopa. D input is called direct setb.Preset is called direct resetc. present and clear are called direct set and reset respectivelyd. D input overrides other inputs

140. In a positive edge triggered JK flip flopJ=1,K=0 and clock pulse is rising.Q willa. be 0b. be 1c. show no changed. toggle

141. For edge triggering in flip flops manufacturers usea. RC circuitb. direct coupled designc. either RC circuit or direct coupled designd. none of these

142. In a JK flip flop toggle meansa. set Q=1 and Q’=0b. set Q=0 and Q’=1c. change the output to the opposite stated. no change in input

143. A mod 4 counter will counta. from 0 to 4b. from 0 to 3c. from any number n to n+4d. none of above

144.A counter has N flip flops. The total number of states area. Nb. 2Nc. 2Nd. 4N

145.A counter has modulus of 10. The number of flip flops area. 10b. 5c. 4d. 3

146.In a ripple countera. whenever a flip flop sets to 1,the next higher FF togglesb. whenever a flip flop sets to 0,the next higher FF remains unchanged

c. whenever a flip flop sets to 1,the next higher FF faces race conditiond. whenever a flip flop sets to 0,the next higher FF faces race cond

147.A counter has 4 flip flops.It divides the input frequency bya.4b. 2c. 8d. 16

148. A decade counter skipsa. binary states 1000 to 1111b. binary states 0000 to 0011c. binary states 1010 to 1111d. binary states 1111 and higher

149.The number of flip flops needed for Mod 7 counter area. 7b. 5c. 3d. 1

150.A presettable counter with 4 flip flops start counting froma. 0000b. 1000c. any number from 0000 to 1111d. any number from 0000 to 1000151.A 4 bit down counter can count froma. 0000 to 1111b. 1111 to 0000c. 000 to 111d. 111 to 000

152. A 3 bit up-down counter can count froma. 000 to 111b. 111 to 000c. 000 to 111 and also from 111 to 000d. none of above

153.IC counters area. synchronous onlyb. asynchronous onlyc. both synchronous and asynchronousd. none of above

154. Shifting digits from left to right and vice versa is needed ina. storing numbersb. arithmetic operationsc. counting

d. storing and counting

155. The basic storage element in a digital system isa. flip flopb. counterc. multiplexerd. encoder

156. The simplest register isa. buffer registerb. shift registerc. controlled buffer registerd. bidirectional register

157. The basic shift register operations area. serial in serial outb. serial in parallel outc. parallel in serial outd. all of above

158. A universal shift register can shifta. from right to left b. from left to rightc. both from right to left and left to rightd. none of above

159. In a shift register, shifting a bit by one bit meansa. division by 2b. multiplication by 2c. subtraction by 2d. any of above

160. An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses required isa. 1b. 2c. 4d. 8

LINEAR ELECTRONICS CIRCUITSQUESTION BANKMultiple choice questions1. A differential amplifier amplifies the ---------- between two inputsignals.a) additionb) subtractionc) multiplication2. The differential amplifier can amplify ac as well as dc signalsbecause itemploys ----------.

a)b)3. Noise of input signal in differential amplifiera) increasesb) decreasesc) remains the soul4. Cascaded differential amplifier requires level translator because ofd) impedance matchinge) isolating each stagef) d.c.shift.5. In case of constant current bias ,R1 is replaced by diodes D1 & D2TOg) increase the input impedanceh) improve thermal stabilityi) increase gain6. If CMRR is high ,the wide variation of input within the tolerablelimits of theequipment makes outputj) highk) lowl) the same7. For a.c analysis of differential amplifier we usem) h-parametersn) r-parameterso) none of above8. In all types of differential amplifier DC operating pointp) is not equalq) is equalr) is dependent on application9. A single supply operational amplifier isa) LM 318b) MC 414c) LM 32410. The cascode amplifier is composed of direct coupleds) CE-CB configurationt) CC-CC configurationu) CC-CB configuration11. Input bias current is always is ________.a) greaterb) equalc) less than input offset current12. If input frequency is exceed the slew rate the output willbe________.a) distortedb) not distortedc) amplified13. The operational amplifier can be nulled by _________.a) using an offset voltage compensating network

b) using an error minimizing resistancec) cutting off the power supplies14. Open loop configuration of operational amplifier is not need for_________.a) linear operationb) nonlinear operationc) none of above15. Slew rate is defined by________a) dv/dt(max)b) di/dt(maxc) none of the above16. The slew rate has _______a) positive temperature coefficientb) negative temperature coefficientc) none of the above17. Operational amplifier offset voltage due to input bias circuit can besignificantlyreduced if we usea) offset compensatory networkb) offset minimizing resistance18. The standard supply voltage for an ordinary operational amplifier is_________a) 15 voltsb) 13 voltsc) 12 volts19. The input offset voltage _______ with negative feedback .a) increasesb) decreasesc) does not change20. Specified value of CMRR for 741 opamp is ________.a) 30 dBb) 40 dBc) 90 dB21. 741 opamp is a chip of type _________.a) industrialb) militaryc) commercial22. voltage follower is a special case of __________.a) inverting configurationb) non-inverting configurationc) difference configuration23. frequency response of differetiator is same as that of ______.a) high pass filterb) low pass filterc) band pass filter24. frequency response of integrator is same as that of ______.a) high pass filter

b) low pass filterc) band pass filter25. voltage shunt configuration is nothing but ________a) inverting configurationb) non-inverting configurationc) difference configuration26. voltage series configuration is nothing but ________a) inverting configurationb) non-inverting configuration c)c) difference configuration27. the type of feedback used for closed loop configuration is _______a) positive feedbackb) negative feedbackc) none of the above28. instrumentation amplifier is used to amplify the output of__________.a) speakerb) transducer29. basic differentiator fails to work at ________.a) low frequencyb) high frequencyc) medium frequency30. basic integrator fails to work at ________.a) low frequencyb) high frequencyc) medium frequency31. In which of the following is an operational amplifier (op-amp)used?a) oscillatorsb) filtersc) instrumentation circuitsd) all of the above32. What is the difference output voltage of any signals applied tothe input terminals?a) the differential gain times the difference input voltageb) The common-mode gain times the common input voltagec) the sum of the differential gain times the difference inputvoltage and the common-mode gain times the commoninput voltaged) the difference of the differential gain times the differenceinput voltage and the common-mode gain times thecommon input voltage33. What is the difference voltage if the inputs are an ideal inphasesignal?a) the differential gain times twice the input signalb) the differential gain times the input signalc) the common-mode gain times twice the inputsignald) the common-mode gain times the input signal34. The larger the value of CMRR, the closer the output voltage is

to the difference input times thedifference gain with the common-mode signal beingrejecteda) Trueb) False35. What is the voltage gain of the unity follower?a) 0b) 1c) –1d) infinity36. What is the scale multiplier (factor) of a basic integrator?a) R/Cb) C/Rc) –RCd) –1/RC37. Which of the following is (are) the result of gain reduction by afeedback?a) The amplifier voltage gain is a more stable and precisevalue.b) The input impedance of the circuit is increased overthat of the op-amp alone.c) The output impedance is reduced over that of the opampalone.d) all of the above38. third order Butterworth low pass filter has upper cut off frequency of1KHz.The gain of the filter drops by -------- if frequency is increased to2KHz.a) 6dbb) 18 dbc) 20 dbd) 60 db.39. For an Op-amp based wien Bridge Oscillator , if theoscillations stops after a few cycles, then the cause is ---------------.a) the amplifier gain is too high.b) The loop gain is less than 1.c) The loop gai is equal to 1.d) The loop gain is greater than 1.OBJECTIVE QUESTIONS1. What are the Four types of differential amplifiers ?2. What is the figure of merit of a differential amplifier?3. What is the swamping resistor in differential amplifier?4. The transfer curve of opamp is the graph of ________versus differential input voltage.5. Input impedance of DIBO-DA is________.6). The gain reduces in case of ________ feedback.7)The distortion increases in case of _______ feedback.8. The specified value for slew rate of 741 opamp is ______.9) The specified value for open loop gain of 741 opamp is

______.10)The level translator is to shift _______ level down toground.11)For emitter coupled amplifier RE-> _, CMRR-> -----12)The second state of OP_AMP consists of dual input ------- outputdifferential amplifier.13)Differntial amplifier is ----------coupled amplifierAs common mode gain decreases the value of CMRR -------------14)Current source is used as ----------element in amplifier15)Biasing circuit provides ----------stabilization16)Level shifter of op-amp should have ----------input impedance17)Differntial amplifier is perfectly balanced if transistors are -----------18)Level shifter of op-amp shifts o/p dc level down to ------------19)CMRR is -----------proportional to RE20)Offset voltage compensating network is connected in between pinnumber ----&----- of OPAMP21)Output stage of opamp provides ------ o/p resistance22)1DC voltage is well above the ground potential due to -------coupling.23)To overcome noise problem in level shifter ------- is used24)O/p DC level is always -------- than input dc level25) When same voltage is applied to both the terminals of differentialamplifier, it is said to operate in ------------ configuration.26) Summing amplifier can be converted into summer by takin all theresistors of ___ equal value.27)The gain of voltage follower is ____.28) Photodiode is an example of _______to________ converter.29) ______ to_______ has application in tansmission lines.30) The input resistance of NI configuration is given by ________-.31)Average rate of change of offset voltage per unit time is called as ----32)OPAMP has standard slew rate of ---------33)CMRR has standard value for 741 IC as ----------34)UGB mean gain of opamp at a frequency -----------35)Maximum rate of change of o/p voltage is -----36)Ideal OPAMP has ------ voltage gain37)For ideal opamp when i/p voltage is zero then o/p voltage is ----38)The ideal value of SVRR for 741 opamp is ------------39)Algebric difference between two i/p currents of OPAMP is -----------40).Input two-voltage range of for 741 IC is ±--------------41).The average of two-i/p bias current is called as -----------42)For DIP package of Operational amplifier DIP means -----------43)The input bias current value for 741IC is --------

44)The input offset current value for 741IC is -------45)This is the last stage of OPAMP ------------------46)The circuit in which output current is forced to equal input current issaid to be a ------47)What are the different types of adder circuit?48)What do you mean by scalar adder?49) Which type of frequency responce of integrator?50) Which type of frequency response of differentiator?51) What is difference between practical integrator and ideal integrator?52)What is difference between practical differentiator and idealdifferentiator?53)What do you mean by average adder?54)Draw the circuit diagram of subtractor55) What is importance stability resistor?56) What is importance of capacitor in integrator?57) What is importance of resistor in differentiator?58) What is the effect of noise integartig circuit?59) What is the effect of noise differentiator circuit?60)What are the application of integrating circuit?61)What are the application of differentiating circuit?62) which type of filter we get from integrator and differentiator63)What are different application of adder circuit64)What are different application of buffer circuit65)What do you mean by quality factor?66) What is the range of quality factor for band reject filter?67)What is the range of quality factor for band pass filter?68) What do you mean by order of filter?69)What do you mean by roll over frequency?70)What is the importance of higher order filter?71) What do you mean by cut-off frequency?72)Is it possible to design band pass filter by using one high pass andone low pass filter?73)What is difference between active filters and passive filters?74) What is difference between analog filters and digital filters?75) Which filters are more useful analog or digital?76) What are the disadvantages of analog filters?77) What are the different steps for the designing of low pass filters?78) What are the different steps for the designing of high pass filters?79) What is the importance of major and minor lobes in filter response?80)What happened if order of filter is not increased?81)What are different application of low pass filter circuit82)What are different application of high pass filter circuit83) Define Oscillator &Explain Barkhausain criteria for oscillations ?84) What are the advantages of Active filter over passive one ?

85) What is Butter worth Response?86) What are the advantages of Higher order filters?87) List the most commonly used filters?88) What is an all pass filter ? Where and why it is needed?89) How are the Oscillators Classified?90). What is the difference between comparator & Schmitt trigger ?91) Define Resolution, settling time, Conversion time for D/AConverter?92) What is comparator?93) What is Voltage limiting & why it is needed?94) What is the difference between Clippers & Clampers?95) What is Sample & hold Circuit? Why it is needed?96) What is the basic difference between comparator & Schmitttrigger?97) What is a Multiviberator circuit?98) What is Phase Locked Loop?100) What is the major difference between Analog & digital PLL?101)List the applications of PLL?102)What are the two basic modes of operation of IC 555?103)List important features of IC 555?104) What is a Regulator? List four different types of Regulators?105)What is Switching Regulators?

Network Filters Transmission Lines

1. Pick up wrong statement

(a) A group of interconnected individual components known as circuit elements is called a network.

(b) A humped network is an arrangement of physically separate resistors, inductors and capacitors.

(c) Distributed network is one, which the resistive, inductive and capacitive effects are inseparable for network analyses.

(d) A branch is a network having four elements.

2. Kirchoff's laws for networks are:

(a) The algebraic sum of branch currents meeting at any node is zero.

(b) The algebric sum of voltage drops in any set of branches forming a closed circuit or loop must be equal to zero.

(c) Both (a) and (b)

(d) Neither (a) and (b)

3. Mutually coupled circuit is a circuit which is:

(a) Bilateral

(b) Unilateral

(c) None of these

(d) Either (a) or (b)

4. Duality is a

(a) Transformation in which current and voltages are interchanged

(b) Active sources become passive sources

(c) Passive sources become active sources

(d) Both (b) and (c)

5. Combined inductance of two inductors L1 and L2 connected and voltages are interchanged

(a) L1 + L2

(b) (L1 + L2)/ L1

(c) (L1 + L2) / (L1 X L2)

(d) (L1 X L2) / (L1 + L2)

6. Normal analysis techniques are based on

(a) Thevenin's theorem

(b) Tellegan's theorem

(c) Superposition theorem

(d) Kirchoff's Law

7. Two voltage sources can be connected in parallel when they are equal in

(a) Magnitude

(b) Frequency

(c) Phase

(d) All the above

8. The kirchoff's law fail in

(a) Linear circuits

(b) Non-linear circuits

(c) Lumped parameter circuits

(d) Distributed parameter circuits

9. Which of the following is a nonreciprocal network ?

(a) A network consisting of all resistances

(b) A network consisting of all capacitances

(c) A network consisting of all inductances

(d) A transistor model

10. When two systems obey equations of the same form the systems are said to be

(a) Similar system

(b) Identical system

(c) Analogous system

(d) Digital system

11. For a highly selective circuit

(a) It must have large value of Q

(b) It must have high value of capacitance to produce resonance at fixed frequency

(c) Either (a) or (b)

(d) Neither (a) nor (b)

12. A network consisting of four terminals is called a

(a) One port network

(b) Two port network

(c) Four port network

(d) None of the above

13. Driving point of a network is

(a) A port where voltage or current source is connected

(b) A terminal where load is connected

(c) A port where load is connected

(d) None of the above

14. Ceramic filters are similar in construction to

(a) Crystal filters

(b) Crystal ladder filters

(c) Crystal lattice

(d) Mechanical filters

15. When two port networks are connected in parallel the resultant

(a) Z parameters are the some of individual parameters

(b) Y- parameters are the some of individual parameters

(c) Both (a) and (b)

(d) Neither (a) nor (b)

16. Electric wave filters

(a) Allow electric signals with specified frequency range

(b) Suppress signals outside a specified range

(c) Both (a) and (b) occurs simultaneously

(d) Either (a) or (b) occur at a time

17. A cascade connection of low pass filter and high pass filter is called

(a) Band pass filter

(b) Band elimination filter

(c) Neither (a) nor (b)

(d) Both (a) and (b)

18. The response of a network is decided by the location of

(a) Its poles

(b) Its zeros

(c) Either (a) nor (b)

(d) Both (a) and (b)

19. Example of two port network is

(a) Transformer

(b) Transmission line

(c) Bridge circuit and transistor circuit

(d) All of the above

20. The circuit whose properties are same in either direction is called

(a) Universal circuit

(b) Reversible circuit

(c) Unilateral circuit

(d) Bilateral circuit

21. Distortion in transmission line is due to

(a) Delay distortion

(b) Phase distortion

(c) Frequency distortion

(d) All the above

22. The general parameters distributed along a transmission line are

(a) R&L only

(b) L&C only

(c) C&G only

(d) R, L, C&G

23. Phase distortion is prominently caused by

(a) circuit transients

(b) non linear characteristics

(c) linearity

(d) none

24. The voltage or current from the receiving end towards the sending end, decreasing in amplitude with increasing distance from the load is called

(a) incident wave

(b) medium wave

(c) reflected wave

(d) none of above

25. E.M. Waves of UHF is propagated efficiently via

(a) parallel wire transmission lines

(b) open wire transmission lines

(c) wave guides

(d) coaxial cables

26. Norton theorem is valid for network containing only

(a) linear elements

(b) no linear elements

(c) resistance

(d) reactance

27. The maximum power is absorbed by one network from other, joined to it at two terminals when the impedance of one is

(a) complex conjugate of other

(b) square root of other

(c) same as other

(d) none of above

28. The decrease in effective conductor cross section at high frequencies

(a) decrease the conductor resistance

(b) increase the conductor resistance

(c) no change in conductor resistance

(d) none of above

29. Voltage standing wave ratio lies in the range

(a) 0 to 1

(b) 1 to infinity

(c) 0 to infinity

(d) -1 to +1

30. Attenuators have applications

(a) in AC circuits only

(b) in DC circuits only

(c) in AC as well DC circuits

(d) in low frequency circuits only

31. In an network

(a) the number of tree branches is equal to the number of links

(b) the number of tree branches cannot be equal to the number of links

(c) the number of tree branches has no relation with the number of links branches

(d) none of these

32. In open line transmission systems, attenuation is more at

(a) lower frequencies

(b) medium frequencies

(c) higher frequencies

(d) remains constant

33. a power ratio 100 is equivalent to

(a) 10 dB

(b) 20 dB

(c) 50 dB

(d) 100 dB

34. The velocity factor for small widely spaced conductors such as open wire line in air is very nearly

(a) 0.66

(b) 0.98

(c) 0.82

(d) 0.76

35. Transmission of power to a load over a transmission line achieves optimum value when standing wave ratio (SWR) becomes

(a) 2 : 1

(b) 1 : 2

(c) 1 : 1

(d) 1 : 10

36. The VSWR in a short circuited loss less transmission line equals

(a) infinity

(b) unity

(c) zero

(d) none of above

37. The velocity factor of a transmission line

(a) is always greater than unity

(b) depend upon the permittivity of the surrounding medium

(c) is lease for air medium

(d) is governed by skin effect

38. Which of the following is not correct

(a) voltage source is an active element

(b) current source is a passive element

(c) resistance is a passive element

(d) conductance is a passive element

39. A network is said to be nonlinear if it does not satisfy

(a) superposition condition

(b) homogeneity condition

(c) both superposition and homogeneity conditions

(d) associative condition

40. An capacitor with zero initial condition at t = 0+ act as a

(a) short circuit

(b) open circuit

(c) current source

(d) voltage source

41. An inductor stores energy in

(a) electrostatic field

(b) electromagnetic field

(c) magnetic field

(d) core

42. In series LCR circuits, at resonance,

(a) current is maximum, power factor is zero

(b) current is maximum, power factor is unity

(c) current is minimum, power factor is unity

(d) none of above

43. In an RCL series circuit, during resonance, the impedance will be

(a) zero

(b) minimum

(c) maximum

(d) none of above

44. When a source is delivering maximum power to load, the efficiency of the circuit is always

(a) 50%

(b) 75%

(c) 100%

45. In a linear network, when the ac input is doubled, the ac output becomes

(a) two times

(b) four times

(c) half

(d) one forth

46. A passive network has

(a) current sources but no voltage sources

(b) voltage sources but no current sources

(c) both current and voltage sources

(d) no voltage or current sources

47. Two resistances are connected in parallel and each dissipates 50 waits. The total power supplied by the source is

(a) 25 watts

(b) 50 watts

(c) 100 watts

(d) 200 watts

48. Three bulbs of 60 watts each are connected is parallel across 220v, 50 Hz supply. If one bulb burns out

(a) only remaining two will operate

(b) remaining two will not operate

(c) all of three will operate

(d) there will be heavy current from the supply

49. The amplitude of an audio signal is 10 and that of carrier wave is 50. Percentage modulation is:

(a) 0.2

(b) 20

(c) 5

(d) 60

50. The main advantage of PCM system is:

(a) lower bandwidth

(b) lower power

(c) lower noise