Analog Applications Journal - TI.com

High-Performance Analog Products

Analog ApplicationsJournal

Second Quarter, 2010

© Copyright 2010 Texas Instruments

Texas Instruments Incorporated


2

Analog Applications JournalHigh-Performance Analog Products www.ti.com/aaj 2Q 2010

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or “enhanced plastic.” Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Amplifiers amplifier.ti.com Data Converters dataconverter.ti.com DLP® Products www.dlp.comDSP dsp.ti.com Clocks and Timers www.ti.com/clocksInterface interface.ti.com Logic logic.ti.com Power Mgmt power.ti.com Microcontrollers microcontroller.ti.com RFID www.ti-rfid.comRF/IF and ZigBee® www.ti.com/lprf Solutions

Applications Audio www.ti.com/audio Automotive www.ti.com/automotive Communications and Telecom www.ti.com/communications Computers and Peripherals www.ti.com/computersConsumer Electronics www.ti.com/consumer-appsEnergy www.ti.com/energyIndustrial www.ti.com/industrial Medical www.ti.com/medical Security www.ti.com/security Space, Avionics and Defense www.ti.com/space-avionics-defenseVideo and Imaging www.ti.com/video Wireless www.ti.com/wireless

Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265

http://www.ti.com/aaj

http://amplifier.ti.com

http://dataconverter.ti.com

www.dlp.com

http://dsp.ti.com

http://www.ti.com/clocks

http://interface.ti.com

http://logic.ti.com

http://power.ti.com

http://microcontroller.ti.com

http://www.ti-rfid.com

http://www.ti.com/lprf

http://www.ti.com/audio

http://www.ti.com/automotive

http://www.ti.com/communications

http://www.ti.com/computers

http://www.ti.com/consumer-apps

http://www.ti.com/energy

http://www.ti.com/industrial

http://www.ti.com/medical

http://www.ti.com/security

http://www.ti.com/space-avionics-defense

http://www.ti.com/video

http://www.ti.com/wireless


3

Analog Applications Journal 2Q 2010 www.ti.com/aaj High-Performance Analog Products

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Data AcquisitionHow digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Digital audio processing provides considerable design flexibility for filter structures that can be cascaded to form equalization, low-pass, high-pass, shelf, and many other filter combinations. This article presents common design problems such as how the digital conversion and processing affects the signal level. Included are descriptions of quantization and number representation, overflow and saturation, noise effects on system performance, and the use of headroom bits and scaling to preserve signal quality.

Power ManagementDiscrete design of a low-cost isolated 3 .3- to 5-V DC/DC converter . . . . . . . . . . . . . . .12

Isolated 3.3- to 5-V converters are often required in long-distance data-transmission networks. In integrated form, these converters—particularly those with regulated outputs—often have long lead times, are relatively expensive, and are limited to certain isolation voltages. This article shows how a discrete design with standard components can provide a low-cost converter that has isolation voltages greater than 2 kV and an operating efficiency of over 60%.

Designing DC/DC converters based on ZETA topology . . . . . . . . . . . . . . . . . . . . . . . . . .16Similar to the SEPIC DC/DC converter topology, the ZETA converter topology provides a positive output voltage from an input voltage that varies above and below the regulated output voltage. This article explains how to design a ZETA converter running in continuous-conduction mode (CCM) with a coupled inductor.

Amplifiers: AudioPrecautions for connecting APA outputs to other devices . . . . . . . . . . . . . . . . . . . . . . .22

It is not uncommon for two or more audio power amplifiers (APAs) to share a single output circuit. The shared connection is sometimes by design and other times by mistake. This article explains limits that must be observed to avoid potential damage to APA circuitry when an output circuit is shared.

Amplifiers: Op AmpsOperational amplifier gain stability, Part 2: DC gain-error analysis . . . . . . . . . . . . . . . .24

The goal of this three-part series is to provide a more in-depth understanding of gain error and how it can be influenced by the actual op amp parameters in a typical closed-loop configuration. This second article focuses on DC gain error. Included is a step-by-step example of how to use data-sheet information to calculate the worst-case gain error.

Index of Articles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Contents

To view past issues of the Analog Applications Journal, visit the Web site

www.ti.com/aaj




4


Analog Applications Journal is a collection of analog application articles designed to give readers a basic understanding of TI products and to provide simple but practical examples for typical applications. Written not only for design engineers but also for engineering managers, technicians, system designers and marketing and sales personnel, the book emphasizes general application concepts over lengthy mathematical analyses.

These applications are not intended as “how-to” instructions for specific circuits but as examples of how devices could be used to solve specific design requirements. Readers will find tutorial information as well as practical engineering solutions on components from the following categories:

•DataAcquisition

•PowerManagement

•Amplifiers:Audio

•Amplifiers:OpAmps

Where applicable, readers will also find software routines and program structures. Finally, Analog Applications Journal includes helpful hints and rules of thumb to guide readers in preparing for their design.

Introduction


5

Analog Applications Journal


2Q 2010 www.ti.com/aaj High-Performance Analog Products

Data Acquisition

How digital filters affect analog audio signal levels

IntroductionDigital audio processing provides a great amount of flexi-bility to system designers. Multiple filter structures can be cascaded to form equalization (EQ), low-pass, high-pass, shelf, and many other filter combinations with relatively low power consumption and little PCB space. Infinite-impulse-response (IIR) filters can be used to easily simu-late filter functions performed by analog counterparts.

Digital audio signals are represented as an array of bits with a fixed resolution. This means that the signal is dis-crete in nature, both in amplitude and in time. If the source of this data is analog, it is quantized and sampled at fixed intervals (sampling periods) by an analog-to-digital con-verter (ADC). An audio engineer has to be careful to ensure that the signal being recorded is not clipped, while maintaining the signal as loud as possible to maximize the signal-to-noise ratio (SNR). An ADC has an amplitude limit, which may be defined as a full-scale voltage, mean-ing that any signal above a certain amount of volts at the converter’s input may result in clipping. Also, the signal is quantized into a number with a certain fixed resolution (which might also be close to the clipping point).

A mastering engineer also has to be careful when work-ing with music in the digital domain. Some EQ can be

added to boost certain frequencies as well as to achieve other effects. If there is an extravagant amount of head-room, the engineer can boost, boost, and boost. However, the final medium for the music is a CD (which is limited to 16-bit audio), so trade-offs have to be made because the rest of the music sounds too “quiet” compared to the SNR of the medium.

Boosting frequency bands in the digital domain can create certain problems when the bands are converted into the analog domain. Digital-to-analog converters (DACs) can also clip the signal if their digital input is larger than their full-scale voltage. Most processors allow a certain amount of headroom to work with intermediate values, but ultimately a DAC expects a certain data width bounded by maximum and minimum values. If the signal is scaled down and certain frequencies are then boosted to accommodate the higher peaks, then the SNR at the flat region(s) will suffer from a lower SNR.

Understanding the problemA very important aspect to consider when digital filters are used is how the signal level is affected upon its conversion from the digital to the analog domain. Suppose that a sys-tem provides a digital signal to a processing unit and con-verts it to analog using an ideal DAC without any proc ess-ing being applied, as shown in Figure 1. In this example, a 0-dBFS digital signal is provided to the DAC and converted

By Jorge Arbona, Applications Engineer,and Supriyo Palit, Software Systems Engineer

Source Data Processor DAC Amp

1-kHz EQ

–130

0

1 k Frequency (Hz)

Am

pli

tud

e( d

B)

DA

C R

an

ge

DA

C R

an

ge

DA

C(V

)O

UT

–130

0

1 k Frequency (Hz)

Am

pli

tud

e( d

B)

–130

0

1 k Frequency (Hz)

Am

pli

tud

e( d

B)

0

Time

2 –1n–1

–2n–1

0

Time

2 –1n–1

–2n–1

Time

0

1

–1

Figure 1. Full-scale digital signal represented as a 1-Vpeak analog signal



6


Data Acquisition

into the analog domain. A relationship between the digital code and the analog output amplitude is provided in the specification of a codec as the full-scale amplitude. If the specification of the full-scale amplitude is 0.707 VRMS (or 1 Vpeak), this means that a full-scale 0-dBFS digital sinu-soid will result in a 1-Vpeak sinusoid, as shown in the figure.

If a DAC is bounded by –2n–1 and 2n–1 – 1, amplifying a signal beyond these limits will distort the signal by clipping it at its output (assuming saturation logic), as shown in Figure 2. Note that it is typical for most signal processors to allow some amount of headroom before providing data to a DAC. It is important for the data within the proc ess or’s

memory to remain undistorted. Figure 2 illustrates the DAC input limits where output clipping may occur if exceeded.

A solution to this problem would be to ensure that the signal is not amplified beyond the DAC’s limits (i.e., ensure that positive gain is not applied to the source signal). However, there are cases for which the solution is not as obvious. Performing a boost relative to the full-scale amplitude of the DAC input at a specific frequency range will also cause adverse effects. In Figure 3, a 500-Hz signal is boosted by 6 dB. The distortion observed in the analog output is due to DAC clipping.

2 –1n–1

–2n–1

0

DAC’s Positive Limit

DAC’s Negative Limit

Figure 2. Excessive gain in the digital domain can make the signal exceed the DAC’s upper and lower limits

–130 –130

0 0

1 k 1 kFrequency (Hz) Frequency (Hz)

0

Time Time

0

1

–1

6 6

DAC’sLimits

Processor Analog Output

Am

pli

tud

e( d

B)

Am

pli

tud

e( d

B)

DA

C(V

)O

UT

2 –1n–1

–2n–1

Figure 3. Possible effects of boost on a specific frequency band



7


Data Acquisition

This concept is also illustrated in Figure 4. Note that the noise from the source data is inherited when passed to the larger bus width of the processor’s memory. As mentioned previously, data could be scaled down by the maximum amount of total boost to accommodate the boosted regions. However, as seen in Figure 5, even if the boost reference point is in a good position, the DAC signal might be affected by the output SNR. If the amount of boost does not compromise overall system SNR signifi-cantly, then sim ple scaling might be a viable solution. Some low-power codecs provide 100 dB of SNR, which allows some amount of scaling without sacrificing the SNR of the original 16-bit source.

Quantization and number representationIn digital processing, a real number is represented as an integer value with a fixed precision. This is called quanti-za tion, and the quantized value is an approximation of the original value. The integer value can be represented as a fixed-point number or a floating-point number. An integer value represented as a fixed-point number is composed of magnitude bits and fractional bits. An inte-ger value represented as a floating-point number is com-posed of exponent bits and mantissa bits. This discussion will henceforth be restricted to fixed-point numbers and fixed-point arithmetic.

A fixed-point number is represented as a twos- complement integer with a fixed number of digits after the radix point (or the decimal point). These digits make up the fractional part of the number. The digits before the radix point are the magnitude part and denote the range of the number. The magnitude part also contains the sign of the number.

Digital data coming into an audio processor is consid-ered to be a real number lying between –1 and 1 – 1LSB. Assuming that the real value is represented as a 16-bit fixed-point number, the number –1 will be represented as 1000000000000000 in binary (or 0x8000 in hexadecimal). In twos-complement arithmetic, 0x8000 corresponds to an integer value equal to –32768. This means that dividing the integer number by 32768 will result in the quantized

Max Max

ClippingMax Max

Boost

MinMin

Min Min

16-BitDigitalSignal

32-BitProcessorMemory

DACInput

Data ispassed tomemory

Lowfrequenciesare boosted

DACclips the

signal

Figure 4. Signal content throughout the digital signal chain

Max Max

Max Max Max

BoostRef

MinMin

Min Min Min

16-BitDigitalSignal

32-BitProcessorMemory

DACInput

Data ispassed tomemory

Data isscaleddown

Boost isadded tospecific

frequencies

Figure 5. Signal content with the use of scaling



8


Data Acquisition

approximation of the real value. The largest positive num-ber in 16 bits is 0111111111111111 in binary (or 0x7FFF in hexadecimal). The corresponding integer value is 32767. Dividing this by the scale factor of 32768 produces the largest real number that can be represented in this format. The number is 32767/32768 = 0.999969482421875. The fixed-point representation is shown in Figure 6.

In this representation, there are 15 fractional bits and 1 magnitude bit, which is also the sign bit. This means that a real number must lie between –1 and 0.999969482421875 before quantization. If the real number is above or below this range, it cannot be represented in the given format because the 16-bit register will overflow. To accommodate larger real numbers, the magnitude part needs to be increased at the expense of a reduced fractional part. This format is also known as the 1.15 format (1 = magnitude bits, and 15 = sign bits). Input to a digital processor is always represented in 1.n format, where n is the number of fractional bits (15, 19, 23, or 31). A value of 0 dBFS corresponds to the RMS value of a full-scale sine wave whose amplitude is (2n – 1)/2n. The largest real number in the given format is represented by 2n. The number of bits that are used to represent a signal is called the signal bit width or the data bit width.

Overflow and saturationOverflowoccurswhenaprocessingunit’scomputationresults in a value greater in magnitude than the data bit width.Overflowistypicallyassociatedwithcomputationinthe accumulator, where successive numbers of the same sign are added and stored. Accumulators usually keep accumulating even after overflow because the final result, if within bounds, will still come out correctly.

The output of the accumulator is saturated before it is stored as a signal value. Saturation is a process where a positive overflow is converted to the maximum positive number and a negative overflow is converted to the mini-mum negative number. Saturation is a nonlinear operation and results in severe harmonic distortion of the output. Headroom bits are used to prevent saturation.

Signal bitsSignal and noise bits affect the performance of a system. The digital audio processor adds quantization noise, and the overall performance will be the effect of both the analog circuit noise and the quantization noise. Assuming that both noise sources are the outcome of independent random processes, the overall system noise performance can be defined as

2

10 2 2C Q

SSNR 10 log ,

N N

= +

where S is a uniformly distributed random signal, NC is DAC circuit noise, and NQ is quantization noise. Using a 100-dB DAC and a 120-dB signal processor will result in an overall SNR of 99.96 dB.

It should be noted that the overall SNR is also limited by the source—the input to the digital audio processor. If the input is provided as a 16-bit number, then the signal-to-quantization-noise ratio (SQNR) of the system can, at best, be 96 dB (assuming a uniformly distributed random signal, unweighted). So, even a higher-bit internal repre-sentation (lower NQ) will not provide much improvement in this case.

Noise bitsEarlier it was mentioned that the number of signal bits de termines the performance of the digital audio system. More bits are sometimes needed for filter-response calculations.

A filter implementation consists of a data path through which the signal flows and is stored as delay elements for the filter. The signal and delay values are multiplied by the coefficients associated with the filter taps. Coefficient quan-tization also plays an important role in system perform-ance. The product of the signal and coefficient values is stored in the accumulator, which usually has a higher bit width than that of the signal. Subsequent products are added in the accumulator (at a higher bit width), and the final filter output is then stored back in signal precision (at a lower bit width).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Magnitude Part

Decimal Point

Fractional Part

Figure 6. Fixed-point representation of a real number



9


Data Acquisition

Consider the biquad filter implementation in Figure 7. In this figure, the input and output signals are represented by “A bits.” The a and b coefficients are represented by “B bits.” The input signal and its delay elements are multi-plied by the coefficients and added at the accumulator. The multiplier and accumulator together are A + B bits wide. The output signal is then quantized by the Q block and stored as an A-bit number. This introduces a quanti-zation error, which is a noise source for the digital filter; therefore extra bits are needed to ensure that the noise contribution from the digital filter is below the target SNR. These extra bits are called the noise bits. The effect of noise is more pronounced with IIR filters than with finite-impulse-response (FIR) filters. The number of noise bits also depends on the sampling frequency and the cut-off frequency of the digital filter. As the sampling fre-quency increases, the number of noise bits required increases. As the cutoff frequency decreases, the number of noise bits required increases. For a 48-kHz operation, 14 to 16 noise bits are enough to maintain the target SNR for a 40-Hz IIR filter.

Headroom bitsOtherthansignalandnoisebits,additionalbitsareneededto prevent overflow. These bits are called headroom bits. An end-to-end audio-processing chain will usually pre-serve the signal level. This means that if a 0-dB signal is input to the signal chain, the output will measure 0 dB or less. (Usually there is a signal compressor that will limit the signal swing to a few decibels below zero.) If boost filters are used to amplify specific signal bands, the remain-ing bands are usually attenuated to prevent the signal from going above 0 dB. For the latter case, when the input- signal level is at 0 dB (also known as the neutral signal level), the output signal will be lower than 0 dB, and only the amplified bands will reach 0 dB at the output. This will reduce the average volume level of the audio signal.

In spite of the signal level being maintained at 0 dB, the signal can overflow at intermediate processing points. To prevent overflow, headroom bits—i.e., bits in addition to signal and noise bits—are needed.

There can be two sources of overflow:

1. An audio-processing chain can have a filter whose gain (at some specific frequency values) is greater than 0 dB. The filter can be part of a cascaded filter chain (e.g., low-pass, high-pass, and/or band-pass filters) whose overall gain is 0 dB, or it can be a frequency-selective filter that amplifies a specific frequency band relative to the neutral signal level (e.g., shelf and EQ filters). Note that if a real number is represented in 1.n format (where n is the number of fractional bits), the magni-tude of the number is always less than 1. So, if a filter with a gain of more than 0 dB (a real number greater than 1) is used, then the output value from the filter is going to overflow if the input value is 0 dB (a real num-ber equal to 1). To prevent overflow in such cases, more headroom bits are needed.

2. A filter with a gain of less than or equal to 0 dB can have instantaneous real values greater than 1. To ensure that these instantaneous values do not overflow, headroom bits are needed.

A pictorial representation of the signal in the audio proc-essor is shown in Figure 8. An important point to note is that headroom bits are primarily used to accommodate intermediate signal growth. It is expected that at the end of the final processing block, the output will fit within the signalbitwidth.Otherwise,forlow-signalamplitudes,theoutput will still be within limits and not distort; but, for high-signal amplitudes, the output will get saturated and cause distortion. To prevent distortion, it is best to attenu-ate the signal prior to the final output.

Q

b

b

–a1

–a2

1

2

b0

z–1

z–1 z–1

z–1

A Bits B Bits A+B Bits A Bits

x(n) y(n)

+

Figure 7. Biquad filter implementation

Input-SignalBits

Output-SignalBits

HeadroomBits

NoiseBits

Figure 8. Representation of signal with headroom bits



10


Data Acquisition

ScalingScaling can be used to avoid saturation for filters with gain exceeding 0 dB. A boost filter can be used intentionally that will gain a particular frequency. Even a multisection low-pass filter can have a biquad section that actually gains certain frequencies that are higher than the available head-room (the overall response will still be 0 dB). In such a case, whether or not to use scaling can be determined by multiplying the input-signal level by the maximum gain of the total filter response. If the product is greater than the available DAC headroom, then scaling could be used to avoid saturation.

Onemethodofscalingistoattenuatethesystem’strans-fer function by an amount equal to the maximum amplitude of the filter’s transfer function. The scaling factor can be defined as

jS max H(e ) ,ω=

where 0 ≤ ω ≤ π. A second method is to scale the input signal by S. Figure 9 demonstrates the effect of scaling the transfer function. A full-scale sinusoid is input to the trans-fer function, which attenuates the flat frequencies by 6 dB. Relative to –6 dBFS, the 1-kHz signal is boosted by 6 dB.

In some cases, due to the filter structure and the instan-taneous signal sequences, the output of a filter can be more than 0 dB even though it does not have a gain of more than 0 dB. An FIR filter can increase the gain of a signal by a sum of the absolute value of the filter taps if the individual memory elements are at 0 dB with a sign opposite to that of the taps. The response of the filter may not exceed 0 dB, so additional headroom may be applied. Computing additional headroom for IIR filters is complex

because they have feedback elements, and finding a closed- form expression to determine the upper limit for instanta-neous gain is complex. In fact, one of the reasons signal processors provide additional headroom (above the DAC limit) is to allow headroom for instantaneous values. Mea-surements might be needed to compute additional head-room. In some cases, the SNR may need to be traded off for distortion that is due to saturation, and then an analog gain may need to be added to get the signal back to 0 dB.

When scaling is used, it is sometimes desirable to add additional gain (boost) in the analog output stage to com-pensate. Special care should be taken to ensure that the signal of the boosted regions does not saturate the output amplifiers as well, resulting in a distorted signal. Boost is also provided at the final output stage of the processor to compensate for scaling. This is required for multisection, 0-dB filters where scaling has been done to prevent over-flow for one or more of the individual sections. For filters that gain frequencies above 0 dB (EQ and shelf filters), the neutral signal level is scaled below 0 dB. In this case, the final-stage boost is not required. The result is a loss of SNR for the flat regions.

A more elegant solution is to limit the amount of filter gain based upon the volume gain applied at the digital proc essor, which is very well-suited for headphone use. At higher volume levels, the frequency boost can be lowered and, ultimately, be flat at full volume.

In some cases, the frequency boost is kept constant, while the signal is compressed when the volume is high. This is the anti-clipping dynamic-range compressor (DRC) function: At low volume levels, the original SNR is main-tained; but, as volume increases, the scaling is proportion-ately increased to prevent distortion.

Input

–130

0

1 k Frequency (Hz)

0

Time

6

1-kHz EQ

Am

plitu

de

( dB

)

DA

C R

an

ge

2 –1n–1

–2n–1

Figure 9. Scaling the transfer function



11


Data Acquisition

Regardless of the method used, it is important to con-sider how humans perceive sound and noise. Human hearing has an outstanding dynamic range. Headphone amplifiers trade between noise floor and output power to best accommodate this range. For instance, the TLV320AIC3254 audio codec can deliver a very high sound-pressure level (SPL) with just 500 mVRMS into a typical 32-Ω or 16-Ω headphone load, and at the same time can have a noise floor of 100 dB (A-weighted) below full scale, which can be below the threshold of hearing (see Figure 10). Sometimes, it is not even necessary to add additional amplification after scaling is performed, since the output power could be very well above the comfortable listening level.

References1. David Zaucha, “Importance of precision on performance

for digital audio filters,” 112th Audio Engineering Society (AES) Convention, Munich, Germany, April 2002, Paper 5613.

2. W. Marshall Leach, Jr., Introduction to Electroacoustics and Audio Amplifier Design, 3rd ed. (Dubuque, IA: Kendall/Hunt Publishing Co., 2003), p. 7.

Related Web siteswww.ti.com/digitalaudiowww.ti.com/sc/device/TLV320AIC3254

Amp

0-dB SPL

–6 dBV

–106 dBV

140-dB SPL Threshold of Pain

Jet Aircraft

Threshold of Hearing

Quiet Room

Truck

32 Ω

Figure 10. Headphone volume relative to human hearing


http://www.ti.com/digitalaudio

http://www.ti.com/sc/device/TLV320AIC3254

12



High-Performance Analog Products www.ti.com/aaj 2Q 2010

Power Management

Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter

Isolated 3.3- to 5-V converters are often required in long-distance data-transmission networks, where the bus-node controller operates from a 3.3-V supply to conserve power while the bus voltage is 5 V to maintain signal integrity and to provide high drive capability over long distances. Although isolated DC/DC converter modules for 3.3- to 3.3-V and 5- to 5-V conversion are readily available on the market, 3.3- to 5-V converters in integrated form are still hard to find. Even if a search for the latter proves success-ful, these specific converters—in particular, those with regulated outputs—often possess long lead times, are relatively expensive, and are usually limited to certain isolation voltages.

A discrete design can be a low-cost alternative to inte-grated modules if an application requires isolation voltages higher than 2 kV, converter efficiency higher than 60%, or reliable availability of standard components. The drawback of designing a discrete DC/DC converter is that it requires a great deal of work—choosing a stable oscillator structure andbreak-before-makecircuit,selectinggoodMOSFETsthat can be driven efficiently by standard logic gates, and performing temperature and long-term-reliability tests. This entire effort costs time and money. Therefore, before rush ing into such a project, the designer should consider the following: Integrated modules have usually passed tem-perature tests and have met other industrial qualifications. These modules not only represent the most reliable solution but also provide a fast time to market.

Converters with unregulated output are priced at around $4.50 to $5.00 each in quantities of 1000 units, while converters with regulated output often cost twice as much, approx imately $10.00 or more. Thus, it makes sense to purchase a converter with unregulated output and either buffer the output with bulk capacitance or feed it into a low-cost, low-dropout regulator (LDO)suchastheTexasInstruments (TI) TPS76650 at around $0.50.

The discrete DC/DC converter design in Figure 1 uses only readily available, standard components (such as logic ICsandMOSFETs)forthetransformerdriverandanLDOfor a regulated output voltage. While this circuit has been prototyped with through-hole components, thus making its form factor larger than that of integrated modules, the board space can be drastically reduced by using TI’s Little Logic™ devices.

The main benefits of this design are its low bill of mate-rial(BOM)andthefreedomtochooseanisolationtrans-former for isolation voltages ranging from 1 to 6 kV. The goal is to offer a low-cost alternative to fully integrated DC/DC converters with regulated outputs, and to stand-alone transformer drivers (usually priced at around $1.80), by making the transformer-driver stage as inexpen sive as possible.

Operation principleLow-cost, isolated DC/DC converters are commonly of the push-pull driver type. The operation principle is fairly sim-ple. A square-wave oscillator with a push-pull output stage drives a center-tapped transformer, whose output is recti-fied and made available in regulated or unregulated DC form. An important, functional requirement is that the square wave must have a 50% duty cycle to ensure

By Thomas KugelstadtSenior Applications Engineer

U2b

Q2

Q1T1

D1

D2

U1c

U1b

U2c

RF1CF1

Cb3

Cb4

COUT

COSC

ROSC1

RG2

RG1

Cb1Cb2

ROSC2TP1

TP4

TP6 TP8

TP5

TP7TP9

TP2

TP3

U1d U2d

RF2CF2

CIN

–VIN

–VOUT

+VIN

+VOUT(Isolated)GND

U3

VOUTVIN

U1aU2a

Figure 1. Isolated 3.3- to 5-V push-pull converter



13


Power Management

symmetrical magnetization of the transformer core. Another requirement is that the product of magnetizing voltage (E) and magnetizing time (T), known as the ET product and measured in Vμs, must not exceed the trans-former’s characteristic ET product specified by its manufac-turer. A break-before-make circuit following the oscillator must also be implemented to prevent the two legs of the push-pull output stage from conducting simultaneously and causing a circuit failure.

The discrete designThe well-known three-inverter-gate oscillator, consisting of U1a, U2a, and U2b, has been chosen because it is stable with supply variations. Its nominal frequency is set to 330 kHz through a 100-pF ceramic capacitor (COSC) and two 10-kΩ resistors (ROSC1 and ROSC2). The oscillator possesses a duty cycle of close to 50% and a maximum frequency variation of less than ±1.5% across a 3.0- to 3.6-V variation in supply voltage. Figure 2 shows the wave-forms at the summing point of ROSC1 and ROSC2 (TP1) and at the oscillator output (TP2). All voltages are measured with respect to circuit ground.

Two Schmitt-trigger NAND gates (U1c, U1d) perform a break-before-make function to avoid overlapping of the MOSFET’sconductingphases.TwootherNANDgates(U2c, U2d) are configured as inverting buffers, generating the correct signal polarity necessary to drive the n-channel MOSFETs(Q1,Q2).Thecompletebreak-before-makeaction is shown in Figure 3. To accommodate the limited drivecapabilityofstandardlogicgates,theMOSFETshavebeen selected for their low total charge and their fast response times.

The isolation transformer (T1) has a secondary-to- primary winding ratio of 2:1, a primary inductance of 0.9 mH, and a guaranteed isolation voltage of 3 kV. The input and output waveforms of the transformer are shown in Figure 4.

TP1(VSUM)

TP2(VOSC)

Time (1 µs/div)

+1.5 x VCC

–1.5 x VCC

5 V/div

Figure 2. Oscillator waveforms at TP1 and TP2

TP2(V )OSC

TP3(RC Input)

TP4(R Input)G1

Time (500 ns/div)

TP5(R Input)G2

t = 185 ns

t = 185 ns

5 V/div

Figure 3. Break-before-make waveforms

5 V/div

TP6(Q1 Drain)

TP7(Q2 Drain)

Time (1 µs/div)

Figure 4. Transformer waveforms

5 V/div

TP8(D1 Anode)

TP9(D2 Anode)

Time (1 µs/div)

(a) Input (b) Output



14


Power Management

The two diodes (D1, D2) are fast Schottky rectifiers per-forming a full-wave rectification while providing low forward voltage at full load current (VFW < 0.4 V at 200 mA). It is possible to take the output voltage directly from a bulk capacitor (Cb3) following the diodes. In this case, the out-put is unregulated but provides the maximum efficiency of the DC/DC converter. However, the designer must ensure that the maximum supply of the affected circuitry is not exceeded, which can easily occur under low-load or open-circuit conditions. If the unregulated output voltage under minimum load proves to be too high, it is necessary to use a linear regulator after the full-wave rectifier to provide a stable output supply.

The main benefit of a linear regulator is the low ripple output.Otherbenefitsincludeshort-circuitprotectionandovertemperature shutdown. The main drawback, however, is a significantly reduced efficiency.

Figure 5 shows the ripple of the circuit in Figure 1 at an output voltage of 4.93 V, and Figure 6 compares the circuit’s efficiency with that of an integrated DC/DC module with regulated output.

Table1onthenextpageprovidesanapproximateBOMfor the discrete converter. Note that the values of the bypass capacitors are larger than the 10 nF commonly implemented in low-speed applications. This is because high-speedCMOStechnologiessuchasAHC,AC,andLVCpossess high dynamic loading, so the values for bypass capacitors must be 0.1 μF or higher to assure proper operation. This is of particular importance for the inverter buffersdrivingtheMOSFETs,wherethebypasscapacitoris 0.68 μF.

50 mV/div

VRipple

OUT

Time (1 µs/div)

V = 38 mV

Figure 5. Output ripple at VOUT = 4.93 V

I (mA)Load

0 20 40 60 80 100 120 140 160 180 200

80

70

60

50

40

30

20

10

0

Effic

ienc

y( %

)

Discrete Design

DC/DC Module

Figure 6. Efficiency comparison

ConclusionWhere board-space constraints are not an issue, the dis-crete design of an isolated 3.3- to 5-V DC/DC converter with regulated output can present a viable low-cost alterna-tive to an integrated DC/DC module with regulated output. A major benefit of the discrete design is the freedom to choose an isolation transformer for varying isolation-voltage requirements.

Related Web sitespower.ti.comwww.ti.com/sc/device/partnumberReplace partnumber with SN74AC00, SN74AHC132, or TPS76650


http://power.ti.com

http://www.ti.com/sc/device/SN74AC00

http://www.ti.com/sc/device/SN74AHC132

http://www.ti.com/sc/device/TPS76650


15


Power Management

Table 1. BOM for discrete DC/DC converter

DEVICE LABELPART NUMBER

OR VALUEDESCRIPTION

COMPONENT PRICE* (EACH)

QUANTITY TOTAL PRICE*TRANSFORMER DRIVER PRICE*

U1 SN74AHC132 Quad Schmitt-trigger NAND 0 .17 1 0 .17 0 .17

U2 SN74AC00 Quad NAND 0 .17 1 0 .17 0 .17

U3 TPS76650 250-mA LDO 0 .53 1 0 .53 —

Q1, Q2 FDN335 n-channel power MOSFET 0 .105 2 0 .21 0 .21

ROSC1, ROSC2 10 kΩ OSC resistor 0 .04 2 0 .08 0 .07

RF1, RF2 1 .54 kΩ Delay resistor 0 .035 2 0 .07 0 .07

RG1, RG2 150 Ω Gate-drive resistor 0 .035 2 0 .07 0 .07

COSC 100 pF Oscillator capacitor 0 .04 1 0 .04 0 .04

CF1, CF2 47 pF Delay capacitor 0 .04 2 0 .08 0 .08

Cb1 0 .1 µF Bypass capacitor 0 .02 3 0 .06 0 .02

Cb2 0 .68 µF Bypass capacitor 0 .03 1 0 .03 0 .03

Cb3 0 .1 µF LDO input capacitor 0 .02 1 0 .02 —

CIN, Cb4, COUT 4 .7 µF Bulk capacitor 0 .12 3 0 .36 0 .12

D1, D2 MBR0520L Schottky diode 0 .045 2 0 .09 —

T1 TGRTI-360NARL 1:2 transformer, 3 kV 2 .31 1 2 .31 —

TOTAL 4.28 1.09

*Typical price in U .S . dollars in quantities of 1000 units .


16




Power Management

Designing DC/DC converters based on ZETA topology

IntroductionSimilar to the SEPIC DC/DC converter topology, the ZETA converter topology provides a positive output voltage from an input voltage that varies above and below the output voltage. The ZETA converter also needs two inductors and a series capacitor, sometimes called a flying capacitor. Unlike the SEPIC converter, which is configured with a standard boost converter, the ZETA converter is config-uredfromabuckcontrollerthatdrivesahigh-sidePMOSFET. The ZETA converter is another option for regulating an un regulated input-power supply, like a low-cost wall wart. To minimize board space, a coupled inductor can be used. This article explains how to design a ZETA converter running in continuous-conduction mode (CCM) with a coupled inductor.

Basic operationFigure 1 shows a simple circuit diagram of a ZETA converter, consisting of an input capac-itor, CIN; an output capacitor, COUT; coupled inductors L1a and L1b; an AC coupling capac itor, CC;apowerPMOSFET,Q1;andadiode, D1. Figure 2 shows the ZETA con-verter operating in CCM when Q1 is on and when Q1 is off.

To understand the voltages at the various circuit nodes, it is important to analyze the circuit at DC when both switches are off and not switching. Capacitor CC will be in parallel with COUT, so CC is charged to the output voltage, VOUT, during steady-state CCM. Figure 2 shows the volt ages across L1a and L1b during CCM operation.

When Q1 is off, the voltage across L1b must be VOUT since it is in parallel with COUT. Since COUT is charged to VOUT, the voltage across Q1 when Q1 is off is VIN + VOUT; there fore the voltage across L1a is –VOUT relative to the drain of Q1. When Q1 is on, capacitor CC, charged to VOUT, is connected in series with L1b; so the voltage across L1b is +VIN, and diode D1 sees VIN + VOUT.

By Jeff FalinSenior Applications Engineer

L1a

L1bCC

D1CIN COUT

Q1

VIN VOUT

Figure 1. Simple circuit diagram of ZETA converter

VOUTVIN

CIN

CC

Q1 is On

– V +OUT + V –IN

VIN

+

–

COUTL1a

L1bIL1a

GND

IL1b

Figure 2. ZETA converter during CCM operation

(a) When Q1 is on

(b) When Q1 is off

VOUTVIN

CIN

CC

Q1 is Off

– V +OUT– V +OUT

VOUT

–

+

COUTL1a

L1b

IL1a

GND

IL1b



17


Power Management

The currents flowing through various circuit components are shown in Figure 3. When Q1 is on, energy from the input supply is being stored in L1a, L1b, and CC. L1b also provides IOUT. When Q1 turns off, L1a’s cur-rent continues to flow from current provided by CC, and L1b again provides IOUT.

Duty cycleAssuming 100% efficiency, the duty cycle, D, for a ZETA converter operating in CCM is given by

OUT

IN OUT

VD .

V V=

+ (1)

This can be rewritten as

= =

−IN OUT

OUT IN

D I V.

1 D I V (2)

Dmax occurs at VIN(min), and Dmin occurs at VIN(max).

Selecting passive componentsOneofthefirststepsindesigninganyPWMswitching regulator is to decide how much inductor ripple current, ∆IL(PP), to allow. Too much increases EMI, while too little may result in unstable PWM operation. A rule of thumb is to assign a value for K between 0.2 and 0.4 of the average input current. A desired ripple current can be calculated as follows:

L(PP) IN

OUT

Desired I K I

DK I .1 D

∆ = ×

= × ×−

(3)

In an ideal, tightly coupled inductor, with each inductor having the same number of windings on a single core, the coupling forces the ripple current to be split equally between the two coupled inductors. In a real coupled inductor, the inductors do not have equal inductance and the ripple currents will not be exactly equal. Regard less, for a desired ripple-current value, the inductance required in a coupled inductor is estimated to be half of what would be needed if there were two separate inductors, as shown in Equation 4:

INmin min

L(PP) SW(min)

1 V DL1a L1b

2 I f×

= = ×∆ ×

(4)

To account for load transients, the coupled inductor’s saturation current rating needs to be at least 1.2 times the steady-state peak current in the high-side inductor, as computed in Equation 5:

L

L1a(PK) OUTD I

I I1 D 2

∆= × +

− (5)

Note that IL1b(PK) = IOUT+ ∆IL/2, which is less than IL1a(PK).

Like a buck converter, the output of a ZETA converter has very low ripple. Equation 6 computes the component of the output ripple voltage that is due solely to the capac-itance value:

∆∆ =

× ×OUT

L1b(PP) IN(max)C (PP)

OUT SW(min)

I [at V ]V ,

8 C f (6)

where fSW(min) is the minimum switching frequency. Equation 7 computes the component of the output ripple voltage that is due solely to the output capacitor’s ESR:

∆ = ∆ ×

OUT OUTESR _C (PP) L1b(PP) IN(max) CV I [at V ] ESR (7)

Note that these two ripple-voltage components are phase-shifted and do not directly add together. For low-ESR (e.g., ceramic) capacitors, the ESR component can be ignored. A minimum capacitance limit may be necessary to meet the application’s load-transient requirement.

The output capacitor must have an RMS current rating greater than the capacitor’s RMS current, as computed in Equation 8:

OUT

L1b(PP) IN(max)C (RMS)

I [at V ]I

3

∆= (8)

D × TS

TS

(1 – D) × TS

V + VIN OUT

IIN

I + lIN OUT

IQ1(Peak)

IIN

IOUT

–IOUT

VQ1

lQ1

lL1a

IL1b

*Measured flowing into C from Q1’s drain.C

I + lIN OUTlD1

l*CC

Figure 3. ZETA converter’s component currents during CCM



18


Power Management

The input capacitor and the coupling capacitor source and sink the same current levels, but on opposite switching cycles. Similar to a buck converter, the input capacitor and the coupling capacitor need the RMS current rating,

IN C

OUTC (RMS) C (RMS) OUT

IN(min)

VI I I .

V= = (9)

Equations 10a and 10b compute the component of the output ripple voltage that is due solely to the capacitance value of the respective capacitors:

×∆ =

×IN

max OUTC (PP)

IN SW(min)

D IV

C f (10a)

×∆ =

×C

max OUTC (PP)

C SW(min)

D IV

C f (10b)

Equations 11a and 11b compute the component of the output ripple voltage that is due solely to the ESR value of the respective capacitors:

∆ = + ×

= ×−

IN IN

IN

ESR _C (PP) IN(max) OUT C

OUTC

max

V (I I ) ESR

IESR

1 D

(11a)

∆ = + ×

= ×−

C C

C

ESR _C (PP) IN(max) OUT C

OUTC

max

V (I I ) ESR

IESR

1 D

(11b)

Again, the two ripple-voltage components are phase-shifted and do not directly add together; and, for low-ESR capaci-tors, the ESR component can again be ignored. A typical ripple value is less than 0.05 times the input voltage for the input capacitor and less than 0.02 times the output voltage for the coupling capacitor.

Selecting active componentsThepowerMOSFET,Q1,mustbecarefullyselectedsothat it can handle the peak voltage and currents while minimizing power-dissipation losses. The power FET’s current rating will determine the ZETA converter’s maxi-mum output current.

As shown in Figure 3, Q1 sees a maximum voltage of VIN(max) + VOUT. Q1 must have a peak-current rating of

Q1(PK) L1a(PK) L1b(PK) IN OUT LI I I I I I .= + = + + ∆ (12)

At the ambient temperature of interest, the FET’s power-dissipation rating must be greater than the sum of the conductive losses (a function of the FET’s rDS(on)) and the switching losses (a function of the FET’s gate charge) as given in Equation 13:

DS(on)D _ Q1 r SWG Gate

2Q1(RMS) DS(on)

IN(max) OUT Q1(PK) GD Gate SW(max)

Gate G SW(max)

P P P P

I r

(V V ) I Q / I f

V Q f ,

= + +

= ×

+ + × × ×

+ × ×

(13)

where QGD is the gate-to-drain charge, QG is the total gate charge of the FET, IGate is the maximum drive current, and VGate is the maximum gate drive from the controller. Q1’s RMS current is

Q1( RMS ) IN(max) OUT max

OUT OUT

IN(min) max

I (I I ) D

I V.

V D

= + ×

×=

×

(14)

The output diode must be able to handle the same peak current as Q1, IQ1(PK). The diode must also be able to with-stand a reverse voltage greater than Q1’s maximum voltage (VIN(max) + VOUT) to account for transients and ringing. Since the average diode current is the output current, the diode’s package must be capable of dissipating up to IOUT × VFWD, where VFWD is the Schottky diode’s forward voltage at IOUT.

Loop designThe ZETA converter is a fourth-order converter with multi ple real and complex poles and zeroes. Unlike the SEPIC converter, the ZETA converter does not have a right-half-plane zero and can be more easily compensated to achieve a wider loop bandwidth and better load- transient results with smaller output-capacitance values. Reference 1 provides a good mathematical model based on state-space averaging. The model excludes inductor DC resistance (DCR) but includes capacitor ESR. Even though the converter in Reference 1 uses ceramic capacitors, for the following design example, the inductor DCR was sub-sti tuted for the capacitor ESR so that the model would more closely match measured values. The open-loop gain bandwidth (i.e., the frequency where the gain crosses zero with an acceptable phase margin of typically 45º), should be greater than the resonant frequency of L1b and CC so that the feedback loop can dampen the nonsinusoidal ripple on the output with fundamental frequency at that resonant frequency.

Design exampleFor this example, the requirements are for a 12-V, 1-W supply with η = 0.9 peak efficiency. The load is steady-state, so few load transients are expected. The 2-A input supply is 9 to 15 V. A nonsynchronous voltage-mode con-troller, the Texas Instruments TPS40200, was selected, running with a switching frequency between 340 and 460 kHz. The maximum allowed ripple at the input and flying capacitor is respectively 1% of the maximum voltage across each. The maximum output ripple is 25 mV, and the maximum ambient temperature is 55ºC. Because EMI is not a concern, an inductor with a lower inductance value was selected by using the minimum input voltage. Table 1 on the next page summarizes the design calcula-tions given earlier. Equations 7 through 9 and Equation 11 were ignored because low-ESR ceramic capacitors with high RMS current ratings were used.



19


Power Management

Table 1. Computations for example ZETA-converter design

BASED ON DESIGN EQUATION

COMPUTATION (ASSUMING η = 1) ADJUSTED FOR η = 0.9 SELECTED COMPONENT/RATING

Passive Components

(1) = =+max

12 VD 0 .57

12 V 9 VN/A N/A

(1) = =+min

12 VD 0 .44

12 V 15 VN/A N/A

(2) = × =−IN(max)0 .57

I 1A 1 .33 A1 0 .57

=1 .33 A

1 .48 A0 .9

N/A

(3) ∆ = × =L(PP) IN(min)Desired I [at V ] 0 .3 1 .33 A 0 .4 A =0 .4 A

0 .44 A0 .9

N/A

(4) using VIN(min)×

= = × =×

1 9 V 0 .57L1a L1b 18 .9 µH

2 0 .40 A 340 kHz× =18 .9 µH 0 .9 17 .0 µF

Coilcraft MSD1260: 22 µH – IRMS = 1 .76 A in each winding simultane-ously, ISAT = 5 A

(4) at VIN(min)×

∆ = × =×L(PP)

1 9 V 0 .57Actual I 0 .34 A

2 22 µH 340 kHzN/A

(5) = + =L1a(PK)0 .34 A

I 1 .33 A 1 .50 A2

+ =0 .34 A

1 .48 A 1 .65 A2

(4) at VIN(max)×

∆ = × =×L(PP)

1 15 V 0 .44Actual I 0 .45 A

2 22 µH 340 kHzN/A N/A

(6) = =× ×OUT(min)

0 .44 AC 6 .5 µF

8 0 .025 V 340 kHzN/A

Two 10-µF, 25-V X5R ceramics and one 4 .7-µF, 25-V X5R ceramic to pro-vide good load-transient response and to accommodate ceramic capacitor derating

(10a) for CIN×

= =× ×IN(min)

0 .57 1AC 11 .2 µF

0 .01 15 V 340 kHz=

11 .2 µF12 .4 µF

0 .9

Two 10-µF, 25-V X5R ceramics and one 4 .7-µF, 25-V X5R ceramic to accommodate ceramic capacitor derating

(10b) for CC×

= =× ×C(min)

0 .57 1AC 14 µF

0 .01 12 V 340 kHz=

14 µF15 .6 µF

0 .9

Three 10-µF, 25-V X5R ceramics to accommodate ceramic capacitor derating

Active Components

(12) = + + =Q1(PK)I 1 .33 A 1A 0 .34 A 2 .67 A + + =1 .48 A 1A 0 .34 A 2 .82 A N/A

(14)×

= =×Q1(RMS)

1A 12 VI 1 .77 A

9 V 0 .57=

1 .77 A1 .96 A

0 .9Fairchild FDC365P: –35-V, –4 .3-A, 55-mΩ PFET

(13)

= × Ω

+ + × × ×+ × × =

2D_Q1P (1 .96 A) 55 m

(15 V 12 V) 2 .82 A 2 .2 nC / 0 .3 A 460 kHz8 V 15 nC 460 kHz 0 .54 W

Included

— = × =D_D1P 1A 0 .5 V 0 .5 W N/A MBRS340: 40 V, 3 A, SMC



20


Power Management

Figure 4 shows the schematic and Figure 5 the efficiency of the ZETA converter. On the next page, Figure 6 shows the converter’s operation in deep CCM, and Figure 7 shows the loop response.

ConclusionLike the SEPIC converter, the ZETA converter is another converter topology to provide a regulated output voltage from an input voltage that varies above and below the output voltage. The benefits of the ZETA converter over the SEPIC converter include lower output-voltage ripple and easier com-pensation. The drawbacks are the requirements for a higher input-voltage ripple, a much larger flying capac itor, and a buck controller (like the TPS40200) capable of driving a high-side PMOS.

C6150 pF

C5390 pF

C1012 nF

C110.47 µF

C12330 pF

C43 x 10 µF

25 V

C12 x 10 µF25 V

C24.7 µF25 V

C82 x 10 µF

25 V C94.7 µF

25 V

C71 µF

FDC365PQ1

D1MBRS340

L122 µH

MSD1260

42

31

R57.15 k

R8178 kR9

11 k

R61 M

R42.0 k

R77.5 k

R12

R20.01

1000 pFC3

R368.1 k

V(

IN9 to 15 V)

V(12 V at up

to 1 A)

OUT

U1TPS40200D

1234

8765

RCSSCOMPFB

VDDISNSDRVGND

Figure 4. ZETA-converter design with 9- to 15-V VIN and 12-V VOUT at 1 A

Ouput Current, I (mA)OUT

0 200 400 600 800 1000

0.9

0.8

0.7

0.6

0.5

Effic

ienc

y( %

)

V = 15 VIN

V = 9 VIN

Figure 5. Efficiency of example ZETA-converter design



21


Power Management

4

321

V (50 mV/div)OUT

Time (5 µs/div)

V (200 mV/div)IN

I (500 mA/div)L1b

I (500 mA/div)L1a

Figure 6. Operation at VIN = 9 V and IOUT = 1 A

60

30

0

–30

–60

100 100 k10 k1 k

Frequency (Hz)

Ga

in (

dB

)

180

90

0

–90

–180

Ph

as

e (

de

gre

es

)

3 4

Gain Crossover Point

3

4

V = 15 VIN

V = 9 VIN

Phase = +59°

Phase = +41°

Phase(V = 9 V)

IN

Phase(V = 15 V)

IN

Gain(V = 9 V)

IN

Gain(V = 15 V)

IN

Figure 7. Loop response at VIN = 9 V and 15 V, and IOUT = 1 A

Reference1. Eng Vuthchhay and Chanin Bunlaksananusorn,

“Dynamic modeling of a zeta converter with state-space averaging technique,” Proc. 5th Int. Conf. Electrical Engineering/Electronics, Computer, Telecommu nica tions and Information Technology (ECTICON) 2008, Vol. 2, pp. 969–972.

Related Web sitespower.ti.comwww.ti.com/sc/device/TPS40200


http://power.ti.com

http://www.ti.com/sc/device/TPS40200

22




Amplifiers: Audio

Precautions for connecting APA outputs to other devices

Multiple audio power amplifiers (APAs) may be connected to one output circuit by design, to multiplex different sources or to connect an external amplifier to save battery life. Also, one ampli-fier output may be connected to another or to a power supply by mistake. Any of these connec-tions can force APA outputs to abnormal voltages, and this can damage an APA. This article explains limits that must be observed to avoid such damage.

Damage can occur whether an APA is active or shut down. The output of most APAs is protected with short-circuit protection (SCP) or overcurrent protection (OCP)whentheAPAisactive,buttherangeofvoltagesthe APA can tolerate is still the same. Generally, voltage forced into an APA output must be limited as follows to avoid APA damage:

• AnAPAoutputshouldnotbeforcedmorethan0.3Vabove the APA’s positive power-supply voltage (VDD or VCC), or more than –0.3 V below its negative power-supply voltage (ground or VSS).

• AnAPAoutputmustneverbeforcedbeyondtheAbsolute Maximum Ratings for supply voltages given in the APA’s data sheet.

How APAs respond to voltages forced into their outputsWhen shut down, APAs have different resistances at their outputs, ranging from a few ohms to several kilohms to high impedance. If an external audio source connected to an APA output can drive the resistance there, it will force its voltage at the APA output.

When active, most class-AB devices have continuous-current limiting for SCP. This kind of APA holds its output at its intended output voltage until it is forced into SCP or OCPbytheothersource.Thenitcontinuestodrawitslimit current, but its output voltage is controlled by the other source. If the APA continues to draw its limit cur-rent, it may overheat and go into thermal shutdown. Then its output voltage is controlled entirely by the other source. When the APA cools down enough, it will turn on again,

and this cycle will continue as long as the external source is connected.

A typical Class-D APA holds its output at its intended outputvoltageuntilitisforcedintoSCPorOCP.Thenitshuts down and its output voltage is controlled by the other source, without drawing significant current, as long as proper voltage limits are observed. A class-D APA with cycle-by-cycleOCPgenerallybehaveslikeacontinuous-current limiter until it shuts down.

How damage occursIf another source is connected to an APA output when it is shut down, it will force the APA output to follow its volt-age. If the APA is active and the other source can supply enoughcurrenttoforcetheAPAintoSCPorOCP,theother source will then force the APA output to follow its voltage. There are several different ways in which damage can be done.

Forward-biased body diodeSingle-supply APAs operate between a positive power supply,usuallycalledVDDorVCC,andground.Outputdevices are FETs with body diodes that are reverse-biased in normal operation. Body diodes that are reverse-biased in normal operation (see Figure 1) can be damaged if one of the diodes becomes forward-biased and conducts exces-sive current. This can happen if an output of a single- supply APA is forced more than 0.3 V above VDD (or VCC) or more than –0.3 V below ground.

By Stephen CrumpApplications Engineer, Audio Power Amplifiers, Audio and Imaging Products

VDD/HPVDD

GNDor

VSS/HPVSS

VDD/HPVDD> Output >

GND orVSS/HPVSS

GND

ExternalVoltageSource(APA orPowerSupply)

High-SideFET

Low-SideFET

Figure 1. Current conduction in forward-biased body diodes

(a) Safe operation (b) Unsafe operation

VDD/HPVDD

GND or VSS/HPVSS

Output > VDD/HPVDD

Output < GND or VSS/HPVSS

High Current toVDD/HPVDD

High Current toGND or VSS/HPVSS

(To Low-Side FET)

(To High-Side FET)



23


Amplifiers: Audio

Texas Instruments (TI) DirectPath™ APAs operate between a positive power supply, usually called VDD, and a negative rail, usually called VSS, often generated from VDD with a switching circuit. The magnitude of VSS is generally less than the magnitude of VDD. Some DirectPath APAs regulate primary VDD to a lower level for their out-puts, HPVDD, and generate a negative rail, HPVSS, from HPVDD, to control maximum output power. If an output of a DirectPath APA is forced more than 0.3 V above VDD/HPVDD or more than –0.3 V below VSS/HPVSS, one of the body diodes may become forward-biased and conduct excessive current, which can damage the diode.

Power-supply overvoltageEven if external source currents do not damage a body diode, they may flow to VDD/HPVDD or VSS/HPVSS (see

Table 1. Comparison of supply-voltage limits for APA devices*

DEVICE TPA4411 TPA6130A2 TPA6132A2 TPA6136A2

Positive Supply Voltage SVDD = 1 .8 to 4 .5 VDD = 2 .5 to 5 .5 HPVDD = 1 .8 HPVDD = 1 .8

Negative Supply Voltage SVSS ≈ –SVDD CPVSS ≈ –VDD when VDD < 2 .8 V**CPVSS ≈ –2 .8 V when VDD ≥ 2 .8 V HPVSS = –1 .8 HPVSS = –1 .8

* APA outputs must never be forced beyond absolute maximum ratings for supply voltages . •Forsingle-supplyAPAs,thisincludesVDD(orVCC). •ForDirectPathAPAslikeTPA4411,thisincludesSVDDandSVSS. •ForDirectPathAPAslikeTPA6132A2,thisincludesHPVDDandHPVSS. •SometimesnoabsolutemaximumratingisgivenforVSS/HPVSS.Inthesecases,thenegativeofthemaximumrecommended

operating voltage for VDD/HPVDD should be used . ** When VDD < 2 .8 V, CPVSS falls as VDD falls .

Figure 2). VDD/HPVDD and VSS/HPVSS typically only source current, so the diode currents may charge the supply voltages beyond their absolute maximum ratings and in turn may damage the APA and/or the supply components.

Table 1 may be helpful in understanding the different supplies for various DirectPath APAs. Supplies for devices not included here can be determined by comparing their data-sheet information to this table. Supply labels may be different from the labels shown in the table.

Related Web siteswww.ti.com/audiowww.ti.com/sc/device/partnumberReplace partnumber with TPA4411, TPA6130A2, TPA6132A2, or TPA6136A2

VDD/HPVDD

Output > VDD/HPVDD

GND

High Current toVDD/HPVDD

(+++) VDD/HPVDDOvercharged

Figure 2. Pushing APA supply voltages beyond their limits

(a) High current to VDD/HPVDD (b) High current to VSS/HPVSS

Output < VSS/HPVSS

GND

High Current toVSS/HPVSS

(– – –) VSS/HPVSSOvercharged

VSS/HPVSS


http://www.ti.com/audio

http://www.ti.com/sc/device/TPA4411

http://www.ti.com/sc/device/TPA6130A2



24




Amplifiers: Op Amps

Operational amplifier gain stability, Part 2: DC gain-error analysis

IntroductionThe goal of this three-part series of articles is to provide readers with an in-depth under-stand ing of gain accuracy in closed-loop circuits using two of the most common opera-tional amplifier (op amp) configurations: non-invertingandinverting.Often,theeffectsofvarious op amp param eters on the accuracy of the circuit’s closed-loop gain are overlooked and cause an unexpected gain error both in the DC and AC domains.

This article, Part 2, focuses on DC gain error, which is primarily caused by the finite DC open- loop gain of the op amp as well as its tempera-ture dependency. This article builds upon the results obtained in Part 1 (see Reference 1), in which two separate equations were derived for calculating the transfer functions of non- inverting and inverting op amps. Part 2 pre-sents a step-by-step example of how to calculate the worst-case gain error, starting with finding the pertinent data from the product data sheet. It then shows how to use the data in conjunction with the two aforementioned equations to perform the gain-error calculation.

In Part 3, the gain error for AC input signals will be calculated. In the AC domain, the closed-loop gain error is affected by the AC open-loop response of the op amp. Part 3 will discuss one of the most common mistakes that occur when the AC gain response is calculated.

Transfer functions of non-inverting and inverting op ampsIn Part 1 (Reference 1), the closed-loop transfer function of the non-inverting op amp configuration in the frequency domain was calculated. Specifically, the transfer function was derived with the assumption that the op amp had a first-order open-loop response. For calculating gain error, the magnitude response is of interest. For convenience, the result is repeated in Equation 1:

OL _ DC

OL _ DCCL dB 2

2 2OL _ DC0

A

1 AA ( f ) 20 log ,

f 11

f (1 A )

+ b×=

+ ×+ b×

(1)

where b is defined as

FB I

OUT I F

V R.

V R Rb = =

+ (2)

Also derived in the same article was the equation for calculating the magnitude of the inverting configuration’s closed-loop gain. The result is repeated in Equation 3:

OL _ DC

OL_ DCCL dB 2

2 2OL_ DC0

A

1 AA ( f ) 20 log

f 11

f (1 A )

a+ b×

=

+ ×+ b×

(3)

Equation 3 uses the same variable b defined by Equation 2. Additionally, the variable a is defined by Equation 4:

FB F

IN I F

V RV R R

a = =+

(4)

At this point, the closed-loop gain for non-inverting and inverting amplifiers is represented by Equations 1 and 3, respectively. These equations will be used for subsequent analysis. The analysis of DC closed-loop circuits has been treated in slightly different ways in References 2 to 7; however, the results agree with this analysis.

DC gain error for non-inverting configurationTo illustrate the impact of an op amp’s finite open-loop gain on the accuracy of DC closed-loop gain in a non-inverting configuration, a step-by-step example will be presented on how to calculate the gain error when the op amp is set in an ideal closed-loop gain. An ideal closed-loop gain of 200 (1/b = 200), as shown in Figure 1, will be used. This example focuses on using only the Texas Instruments (TI)

By Henry Surtihadi, Analog Design Engineer,and Miroslav Oljaca, Senior Applications Engineer

199 x R

R

R

VIN

VOUT

VOUT

VFB

VFB

FeedbackNetwork

199 x R

Network

Figure 1. Non-inverting op amp configuration with ideal closed-loop gain of +200



25


configuration. The difference between these two curves is the loop gain, b × AOL. Because the focus of this example is DC gain error, only the loop gain at low frequency (b × AOL_DC) is of interest.

When using the data from the typical curves, designers should consider possible variations. To calculate worst-case values, the open-loop-gain data provided in the product data sheet should be used. Such data are shown in Table 1 fortheTIOPA211/2211opamps.Asthetableshows,whenthe output signal is more than 200 mV from the supply rails and has a 10-kΩ load, the typical value for the DC open-loop gain is 130 dB, while the minimum ensured gain is 114 dB. To calculate the typical and the worst-case DC gain

Amplifiers: Op Amps

OPA211opamp,butcircuitdesignerscanrepeatthe cal cu lation with similar values from the data sheet of any other op amp they choose.

To calculate the DC closed-loop-gain error of a non-inverting op amp, Equation 1 is evaluated for zero frequency (f = 0 Hz):

OL_ DCCL _ DC CL

OL_ DC

AA A (0 Hz)

1 A= =

+ b× (5)

In the case of an ideal op amp with infinite open-loop gain, the DC closed-loop gain of the non- inverting configuration is reduced to

OL _ DC

OL _ DCCL _ DC(ideal)

A OL _ DC

A 1A lim .

1 A→∞= =

+ b× b(6)

In other words, the DC closed-loop gain is entirely determined by the external feedback network.

From the closed-loop models of non- inverting and inverting amplifiers in Figures 3 and 6, respectively, in Part 1 (see Reference 1), it can be seen that the open-loop gain of the op amp is the ratio of VOUT to the input-error volt-age, VERR. VERR is the voltage difference between the inverting and non-inverting op amp inputs. It can also be seen as input offset voltage. In a product data sheet, the open-loop gain is typically expressed in decibels. In this case, the number represents the ratio of VOUT to VERR in the logarithmic domain. For future calculation, AOL_DC must always be converted from decibels to V/V. As an example, an op amp with an open-loop gain of 106 dB can be written in terms of V/V as

OL _ DC dBA 106 dB

OUT20 20OL _ DC V/V ERR

V VA 10 10 199,526 .

V V= = = = (7)

Figure 2 shows the simplified open-loop gain of the OPA211alongwiththeclosed-loopgaininanon-inverting

Table 1. Excerpt from TI OPA211/2211 data sheet

ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18VBOLDFACE limits apply over the specified temperature range, TA = –40ºC to +125ºC . At TA = +25ºC, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted .

PARAMETER CONDITIONS

Standard Grade OPA211AI, OPA2211AI

High Grade OPA211I

UNITMIN TYP MAX MIN TYP MAX

OPEN-LOOP GAIN

Open-Loop Voltage Gain AOL (V–) + 0.2V ≤ VO ≤ (V+) – 0.2V, RL = 10kΩ

114 130 114 130 dB

AOL (V–) + 0 .6V ≤ VO ≤ (V+) – 0 .6V, RL = 600Ω

110 114 110 114 dB

Over Temperature

OPA211 AOL (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, IO ≤ 15mA

110 110 dB

OPA211 AOL (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, 15mA ≤ IO ≤ 30mA

103 103 dB

OPA2211 (per channel) AOL (V–) + 0.6V ≤ VO ≤ (V+) – 0.6V, IO ≤ 15mA

100 dB

140

120

100

80

60

40

20

0

–20

10 100 k 1 M 10 M 100 M10 k1 k100

Frequency (Hz)

Vo

ltag

e G

ain

(d

B)

LoopGain,

AOL ×

Open-Loop Gain, AOL

f0AOL_DC

Closed-Loop Gain,ACL_DC

Gain = 200 V/V or +46 dB

Figure 2. OPA211’s simplified open-loop and closed-loop gain curves



26


Amplifiers: Op Amps

errors at room temperature, the minimum AOL_DCfrom the data sheet should be substituted into Equation 5. Note that intheOPA211datasheet,“AOL_DC” is written as “AOL.”

The first step in this process is to convert AOL_DC from decibels to V/V:

130 dB20

OL _ DC V/VVA 10 3,162,278V

= = (8)

114 dB20

OL _ DC V/VVA 10 501,187V

= = (9)

A value for b of 1/200 (the ideal closed-loop gain of 200) can be used in Equation 5 to find the typical DC gain:

OL _ DCCL _ DC 130 dB OL _ DC

AA

1 A

3,162,278199.98735

11 3,162,278200

=+ b×

= =+

(10)

The actual minimum ensured DC gain can be found in the same manner:

CL _ DC 114 dB

501,187A 199.92022

11 501,187

200

= =+

(11)

The DC gain error caused by the open-loop-gain value of the op amp can then be calculated:

CL _ DC(ideal) CL _ DCtyp

CL _ DC(ideal)

A A100

A

200 199.98735 100 0.00632%200

−ε = ×

−= × =

(12)

max

200 199.92022 100 0.0399%200

−ε = × = (13)

The actual DC closed-loop gain of 199.92 has an error of 0.0399% compared to the desired ideal gain of 200.

Overtemperature,theOPA211ischaracterizedtoensure that AOL_DC is higher than 110 dB over the speci-fied temperature range and when loaded with less than 15-mA output current, which is the absolute worst case. For this value, in terms of V/V, 110 dB is equivalent to

110 dB20

OL _ DC V/VVA 10 316,228 .V

= = (14)

This number can be substituted into Equation 5 to find the absolute worst-case condition for the DC closed-loop gain:

CL _ DC 110 dB

316,228A 199.8736

11 316,228

200

= =+

(15)

The gain error for this result, 0.063%, represents a slight degradation from the room-temperature case of 0.0399% previously calculated in Equation 13.

DC gain error for inverting configurationTo illustrate the impact of the op amp’s finite open-loop gain on the accuracy of DC closed-loop gain in an invert-ing configuration, another step-by-step example will be presented of calculating the gain error when the op amp is set in an ideal closed-loop gain. This example will use an ideal closed-loop gain of –200 (–a/b = –200), as shown in Figure 3. So that results can be properly compared, the sameopamp,OPA211,willbeused.

Similar to the non-inverting case, to calculate the DC closed-loop-gain error of the inverting op amp, Equation 3 is first evaluated for zero frequency (f = 0 Hz):

OL _ DCCL _ DC CL

OL _ DC

AA A (0 Hz)

1 A= = −a

+ b× (16)

The negative sign indicates the inverting configuration.In the case of an ideal op amp with infinite open-loop

gain, the DC closed-loop gain of the inverting configura-tion is reduced to

OL _ DC

OL _ DCCL _ DC(ideal)

A OL _ DC

AA lim .

1 A→∞

a= − a = −

+ b× b (17)

200 x R

200 x R R

R

VIN

VIN VOUT

VOUT

VFB

VFB VFB

FeedbackNetwork

R 200 x R

Network Network

Figure 3. Inverting op amp configuration with ideal closed-loop gain of –200



27


Amplifiers: Op Amps

As in the non-inverting configuration, the DC closed-loop gain is entirely determined by the external feedback network.

With the same open-loop-gain specifications of 130 dB (typical) and 114 dB (minimum) at room temperature, and 110 dB (minimum) across the specified temperature range—i.e., the worst case—the same calculations can be done for the inverting configuration as were done for the non-inverting configuration. For an inverting amplifier with an ideal closed-loop gain of –200 (–a/b = –200), the coefficients a = 200/201 and b = 1/201 can be used for the following three gain calculations.

•TypicalDCgain:

OL _ DCCL _ DC 130 dB OL _ DC

AA

1 A

200 3,162,278201 1

1 3,162,278201

199.98729

= −a+ b×

= − ×+ ×

= −

(18)

•MinimumensuredDCgainatroomtemperature:

CL _ DC 114 dB

200 501,187A

1201 1 501,187201

199.9198

= − ×+ ×

= −

(19)

•Worst-caseDCclosed-loopgainovertemperature:

CL _ DC 110 dB

200 316,228A

12011 316,228

201199.87296

= − ×+ ×

= −

(20)

The DC gain error caused by the variation of the open-loop-gain value of the op amp can then be calculated:

−ε = ×

−= × =

CL _ DC(ideal) CL _ DCtyp

CL _ DC(ideal)

A A100

A

200 199.98729100 0.00636%

200

(21)

max

200 199.9198100 0.0401%

200−

ε = × = (22)

The calculated absolute worst-case condition over tem-perature for the DC closed-loop gain for the inverting configuration is 0.0635%, compared to 0.0632% for the non-inverting configuration. This example shows that the difference between the non-inverting and inverting config-urations is minimal and in many cases can be ignored.

Normalized open-loop gain versus temperatureIt should be clear at this point that the DC closed-loop gain is determined by the DC open-loop gain (AOL_DC) of the op amp. Thus, the stability of the DC open-loop gain deter mines the stability of the DC closed-loop gain. The stability of the open-loop DC gain is determined by many factors, such as the power-supply rejection ratio (PSRR), the temperature, and process variations.

Figure4showstheOPA211’snormalizedDCopen-loopgain versus temperature. Note that the changes in open-loop gain are shown in μV/V. As an alternative to repre-senting changes in AOL_DC with decibels as before, AOL_DC can also be represented in terms of μV/V. This representa-tion shows the ratio of the op amp’s change in input voltage (error or offset) to the change in its output voltage. In

5

4

3

2

1

0

–1

–2

–3

–4

–5

–75 –50 –25 0 25 50 75 100 125 150 175 200

Temperature (°C)

Op

en

-Lo

op

Ga

in( µ

V/V

)

R = 10 kL

300-mV Swing from Rails

200-mV Swing from Rails

Figure 4. OPA211’s normalized DC open-loop gain versus temperature



28


Amplifiers: Op Amps

other words, the μV/V values have an inverse correlation to the decibel values. As an example, an op amp with an open-loop gain of 199,526 V/V can be written in terms of decibels as

OUTOL _ DC V/V ERR

V VA 199,526

V V= = (23)

and

OUTOL _ DC dB ERR

VA 20 log 20 log(199,526) 106 dB.

V= = = (24)

In terms of μV/V, the same gain is written as

ERROL _ DC V/V OUT

V 1 VA 5.012 .

V 199,526 Vµ

µ= = = (25)

Figure4showshowtheOPA211’sAOL_DC (in terms of μV/V) may change over temperature. For a device with a given AOL_DC at room temperature (25ºC), AOL_DC will typically change less than 0.25 μV/V in the specified temperature range (–40ºC to 125ºC). For example, if the typical AOL_DC perform ance is 130 dB, or 0.32 μV/V, at room temperature, then over the specified temperature range, AOL_DC may typically vary between 0.32 μV/V and 0.57 μV/V. To ensure stable operation over temperature, the minimum gain is as follows:

ERROL _ DC V/V OUT

V 1 VA 1,754,386

V 0.57 V V= = =

µ (26)

OL _ DC dBA 20 log(1,754,386) 124.88 dB= = (27)

This is equivalent to an AOL_DC ranging from 124.88 dB to 130 dB. Keep in mind that these are typical data. It is sug-gested that, during the circuit-design process, the designer not use typical values but instead use minimum ensured values published by the op amp’s manufacturer.

Note that none of the calculations in this article include other factors that also affect AOL_DC, such as the PSRR or the common-mode rejection ratio. The procedure to include these types of errors is similar: Simply add the additional error to the AOL_DC term and recalculate the closed-loop DC gain.

ConclusionPart 1 of this article series explored general feedback- control-system analysis and synthesis as they apply to first-order transfer functions. The analysis technique was applied to both non-inverting and inverting op amp circuits,

resulting in a frequency-domain transfer function for each configuration. Part 2 has shown how to use these two transfer functions and manufacturer data-sheet specifica-tions to analyze the DC gain error of a closed-loop op amp circuit. This analysis also took into consideration the tem-perature dependency of the open-loop gain as well as its finite value. Part 3 will explore the frequency dependency of the closed-loop gain, which will help designers avoid the common mistake of using DC gain calculations for AC-domain analysis.

ReferencesFor more information related to this article, you can down-load an Acrobat® Reader® file at www.ti.com/lit/litnumber and replace “litnumber” with the TI Lit. # for the materials listed below.

Document Title TI Lit. #1. MiroslavOljacaandHenrySurtihadi,

“Operationalamplifiergainstability,Part1: General system analysis,” Analog Applications Journal (1Q 2010) . . . . . . . . . . . slyt367

2. Soufiane Bendaoud, “Gain error affects op amp choices,” Planet Analog (July 14, 2006) [Online].Available:http://www.planetanalog.com (Enter bendaoud in lower-case letters into the search field.)

3. RonMancini,“Op-amp-gainerroranalysis,” EDN(Dec.7,2000)[Online].Available: http://www.edn.com —

4. RonMancini,“Op-ampbandwidthand accuracy,” EDN(Feb.17,2000)[Online]. Available: http://www.edn.com —

5. Ron Mancini, “Stability analysis of voltage- feedback op amps,” Application Report. . . . . . . sloa020

6. Bonnie Baker, “A designer’s guide to op-amp gain error,” EDN(Sept.17,2009)[Online]. Available: http://www.edn.com —

7. “Opampopenloopgainandopenloopgain nonlinearity,” Analog Devices, Norwood, MA, U.S.,MT-044Tutorial[Online].Available: http://www.analog.com/static/imported-files/ tutorials/MT-044.pdf —

Related Web sitesamplifier.ti.comwww.ti.com/sc/device/OPA211


http://amplifier.ti.com

http://www.ti.com/sc/device/OPA211

http://www.planetanalog.com

http://www.edn.com

http://www.edn.com

http://www.edn.com

http://www.analog.com/static/imported-files/tutorials/MT-044.pdf

http://www.ti.com/lit/slyt367

http://www.ti.com/lit/sloa020

29



2Q 2010 www.ti.com/aaj High-Performance Analog Products

Index of Articles

Index of Articles Title Issue Page Lit. No.

Data AcquisitionAspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . 1 SLYT191Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . 4 SLYT192Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . .August 1999 . . . . . . 7 SLYT193Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 1 SLYT183Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . . .November 1999. . . . 5 SLYT184A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . . 1 SLYT175The operation of the SAR-ADC based on charge redistribution. . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 10 SLYT176The design and performance of a precision voltage reference circuit for 14-bit and

16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . . 1 SLYT168Introduction to phase-locked loop system modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . . 5 SLYT169New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . 1 SLYT158Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . 5 SLYT159Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 10 SLYT160Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . . 1 SLYT148Hardware auto-identification and software auto-configuration for the

TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . . 8 SLYT149Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 15 SLYT150Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . .February 2001. . . . . 1 SLYT136Using SPI synchronous communication with data converters — interfacing the

MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . . 7 SLYT137A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . . .February 2001. . . . 11 SLYT138A/D and D/A conversion of PC graphics and component video signals, Part 2: Software

and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 5 SLYT129Intelligent sensor system maximizes battery life: Interfacing the MSP430F123

Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . 5 SLYT123SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . . 5 SLYT114Synchronizingnon-FIFOvariationsoftheTHS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 12 SLYT115Adjusting the A/D voltage reference to provide gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . 5 SLYT109MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . 7 SLYT110Using direct data transfer to maximize data acquisition throughput. . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 14 SLYT111Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . . 5 SLYT104ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . . 5 SLYT089Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 11 SLYT090Evaluation criteria for ADSL analog front end. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 16 SLYT091Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . 5 SLYT082ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . 8 SLYT083Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169. . . . . . . . . . . . . .3Q, 2004 . . . . . . . . . 5 SLYT078Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . . .1Q, 2005 . . . . . . . . . 5 SLYT07314-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 13 SLYT074Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 20 SLYT075Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 27 SLYT076Using resistive touch screens for human/machine interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . . 5 SLYT209ASimple DSP interface for ADS784x/834x ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 10 SLYT210Operatingmultipleoversamplingdataconverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . . 5 SLYT222Low-power, high-intercept interface to the ADS5424 14-bit, 105-MSPS converter for

undersampling applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 10 SLYT223Understanding and comparing datasheets for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . 5 SLYT231Matching the noise performance of the operational amplifier to the ADC . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . . 5 SLYT237Using the ADS8361 with the MSP430 USI port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . 5 SLYT244Clamp function of high-speed ADC THS1041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . . 5 SLYT253Conversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . 5 SLYT264Calibration in touch-screen systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . . 5 SLYT277Using a touch-screen controller’s auxiliary inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . . 5 SLYT283


http://www-s.ti.com/sc/techlit/SLYT191




































http://www-s.ti.com/sc/techlit/SLYT209A












30


Index of Articles

Title Issue Page Lit. No.

Data Acquisition (Continued)Understanding the pen-interrupt (PENIRQ) operation of touch-screen controllers . . . . . . . . . . .2Q, 2008 . . . . . . . . . 5 SLYT292A DAC for all precision occasions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . . 5 SLYT300Stop-band limitations of the Sallen-Key low-pass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . . 5 SLYT306How the voltage reference affects ADC performance, Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . . 5 SLYT331Impact of sampling-clock spurs on ADC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . . 5 SLYT338How the voltage reference affects ADC performance, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 13 SLYT339How the voltage reference affects ADC performance, Part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . . 5 SLYT355How digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . . 5 SLYT375

Power ManagementStabilityanalysisoflow-dropoutlinearregulatorswithaPMOSpasselement. . . . . . . . . . . . . . . .August 1999 . . . . . 10 SLYT194Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . 13 SLYT195Migrating from the TI TL770x to the TI TLC770x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 14 SLYT196TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 8 SLYT185Synchronous buck regulator design using the TI TPS5211 high-frequency

hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 10 SLYT186UnderstandingthestablerangeofequivalentseriesresistanceofanLDOregulator . . . . . . . . . .November 1999. . . 14 SLYT187Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . .February 2000. . . . 12 SLYT177Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000. . . . 20 SLYT178Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump. . . . .May 2000 . . . . . . . . 11 SLYT170Low-cost, minimum-size solution for powering future-generation Celeron™-type

processors with peak currents up to 26 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 14 SLYT171AdvantagesofusingPMOS-typelow-dropoutlinearregulatorsinbatteryapplications . . . . . . . .August 2000 . . . . . 16 SLYT161OptimaloutputfilterdesignformicroprocessororDSPpowersupply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 22 SLYT162Understandingtheload-transientresponseofLDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 19 SLYT151Comparison of different power supplies for portable DSP solutions

working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 24 SLYT152Optimaldesignforaninterleavedsynchronousbuckconverterunderhigh-slew-rate,

load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 15 SLYT139–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 20 SLYT140Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 9 SLYT130Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 15 SLYT131Power control design key to realizing InfiniBandSM benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 10 SLYT124Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . .1Q, 2002 . . . . . . . . 12 SLYT125Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 18 SLYT126SWIFT™ Designer power supply design program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 15 SLYT116OptimizingtheswitchingfrequencyofADSLpowersupplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 23 SLYT117Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 28 SLYT118Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . 8 SLYT105Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . 12 SLYT106Understanding piezoelectric transformers in CCFL backlight applications. . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 18 SLYT107Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 5 SLYT100Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 7 SLYT101Auto-Track™ voltage sequencing simplifies simultaneous power-up and power-down. . . . . . . . .3Q, 2003 . . . . . . . . . 5 SLYT095Soft-startcircuitsforLDOlinearregulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 10 SLYT096UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1. . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 13 SLYT097UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2. . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 21 SLYT092LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 14 SLYT084Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 11 SLYT079A better bootstrap/bias supply circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 33 SLYT077Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . 5 SLYT201Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . 8 SLYT202Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 13 SLYT211New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 18 SLYT212Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 19 SLYT224TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 21 SLYT225Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . 9 SLYT232






http://www-s.ti.com/sc/techlit/slyt338
















































31


Index of Articles


Power Management (Continued)TPS79918RFLDOsupportsmigrationtoStrataFlash® Embedded Memory (P30) . . . . . . . . . . .1Q, 2006 . . . . . . . . 14 SLYT233Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 17 SLYT234TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 10 SLYT238Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 13 SLYT239Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 18 SLYT240TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . 8 SLYT245TPS65552A powers portable photoflash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 10 SLYT246Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . .3Q, 2006 . . . . . . . . 12 SLYT247Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 14 SLYT248A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 10 SLYT254bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . .4Q, 2006 . . . . . . . . 13 SLYT255Fully integrated TPS6300x buck-boost converter extends Li-ion battery life. . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 15 SLYT256Selecting the correct IC for power-supply applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . 5 SLYT259LDOwhite-LEDdriverTPS7510xprovidesincrediblysmallsolutionsize . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . 9 SLYT260Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 11 SLYT261Enhanced-safety, linear Li-ion battery charger with thermal regulation and

input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . 8 SLYT269Current balancing in four-pair, high-power PoE applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 11 SLYT270Power-management solutions for telecom systems improve performance, cost, and size. . . . . . .3Q, 2007 . . . . . . . . 10 SLYT278TPS6108x: A boost converter with extreme versatility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 14 SLYT279Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 17 SLYT280Simultaneous power-down sequencing with the TPS74x01 family of linear regulators . . . . . . . . .3Q, 2007 . . . . . . . . 20 SLYT281Driving a WLED does not always require 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . . 9 SLYT284Host-side gas-gauge-system design considerations for single-cell handheld applications . . . . . . .4Q, 2007 . . . . . . . . 12 SLYT285Using a buck converter in an inverting buck-boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . 16 SLYT286Understanding output voltage limitations of DC/DC buck converters . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 11 SLYT293Battery-charger front-end IC improves charging-system safety. . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 14 SLYT294New current-mode PWM controllers support boost, flyback, SEPIC, and

LED-driver applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . . 9 SLYT302Getting the most battery life from portable systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . . 8 SLYT307Compensating and measuring the control loop of a high-power LED driver . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 14 SLYT308Designing DC/DC converters based on SEPIC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 18 SLYT309Paralleling power modules for high-current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . . 5 SLYT320Improving battery safety, charging, and fuel gauging in portable media applications . . . . . . . . . .1Q, 2009 . . . . . . . . . 9 SLYT321Cell balancing buys extra run time and battery life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 14 SLYT322Using a portable-power boost converter in an isolated flyback application . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 19 SLYT323Taming linear-regulator inrush currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . . 9 SLYT332Designing a linear Li-Ion battery charger with power-path control . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 12 SLYT333Selecting the right charge-management solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 18 SLYT334Reducing radiated EMI in WLED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 17 SLYT340Using power solutions to extend battery life in MSP430 applications . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 10 SLYT356Designing a multichemistry battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 13 SLYT357Efficiency of synchronous versus nonsynchronous buck converters. . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 15 SLYT358Fuel-gauging considerations in battery backup storage systems . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . . 5 SLYT364Li-ion battery-charger solutions for JEITA compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . . 8 SLYT365Power-supply design for high-speed ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 12 SLYT366Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 12 SLYT371Designing DC/DC converters based on ZETA topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 16 SLYT372

Interface (Data Transmission)TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS). . . . . . . . . . . . . . . .August 1999 . . . . . 16 SLYT197Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 17 SLYT188Skew definition and jitter analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 29 SLYT179LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 33 SLYT180LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 19 SLYT172Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 30 SLYT163A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 30 SLYT153











































http://www.ti.com/lit/SLYT364













32


Index of Articles


Interface (Data Transmission) (Continued)The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 35 SLYT154The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 19 SLYT132Power consumption of LVPECL and LVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 23 SLYT127Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 18 SLYT085The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 21 SLYT086Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 16 SLYT080Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 11 SLYT203Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 25 SLYT241Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 17 SLYT249Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 18 SLYT257Enablinghigh-speedUSBOTGfunctionalityonTIDSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 18 SLYT271When good grounds turn bad—isolate!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 11 SLYT298Cascading of input serializers boosts channel density for digital inputs . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 16 SLYT301RS-485: Passive failsafe for an idle bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 22 SLYT324Message priority inversion on a CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 25 SLYT325Designing with digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 21 SLYT335

Amplifiers: AudioReducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 19 SLYT198Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . .August 1999 . . . . . 24 SLYT199PCB layout for the TPA005D1x and TPA032D0x Class-D APAs. . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 39 SLYT182An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 39 SLYT1551.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 23 SLYT141Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 27 SLYT142An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 41 SLYT145An audio circuit collection, Part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 34 SLYT134Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 40 SLYT135Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 26 SLYT128Precautions for connecting APA outputs to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 22 SLYT373

Amplifiers: Op AmpsSingle-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 20 SLYT189Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 23 SLYT190Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 36 SLYT181Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 22 SLYT173Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 26 SLYT174Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 33 SLYT164Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 38 SLYT165The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 42 SLYT166Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 48 SLYT167Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 44 SLYT156Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 48 SLYT157Fully differential amplifiers applications: Line termination, driving high-speed ADCs,

and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 32 SLYT143Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 38 SLYT144Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 48 SLYT146Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 25 SLYT133Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 35 SLYT119Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 42 SLYT120Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 46 SLYT121Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 21 SLYT112FilterPro™ low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 24 SLYT113Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 24 SLYT108RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 9 SLYT102Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . 14 SLYT103Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 20 SLYT098Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 23 SLYT099























































33


Index of Articles


Amplifiers: Op Amps (Continued)Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 31 SLYT094Opampstabilityandinputcapacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 24 SLYT087Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 28 SLYT088Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 21 SLYT081Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 19 SLYT204So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 24 SLYT213Getting the most out of your instrumentation amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 25 SLYT226High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 19 SLYT235Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 27 SLYT242Accurately measuring ADC driving-circuit settling time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 14 SLYT262New zero-drift amplifier has an IQ of 17 μA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 22 SLYT272A new filter topology for analog high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 18 SLYT299Input impedance matching with fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 24 SLYT310A dual-polarity, bidirectional current-shunt monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 29 SLYT311Outputimpedancematchingwithfullydifferentialoperationalamplifiers . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 29 SLYT326Using fully differential op amps as attenuators, Part 1: Differential bipolar input signals . . . . . . .2Q, 2009 . . . . . . . . 33 SLYT336Using fully differential op amps as attenuators, Part 2: Single-ended bipolar input signals . . . . .3Q, 2009 . . . . . . . . 21 SLYT341Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 24 SLYT342Using the infinite-gain, MFB filter topology in fully differential active filters . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 33 SLYT343Using fully differential op amps as attenuators, Part 3: Single-ended unipolar input signals . . . .4Q, 2009 . . . . . . . . 19 SLYT359Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 23 SLYT360Operationalamplifiergainstability,Part1:Generalsystemanalysis. . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 20 SLYT367Signal conditioning for piezoelectric sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 24 SLYT369Interfacing op amps to high-speed DACs, Part 3: Current-sourcing DACs simplified . . . . . . . . . .1Q, 2010 . . . . . . . . 32 SLYT368Operationalamplifiergainstability,Part2:DCgain-erroranalysis . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 24 SLYT374

Low-Power RFUsing the CC2430 and TIMAC for low-power wireless sensor applications: A power-

consumption study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 17 SLYT295Selecting antennas for low-power wireless applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 20 SLYT296

General InterestSynthesis and characterization of nickel manganite from different carboxylate

precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 52 SLYT147Analog design tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 50 SLYT122Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops

to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 29 SLYT273

































34


SLYT370

TI Worldwide Technical Support

InternetTI Semiconductor Product Information Center Home Pagesupport.ti.com

TI E2E™ Community Home Pagee2e.ti.com

Product Information CentersAmericas Phone +1(972) 644-5580

Brazil Phone 0800-891-2616

Mexico Phone 0800-670-7544

Fax +1(972) 927-6377 Internet/Email support.ti.com/sc/pic/americas.htm

Europe, Middle East, and AfricaPhone European Free Call 00800-ASK-TEXAS (00800 275 83927) International +49 (0) 8161 80 2121 Russian Support +7 (4) 95 98 10 701

Note: The European Free Call (Toll Free) number is not active in all countries. If you have technical difficulty calling the free call number, please use the international number above.

Fax +(49) (0) 8161 80 2045Internet support.ti.com/sc/pic/euro.htm

JapanPhone Domestic 0120-92-3326

Fax International +81-3-3344-5317 Domestic 0120-81-0036

Internet/Email International support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic

AsiaPhone International +91-80-41381665 Domestic Toll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kong 800-96-5941 India 1-800-425-7888 Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800 Thailand 001-800-886-0010Fax +886-2-2378-6808Email [email protected] or [email protected] support.ti.com/sc/pic/asia.htm

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringement of patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

© 2010 Texas Instruments IncorporatedPrinted in U.S.A. by (Printer, City, State)

DLP is a registered trademark and Auto-Track, DirectPath, E2E, FilterPro, Little Logic, and SWIFT are trademarks of Texas Instruments. Acrobat and Reader are registered trademarks of Adobe Systems Incorporated. The Bluetooth word mark and logos are owned by the Bluetooth SIG, Inc., and any use of such marks by Texas Instruments is under license. Celeron is a trademark and StrataFlash is a registered trademark of Intel Corporation. InfiniBand is a service mark of the InfiniBand Trade Association. ZigBee is a registered trademark of the ZigBee Alliance. All other trademarks are the property of their respective owners.

E042210


http://support.ti.com

http://e2e.ti.com

http://support.ti.com/sc/pic/americas.htm

http://support.ti.com/sc/pic/euro.htm

http://support.ti.com/sc/pic/japan.htm

http://www.tij.co.jp/pic

http://support.ti.com/sc/pic/asia.htm

Analog Applications Journal - TI.com

Documents

Transcript of Analog Applications Journal - TI.com