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13. - 14. September 2018München/Neubiberg, Am Campeon

12. September 2018 Tutor ia ls am TUM City-Campus

www.analog- fachtagung.de

A N A L O G 2 0 1 816. GMM/ITG-Fachtagung

PROGRAMM

MEET YOUR CAD GUY /MEET YOUR DESIGNER

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Inhaltsverzeichnis

Veranstalter und Organisation .......................................... 4

Programmkomitee ........................................................... 4

Informationen zur Tagung ................................................ 5

Homepage ..................................................................... 5

Programm

Mittwoch, 12. September 2018 ...................................... 6

Tutorials .................................................................... 6

Analogfachgruppentreffen ......................................... 6

Donnerstag, 13. September 2018 ................................ 10

Eingeladener Vortrag J. Sauerer … ...................10 / 24

Eingeladener Vortrag M. Ivanov … ....................11 / 26

Eingeladener Vortrag R. Findenig/G. Rutsch … .11 / 28

Postersession ..................................................11 / 16

Freitag, 14. September 2018 ......................................... 13

Eingeladener Vortrag T. Gossmann/J. M. Tomasik 13 / 30

Postersession ..................................................13 / 16

Eingeladener Vortrag V. Issakov .......................14 / 32

Eingeladener Vortrag W. Hartong, A. Schaldenbrand,

V. Zivkovic ........................................................14 / 34

Allgemeine Hinweise ...................................................... 36

Tagungsorganisation ................................................ 36

Anmeldung .............................................................. 36

Teilnahmegebühren .................................................. 36

Stornierung .............................................................. 37

Telefonische Erreichbarkeit während der Tagung ...... 37

Tagungsort .............................................................. 37

Zimmerreservierungen ............................................. 38

Abendveranstaltung ................................................ 39

Fachtagung Analog 2018

Die Fachtagung ANALOG 2018 befasst sich mit allen Teil-gebieten des Entwurfs, der Integration und der Anwendung analoger, gemischt analog / digitaler und hochfrequenter Schaltungen und Systeme.

Sie dient dem Informationsaustausch zwischen System-, Schaltungs- und CAD-Entwicklern, zwischen Industrie, Forschungseinrichtungen und Hochschulen. Sie vermittelt Ideen und Wissen durch Präsentationen von Forschungs- und Entwicklungsergebnissen sowie durch die Diskussion von Herausforderungen und Lösungsansätzen. Dabei weist sie gleichzeitig auf Lücken und ungelöste Aufgaben hin.

Die Fachtagung ist auch ein ausgezeichnetes Instrument zur Unterstützung des Ergebnistransfers bei öffentlich ge-förderten Forschungs- und Entwicklungsprojekten.

Insbesondere werden der wissenschaftliche Nachwuchs und junge Entwicklungsingenieure ihre auch in einem frühen Stadium befindlichen Forschungs- und Entwick-lungsarbeiten präsentieren.

Die Tagungssprache ist Deutsch, etliche Vorträge werden in Englisch sein.

Ein besonderes Anliegen der ANALOG 2018 ist der Austausch zwischen Schaltungsentwicklung und CAD-Entwicklung. Die ANALOG 2018 steht daher unter dem Motto

MEET YOUR CAD GUY/MEET YOUR DESIGNER

Lassen Sie sich von diesem Motto und vom Standort Campeon in München-Neubiberg zum Besuch anregen!

Ihr Organisations-Team der Analog 2018

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Veranstalter und Organisation

VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und Feinwerktechnik (GMM)

Informationstechnische Gesellschaft im VDE (ITG)

Tagungsleitung und Vorsitzender des Programmkomitees

Helmut Gräb Technische Universität München

Programmkomitee

J. Anders Universität StuttgartT. Gemmeke RWTH AachenC. Grimm Technische Universität KaiserslauternK. Hahn Universität SiegenW. Hartong Cadence Design Systems GmbH,

FeldkirchenL. Hedrich Johann Wolfgang Goethe-Universität

Frankfurt am MainE. Hennig Hochschule ReutlingenK. Hofmann TU DarmstadtJ. Kampe Ernst-Abbe-Hochschule JenaD. Killat Brandenburgische Technische Universität

Cottbus-SenftenbergD. Kissinger IHP Leibniz-Institut für innovative Mikroelek-

tronikM. Kuhl Albert-Ludwigs-Universität Freiburg - IMTEKC. Lang Melexis GmbH, ErfurtJ. Lienig Technische Universität DresdenY. Manoli Albert-Ludwigs-Universität Freiburg- IMTEKW. Mathis Gottfried Wilhelm Leibniz Universität

HannoverM. Olbrich Gottfried Wilhelm Leibniz Universität

HannoverS. Paul Universität BremenR. Popp edacentrum GmbH, HannoverH. Pretl Intel/ Johannes Kepler Universität LinzC. Zivkovic Technische Universität Kaiserslautern

T. Reich Fraunhofer-Institut für Integrierte Schaltungen IIS, Dresden

S. Sattler Friedrich-Alexander-Universität Erlangen-Nürnberg

J. Scheible Hochschule ReutlingenR. Thewes Technische Universität BerlinT. Ußmüller Universität InnsbruckR. Weigel Friedrich-Alexander-Universität Erlangen-

Nürnberg

Organisationsteam

H. Gräb Technische Universität MünchenC. Grimm Technische Universität KaiserslauternK. Hahn Universität SiegenJ. Kampe Ernst-Abbe-Hochschule JenaM. Olbrich Gottfried Wilhelm Leibniz Universität

HannoverR. Popp edacentrum HannoverR. Schnabel VDE/VDI-GMM, Frankfurt am Main

Informationen zur Tagung

Website: www.analog-fachtagung.de

VDE/VDI-Gesellschaft Mikroelektronik, Mikrosystem- und Feinwerktechnik (GMM)

Ansprechpartner

Dr.-Ing. Ronald Schnabel Stresemannallee 15 60596 FrankfurtTelefon: 069 / 6308 - 227, -360Telefax: 069 / 6308 - 9828E-Mail: gmm@vde.com

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■ Mittwoch, 12. September 2018

P R O G R A M M Z U R FA C H TA G U N G

A N A L O G 2 0 1 8

Mittwoch, 12. September 2018

Technische Universität München, Arcisstraße 21, 80333 München, Seminarraum 2999

13:00 Registrierung, Kaffee

Tutorials

13:30 Tutorial A: Analog Coverage - Yesterday‘s Dreams, Today‘s Reality and Tomorrow‘s Capabilities

Walter Hartong, Cadence, Munich, Germany Lars Hedrich, University of Frankfurt, Frankfurt/

Main, Germany Markus Olbrich, University of Hanover, Hannover,

Germany

16:00 Tutorial B: Advances in Worst Case and Yield Analysis for Circuit Design

Michael Pronath, MunEDA, Munich, Germany

17:15 Ende

17:30 Analogfachgruppentreffen

■ ANALOG 2018 – Tutorials

Tutorial A: „Analog Coverage – Yesterday‘s Dreams, Today‘s Reality and Tomorrow‘s Capabilities“

Walter Hartong, Cadence, Munich, Germany;Lars Hedrich, University of Frankfurt, Frankfurt/Main, Germany;Markus Olbrich, University of Hanover, Hannover, Germany

Analog circuits are constantly growing in complexity.

Hence, the verification environment needs to include various input voltages, output loads, temperature ranges or process variations. Many special verification tasks are mandatory, like statistical analysis, EM/IR, reliability analy-sis, post layout simulation.

Simultaneously, the requirements on verification quality are increasing drastically – the ISO26262 norm for auto-motive is the most popular example in this trend. The time to market pressure requires even the consumer market to demand strict verification quality goals. A re-spin of a large SOC due to an analog failure is not acceptable anymore.

Beside the classical interactive verification approach, more formalized techniques, verification planning, and complete-ness and quality metrics are required. Here the concept of „verification coverage“ can help to enhance the verification quality and efficiency.

In this tutorial, we will present the latest trends from the EDA industry, namely Cadence Virtuoso ADE Verifier with its new capability to do coverage driven verification for ana-log circuit. We will see how this can be used in re-live pro-jects even today.

In addition, the academic driven view on analog coverage is presented. The latter stems in parts from the ANCONA project focusing on analog coverage approaches.

Main part of the tutorial will be live demos and hands-on experience in the context of possible coverage measures, a practical view on existing measures and methodologies. Some new approaches to measure coverage and combine the results in an overall coverage view. The whole tutori-al will be accompanied by concrete results on small and middle size examples circuits.

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Walter Hartong studied Electrical Engi-neering/Microelectronics at the Universi-ty of Hannover.

He worked as a research assistant at the Institute of Microelectronic Systems and finished his PhD in Computer Science in 2002.

Since 2002, he has been with Cadence Design Systems in Munich, initially as application engineer. His current role is Product Engineering Architect focusing on analog simulati-on environment and verification.

He is one of the core drivers in the ADE Verifier develop-ment and contributes to Explorer and Assembler as well. Walter is also interested in mixed-signal topics, analog fault simulation and behavioral modeling.

Lars Hedrich received the Diploma degree in electrical engineering in 1992 and the Ph.D. in 1997 from the University of Hannover and became a junior profes-sor at the same University in 2002.

Since 2004 he has been full professor at the Institute of Computer-Science, University of Frankfurt, and head of the

design methodo logy group at the same institute.

His research interests include several areas of analog de-sign automation: symbolic analysis of linear and nonlinear circuits, behavioral modeling, reliability analysis and design, circuit synthesis, and formal verification.

Markus Olbrich received his Dipl.-Ing. and Dr.-Ing. degrees from Leibniz Uni-versity of Hannover in 1996 and 2005, respectively.

He is now with the Institute of Microelec-tronic Systems in Hannover as group leader since 2001 and Academic Direc-tor since 2010.

His research interests cover mixed-signal verification me-thods including formal verification and he also works on physical design methods.

■ ANALOG 2018 – Tutorials ■ ANALOG 2018 – Tutorials

Tutorial B: „Advances in Worst Case and Yield Analysis for Circuit Design“

Michael Pronath, MunEDA, Munich, Germany

In this tutorial we will review a statistical worst case analysis methodology for designers of analog/RF/digital full custom circuits, which includes operating conditions such as tem-perature or Vdd, aging, as well as random variation of the manufacturing process.

We will discuss its mathematical background, accuracy and efficiency, demonstrate recent algorithmic improvements of worst case analysis software, together with applications of high sigma statistical analysis to analog/RF circuits and to large regular circuit structures such as memory arrays.

Michael Pronath has extensive expe-rience in statistical analysis, modeling, and optimization.

Prior to founding MunEDA, Michael worked as a research assistant at the Institute for Electronic Design Automation at the Technical University of Munich.

He holds a PhD in Electrical Engineering from the Techni-cal University of Munich as well as an MBA of University of Hagen.

Dr. Pronath is author and coauthor of several international publications on methods of analog integrated circuit design and testing of mixed-signal circuits.

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■ Donnerstag, 13. September 2018 ■ Donnerstag, 13. September 2018

Donnerstag, 13. September 2018

Am Campeon 1-12, 85579 Neubiberg Konferenzzone im Gebäude 02

08:15 Registrierung, Kaffee

08:45 Begrüßung, Verleihung Best Paper Award Helmut Gräb, TU München

09:00 Eingeladener Vortrag (siehe Seite 24) Moderator: Markus Olbrich, Leibniz Universität

Hannover

Cognitive Sensing: What Does This Mean for Us?

Josef Sauerer, Fraunhofer-Institute for Integrated Circuits IIS, Erlangen

09:45 Kurzvorstellung Poster Moderator: Helmut Gräb, TU München

10:15 Kaffee/Postersession

10:45 Session 1: Sensoren

Moderator: Torsten Reich, Fraunhofer IIS/EAS

Front-End für Long-Range-UHF-RFID- Sensortags mit einer Empfindlichkeit von -30 dBm

Jacek Nowak, Dominik Krausse, Ralf Sommer, TU Ilmenau

Design of a High Accuracy Spatially Distri-buted Temperature Sensor Array for CMOS Lab-on Chip Applications

Yvonne Ebensberger, Timo Lausen, Roland Thewes, TU Berlin

Design of Quasi-Synchronous Finite Sta-te Machines Using a Local On-Demand Clocking Approach

Athanasios Gatzastras, Dominik Wrana, Tobias Wolfer, HS Reutlingen, Georg Gläser, Benjamin Saft, Eric Schäfer, IMMS Institut für Mikroelek-tronik- und Mechatronik-Systeme gemeinnützige GmbH, Eckhard Hennig, HS Reutlingen

11:45 Mittagessen/Postersession

13:00 Eingeladener Vortrag (siehe Seite 26) Moderator: Roland Thewes TU Berlin

Current Sensing Circuits and Applications Misha Ivanov, Texas Instruments Deutschland

GmbH

13:45 Session 2: ADC, DAC, PLL

Moderator: Carna Zivkovic, TU Kaiserslautern

Ultra-Low-Power SAR ADC in 22 nm FD-SOI Technology Using Body-Biasing

Marcel Jotschke, Sunil Satish Rao, Benjamin Prautsch, Torsten Reich, Fraunhofer IIS/EAS Dres-den

A Reusable Triple Core 12-bit Current Stee-ring Digital-to-Analog Converter for High-Performance Transceivers in Industry 4.0 Applications

Reimund Wittmann, Jan Steinkamp, Frank Henkel, IMST GmbH Kamp-Lintfort, Klaus Tittelbach-Helmrich, IHP, Andreas Wolf, Dr. Wolf Wireless GmbH

Design of a 28-32 GHz Low-Noise PLL with Automatic Frequency Calibration

Frank Herzel, Arzu Ergintav, Ulrich Jagdhold, Dietmar Kissinger, IHP GmbH Leibniz-Institut für innovative Mikroelektronik, Frankfurt/Oder

14:45 Pause

15:00 Eingeladener Vortrag (siehe Seite 28) Moderator: Jens Lienig, TU Dresden

Behavioural Modeling for SoC Simulation: Bridging Analog and Firmware Demands

Rainer Findenig, Gabriel Rutsch, Infineon Techno-logies AG

15:45 Kaffee/Postersession (siehe Seite 16)

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■ Donnerstag, 13. September 2018

16:15 Session 3: Verifikation

Moderator: Eckhard Hennig, HS Reutlingen

Coverage Measures and a Unified Coverage Model for Analog Circuit Design

Andreas Fürtig, Goethe-Universität Frankfurt a. M., Walter Hartong, Cadence Design Systems, Lars Hedrich, Goethe-Universität Frankfurt a. M., Mar-kus Olbrich, Malgorzata Rechmal, Leibniz Univer-sität Hannover, Louis-Francois Tanguay, Cadence Design Systems

Verification of Analog/Mixed-Signal Systems with AADD

Carna Zivkovic, Christoph Grimm, TU Kaiserslautern

Automatic Abstraction of Analog Circuits to Hybrid Automata

Ahmad Tarraf, Lars Hedrich, Goethe-Universität Frankfurt a. M.

17:15 Panel: The Design Productivity Gap has been Growing for 20 Years – Who Cares?

Moderator: Klaus Hofmann, TU Darmstadt

Panelists: (siehe Seite 20 - 23)

Dave Reed, Synopsys Klaus Cerny, Cadence Design Systems Vadim Issakov, Infineon Technologies, Neubiberg Dietmar Kissinger, IHP Frankfurt/Oder Ulrich Nerz, Infineon Technologies, Neubiberg

18:15 Ende des Panels

19:30 Abendveranstaltung im Donisl, Traditions-wirtshaus am Marienplatz

22:00 Ende des ersten Veranstaltungstages

■ Freitag, 14. September 2018

Freitag, 14. September 2018

Am Campeon 1-12, 85579 Neubiberg Konferenzzone im Gebäude 02

08:30 Registrierung, Kaffee

09:00 Eingeladener Vortrag (siehe Seite 30) Moderator: Thomas Ußmüller, Universität Innsbruck

Competitive CMOS RF Transceiver Design Timo Gossmann, Jakob M. Tomasik, Intel

Deutschland GmbH

09:45 Session 4: Advanced CMOS

Moderator: Matthias Kuhl, TU Hamburg-Harburg

Low-Power 24 GHz LNA in a Sub-28nm CMOS Vadim Issakov, Radu Ciocoveanu, Andreas Wert-

hof, Infineon Technologies AG, Robert Weigel, Friedrich-Alexander Universität Erlangen-Nürnberg

Comparison and Optimization of the Minimum Supply Voltage of Schmitt Trigger Gates versus CMOS Gates under Process Variations

Alexander Bleitner, Jacob Goeppert, Niklas Lotze, Matthias Keller, Yiannos Manoli, IMTEK Albert-Ludwigs-Universität Freiburg

Analysis and Optimization of Voltage Refe-rence Circuits Based on Sub 1V MOSFETs Operating in Different CMOS Technologies

Giuseppe Quarata, Michael Pronath, MunEDA GmbH München

10:45 Kaffee/Postersession (siehe Seite 16)

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■ Freitag, 14. September 2018

11:15 Eingeladener Vortrag (siehe Seite 32) Moderator: Thomas Gemmeke, RWTH Aachen

Design Challenges and Methodology Con-siderations for Highly Integrated mm-Wave Systems in Silicon-Based Technologies

Vadim Issakov, Infineon Technologies

12:00 Mittagessen/Postersession

13:00 Eingeladener Vortrag (siehe Seite 34) Moderator: Eckhard Hennig, HS Reutlingen

Improving Test Coverage and Eliminating Test Escapes Using Analog Defect Analysis

Walter Hartong, Art Schaldenbrand, Vladimir Zivkovic, Cadence Design Systems

13:45 Session 5: Synthese & Layout

Moderator: Jürgen Scheible, Robert Bosch Zentrum für Leistungselektronik, HS Reutlingen

On Applying Pareto Optimization for Complete Performance Space Modeling of Analog ICs

David Schreiber, Jürgen Kampe, Ernst-Abbe-Hochschule Jena

Template-Driven Analog Layout Generators for Improved Technology Independence

Benjamin Prautsch, Uwe Hatnik, Uwe Eichler, Fraunhofer IIS/EAS Dresden, Jens Lienig, TU Dresden

Automatic Analog-on-top Chip-Level Sche-matic Generation Based on Wire-by-Name Methodology

Jürgen Wittmann, Carsten Wegener, Fabio Rigoni, Dialog Semiconductor GmbH

14:45 Kaffee

■ Freitag, 14. September 2018

15:15 Session 6: Licht & Zufall

Moderator: Helmut Gräb, TU München

Design of an Automotive Visible Light Com-munications Link Using an Off-The-Shelf LED Headlight

Stephan Kruse, Christian Kress, Heinz Nixdorf Institut Universität Paderborn, Claas Tebruegge, HELLA GmbH & Co. KGaA, Agon Memedi, Muhammad Sohaib Amjad, Christoph Scheytt Falko Dressler, Heinz Nixdorf Institut Universität Paderborn

Ringoszillator-basierender Ultra-Low-Power-Zufallszahlengenerator für passive UHF RFID Transponder

Georg Saxl, Manuel Ferdik, Thomas Ußmüller, Universität Innsbruck

On-Line Parameter Extraction Technique for Integrated Circuits

Theodor Hillebrand, Konstantin Tscherkaschin, Steffen Paul, Dagmar Peters-Drolshagen, Univer-sität Bremen

16:00 Schlusswort Helmut Gräb, Technische Universität München

16:15 Ende der Tagung

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■ ANALOG 2018 – Poster

Poster

Session 1: Sensoren

P1.1 Enhanced Behavioral Models of MEMS Ele-ments for the System Level Verification

Tino Blochmann, Stephan Gerth, Peter Schneider, Roland Jancke, Fraunhofer IIS/EAS Dresden

P1.2 Effizientes Design und Layout von 3D-Be-schleunigungssensoren mittels automatisier-ter Synthese

Steffen Michael, Maria Kellner, Ralf Sommer, IMMS GmbH

P1.3 Online Surveillance Techniques for Reliable Active Pixel Sensor Systems

Theodor Hillebrand, Konstantin Tscherkaschin, Sebastian Schmale, Steffen Paul, Dagmar Peters-Drolshagen, Universität Bremen

P1.4 Entwurf und Implementierung eines Sensor-netzwerks zur Baustellensicherung mittels LPWAN

David Krönert, Kai Hahn, Universität Siegen, Helmut Kremer, micro-part GmbH&Co.is.KG, Gunnar Monheimius, TAMMET Systems International GmbH

P1.5 Ein integrierter Schaltkreis zur chronischen Aufnahme von Hirnsignalen bei neugebore-nen Mäusen

Andreas Bahr, Universität Kiel

■ ANALOG 2018 – Poster

Session 2: ADC, DAC, PLL und mehr

P2.1 Einfluss der Taktratensteuerung auf die Ge-nauigkeit asynchroner ADCs

Pavol Pitonak, Dirk Killat, Haoran Zhu, BTU Cottbus-Senftenberg

P2.2 Induktive Vernetzung von Hörgeräten Jan-Christoph Edelmann, Thomas Ußmüller,

Universität Innsbruck

P2.3 Akustische Übertragung medizinischer Daten über die Sprechanlage eines MRT

Viktoria Kalpen, Thomas Ußmüller, Universität Innsbruck

P2.4 UHF-RFID-Lesegerät basierend auf der NI PXIe Plattform

Manuel Ferdik, Markus Samuel Hesche, Lars-Oliver Rack, Georg Saxl, Thomas Ußmüller, Universität Innsbruck

Session 3: Verifikation, Simulation, Modelllierung

P3.1 Fehlersuche innerhalb des μ-Controllers vom Typ PIC32MX

Farouk Babba, Sebastian Sattler, Friedrich-Alexan-der Universität Erlangen-Nürnberg

P3.2 Transistor-Level Simulation of LC-tank VCO Electron Spin Resonance Detectors

Anh Chu, Benedikt Schlecker, Jens Anders, Universität Stuttgart

P3.3 A Hierarchical Method to Perform IR Drop and Electromigration Analysis for Faster Tape-out of Analog-on-top Designs

Tarjina Islam, Infineon Technologies AG

P3.4 Modeling of Delta-Sigma Modulators for Low-Power Audio Applications

Ciana Barretto, Elmar Herzer, Akshay Agashe, Johann Hauer, Fraunhofer-Institut für Integrierte Schaltungen IIS Erlangen, Mirco Meiners, Hoch-schule Bremen

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■ ANALOG 2018 – Poster ■ ANALOG 2018 – Poster

Session 4: Advanced CMOS

P4.1 Theoretical Derivation of Bandwidth Limits of a Symmetric Acoustic-Wave Lumped-Ele-ment Resonator (AWLR) Module

Michael Wagner, Friedrich-Alexander Universität Erlangen-Nürnberg, Stephan Leuschner, Intel Deutschland GmbH, Robert Weigel, Amelie Ha-gelauer, Friedrich-Alexander Universität Erlangen-Nürnberg

P4.2 Design of an EMC-Improved Regulated Charge Pump in 180-nm CMOS Technology

Dirk Nuernbergk, Christian Lang, Viktor Petri, Michael Frey, Melexis GmbH

P4.3 Considerations on the Design Methodology for an Integrated Gate Driver

Norbert Fiebig, Gunter Fischer, Pylyp Ostrovskyy, Dietmar Kissinger, IHP GmbH Leibniz-Institut für innovative Mikroelektronik

P4.4 Ultra-Low-Power Self-Biased 1 nA Current Reference Circuit for Medical Monito-ring Devices in 350 nm and 180 nm CMOS Technology

Gayas Mohiuddin Sayed, Pablo Mendoza-Ponce, Wolfgang Krautschneider, Matthias Kuhl,Technische Universität Hamburg-Harburg

P4.5 Content-Addressable Memory – Trends and Outlook of an Enabler for Modern-Day Appli-cations

Xin Fan, Amgad Ghonem, Tobias Gemmeke, RWTH Aachen

P4.6 A CMOS Bidirectional -69 mA to +63 mA Output Range Voltage-Controlled Current Source for Laser Diode Current Control in FTTx Applications

Sreekesh Lakshminarayanan, Jing Ning, Klaus Hofmann, TU Darmstadt

Session 5: Synthese & Layout

P5.1 Entwurf von zeitkontinuierlichen Sigma-Delta Modulatoren mit www.sigma-delta.de

Johannes Wagner, Maurits Ortmanns, Universität Ulm

P5.1 Parallelization Strategies for the Detailed Routing Step

Björn Bredthauer, Markus Olbrich, Erich Barke, Leibniz Universität Hannover

P5.3 A Procedural Approach to Automate the Manual Design Process in Analog Integrated Circuit Design

Florian Leber and Jürgen Scheible, Robert Bosch Zentrum für Leistungselektronik, HS Reutlingen

P5.4 Design Methodologies and Co-Design Options for Novel 3D Technologies

Tilman Horst, Robert Fischbach, Jens Lienig, TU Dresden

Session 6: Licht & Zufall

P6.1 Methoden zur Verbesserung von CMOS inte-grierten Arbiter-PUFs

Andreas Herkle, Joachim Becker, Maurits Ortmanns, Universität Ulm

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■ ANALOG 2018 – Panel

Panel: The Design Productivity Gap has been Growing for 20 Years – Who Cares?

The costs for the development of mixed-signal circuits have increased enormously for years. The development metho-dology is actually still like 20 years ago. Most of the aca-demic papers are about smaller, better and faster circuits. Hardly anyone ever imagines how to develop a circuit of certain complexity with half the effort. Although the metho-dology papers address some efficiency issues, their practi-cal implementation is lacking.“ (Anonymous)

This panel will discuss if this is statement is (still) valid, and if yes, why it is valid and if remedy is close. Where are the gaps and needs of AMS system design in details, what can EDA do now and in future?

Panelists:

Dave Reed is director of marketing for custom design tools at Synopsys. He has been involved in IC design and elec-tronic design automation for more 30 years, with a focus on analog and cus-tom design. He joined Synopsys through the acquisition of SpringSoft. Before SpringSoft, Dave was co-founder and

CEO of Blaze DFM, which helped customers overcome de-sign challenges of advanced process nodes. Prior to Blaze Dave was VP of Marketing at Monterey Design. Dave holds a BS in Electrical Engineering from Lehigh University.

Klaus Cerny studied Electrical Enginee-ring at the University of Applied Science in Augsburg and Economics at the Uni-versity of Hagen.

He is with Cadence since 2006 and in his role as Senior Account Manager

Technology he overviews the EDA development trends and market needs in the Custom IC design space.

Before joining Cadence he held various IC design and pro-ject management positions for LCD TV/Monitor products in Philips Semiconductor and Server Systems in Siemens Nixdorf AG.

Vadim Issakov was born in the Russian Federation in 1981

He received M.Sc. degree (cum laude) in microwave engineering from the Techni-cal University of Munich and Ph.D. de-gree from the University of Paderborn, Germany (summa cum laude) in 2006

and 2010, respectively.

He is a principal engineer for mm-wave circuit design at Infineon Technologies AG in Neubiberg, Germany. He is a technical lead of a research group working on mm-wave circuit design in CMOS and SiGe technologies for radar and communication applications.

Dietmar Kissinger (S’08–M’11–SM’14) received the Dipl.-Ing., Dr.-Ing. and habil. degree in electrical engineering from FAU Erlangen-Nürnberg, Germany, in 2007, 2011 and 2014, respectively.

From 2007 to 2010, he was with Da-nube Integrated Circuit Engineering,

Linz, Austria, where he worked as a System and Applica-tion Engineer in the Automotive Radar Group. From 2010 to 2014, he held a position as Lecturer and Head of the Radio Frequency Integrated Sensors Group at the Insti-tute for Electronics Engineering, Erlangen. Since 2015, he has been a Full Professor at the Technische Universi-tät Berlin and the Head of the Circuit Design Department at IHP, Frankfurt (Oder). His current research interests in-

■ ANALOG 2018 – Panel

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■ ANALOG 2018 – Panel ■ ANALOG 2018 – Panel

clude silicon high-frequency and high-speed as well as low-power integrated systems for communication and automotive, industrial, security and biomedical sensing applications. He has authored or co-authored over 250 technical papers and holds several patents.

Dr. Kissinger is a member of the European Microwave As-sociation (EuMA) and the German Information Technology Society (ITG) and Society of Microelectronics, Microsystems and Precision Engineering (VDE/VDI GMM). He currently serves as a member of the technical program committee of the European Solid-State Circuits Conference (ESSCIRC), a member of the technical program committee of the IEEE MTT-S International Microwave Symposium (IMS), and as the Chair of the Executive Committee of the IEEE Radio and Wireless Week (RWW). He was a two-time Chair of the IEEE Topical Conference on Wireless Sensors and Sen-sor Networks (WiSNet) and a two-time Chair of the IEEE Topical Conference on Biomedical Wireless Technologies, Networks and Sensing Systems (BioWireless). He further served as a member of the 2013 and 2017 European Mi-crowave Week (EuMW) Organizing Committee and as member of the 2018 IEEE MTT-S International Microwave Symposium (IMS) Steering Committee. He was a nine-time Guest Editor for the IEEE Microwave Magazine and served as an Associate Editor for the IEEE Transactions on Micro-wave Theory and Techniques. He was the Chair of the IEEE MTT-S Technical Committee on Microwave and Millimeter-Wave Integrated Circuits (MTT-6) and is currently an elected member of the IEEE MTT-S Administrative Committee. He received the 2017 IEEE MTT-S Outstanding Young Engi-neer Award, the 2017 VDE/VDI GMM-Prize, and was the co-recipient of nine best paper awards.

Ulrich Nerz was born 1957 in Reutlin-gen, Germany and has more than 30 years of experience in semiconductor development in Siemens and Infineon.

He started in the EDA department to in-troduce first P&R tools, develop libraries and RAM-generators to support the

change from full custom to semicustom design.

In 1994 he changed to Microcontroller development being responsible for the 16 bit product development for automo-tive and industrial applications

In the years that followed he held various management positions in Microcontroller R&D.

Since 2010 he has been one of the key persons being res ponsible for the development of Infineon’s 32bit AURIX Microcontroller family which is successfully used in many car applications such as power train, chassis, safety and autonomous driving.

Moderator:

Klaus Hofmann is a full professor at TU Darmstadt holding a Dipl.-Ing. Degree in Electrical Engineering (1992) from Ruhr-University Bochum, Germany, and recei-ved the Ph.D.degree from TU Darmstadt in 1997. From 1998 to Feb. 2009 he was with Siemens AG, Infineon Technologies AG and Qimonda AG in various positions

(last position: director product development), such as lea-ding the “Advanced Technology Software” and a product development department designing DDR-DDR3 DRAM products ranging from90nm downto 65nm technologies. From 2009 on he is heading the Integrated Electronic Systems Lab of TU Darmstadt as full professor with re-search interests in Analog and Digital Integrated Circuits and Systems, Integrated High Voltage Circuits, Application of Integrated Circuits in robust environments (Industrie 4.0, Infrastructure, FAIR) and Printed Electronics.

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■ ANALOG 2018 – Invited Talks

Cognitive Sensing: What Does this Mean for Us?

Presenter: Josef Sauerer, Fraunhofer-Institute for Integrated Circuits IIS, Erlangen

In many today’s applications we have smart or intelligent sensors, more complex systems comprising the primary sensing element, analog circuitries i.e. for excitation con-trol, compensation and analog signal conditioning, analog-to digital converter, digital information processing and di-gital communication interface. They often provide support for various modes of operation and interfacing and can take some predefined actions or calculations. Smart sen-sors can locally extract information from measured input data and transmit the information when necessary, thus reducing network requirements and complexity of central processing units. Cognitive sensors deploy a number of dif-ferent input values for acquiring situated information of the sensed environment. They are equipped with additional ca-pabilities based on machine learning processes. This enab-les cognitive sensors to build up empirical knowledge from their environment. They can work out particular patterns and trends from the signals. Cognitive sensor systems do not just capture measurement values. They analyze them directly, take decisions locally by intelligent interpretations and decide when it is necessary to pass on information or to trigger actions locally.

Thus, cognitive sensing extends »intelligent sensors« by employing sensor fusion and machine learning approaches to solve complex sensing tasks and to bring sensed infor-mation in a context.

This presentation will give examples of how cognitive sen-sor systems enable digital transformation to be realized in different application areas: Self-learning approaches can extend possibilities in magnetic position sensing; multimo-dal sensor fusion combined with machine learning based data evaluation helps properly brushing teeth, analyzing a driver’s emotions or even enabling a digital representation of human sensory perceptions.

Josef Sauerer received his diploma in electrical engineering from Friedrich Alexander University Erlangen Nurem-berg in 1985.

He started his professional career as analog IC designer at the Fraunhofer Institute for Integrated Circuits IIS in

Erlangen. For some years he was leading a group desig-ning fast analog-to-digital converters in III/V technologies. In 1993 he became head of the department for analog IC design with main focus on development of mixed signal ASICs for industrial and automotive applications. For some years he was responsible for all IC-design activities at Fraunhofer IIS covering CMOS integrated sensor systems, RF-ICs, mixed signal ICs and digital Ics.

Currently Josef Sauerer is heading the division of Smart Sensing and Electronics comprising IC design, optical and hall-sensor systems, imaging systems and medical tech-nologies.

■ ANALOG 2018 – Invited Talks

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■ ANALOG 2018 – Invited Talks

Current Sensing Circuits and Applications

Presenter: Misha Ivanov, Texas Instruments Deutschland GmbH, Freising

Today, we need to measure current everywhere. In most, if not all electrical systems, it is a key part of managing power. However, the requirements to the measurement of current have vast variation. We need to sense leakages in micro-amps, get to full scale in 100’s of amps, at speed up to 1MHz and the potentials of the current conductor that jump from 0V to 600V in <10ns.

Today not any one solution can do it all. The industry crea-ted a number of technologies and circuit topologies that are used in current sensing. These include magnetic field sensors measuring down to nano-Tesla; shunts with only a few micro-ohms; signal amplifiers with offset less than 1 microvolt; high-voltage isolation ICs sustaining surges up to 12000V.

This presentation will attempt to provide an overview of system and circuit approaches used to solve the main chal-lenges in several key applications. We will cover the topolo-gies for precision measurements, solutions to high voltage, common-mode transient immunity, and sensing very high and very low currents.

Misha Ivanov holds an M.S.E.E. degree from Ohio State University and has been with Burr-Brown and Texas Instruments since 1997, first in Arizona and from 2001 in Germany.

Misha has designed precision linear and mixed signal amplifiers, sensor conditio-

ning circuits and delta-sigma modulators.

He holds sixteen patents and was elected TI‘s Senior Member of Technical Stuff.

He currently leads a precision ADC design team, focusing on isolated delta-sigma modulators and amplifiers.

■ ANALOG 2018 – Invited Talks

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■ ANALOG 2018 – Invited Talks

Behavioural Modeling for SoC Simulation: Bridging Analog and Firmware Demands

Presenter: Rainer Findenig, Gabriel Rutsch, Infineon Tech-nologies AG

Simulating today’s SoC models requires fast models of the digital part, the compute platform, and the analog part, in order to be able to efficiently run application software in the simulation.

While abstraction for digital models is well understood, our experience shows that today, the most critical issues are with analog models.

A sensible abstraction is required to achieve models that include all relevant details with the required accuracy, yet still provide the simulation performance required for SoC and firmware verification. At the same time, to reduce de-velopment costs, additional focus needs to be placed on maintainability and reusability. In this talk, we show how we addressed this challenge for different SoCs developed at Infineon.

Rainer Findenig received his diploma from the Upper Austrian University of Applied Sciences in Hardware/ Software Systems Engineering in 2007 and his PhD from Johannes Kepler University Linz in 2016.

His PhD research was focused on code generation for efficient models of digital hardware for virtual prototyping.

He joined Infineon in 2016 and is currently in charge of virtual prototype development for Infineon’s high-end Radar Ics.

Gabriel Rutsch received an MSc degree in Electrical and Computer Enginee-ring from Technical University Munich in 2015.

Since then he has been working for Infi-neon Technologies AG as methodology development and system level design

engineer.

His specific field of activity is the methodology development for AMS system modeling and emulation.

■ ANALOG 2018 – Invited Talks

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■ ANALOG 2018 – Invited Talks

Competitive CMOS RF Transceiver Design

Presenter: Timo Gossmann, Jakob M. Tomasik, Intel Deutschland GmbH, Munich

The evolution of modern systems for cellular communi-cation started with GSM is currently moving towards 5G. This is also reflected in the evolution of Intel’s SMARTi(TM) transceiver ICs. Since starting in 2000, our SMARTi-pro-duct family has seen a significant transformation in techno-logy, architecture, die size, supported bands and features. To keep pace and to cope with these ever increasing demands, our development process had to be adapted and optimized, new methodologies and tools had to be developed and very different engineering mindsets had to be aligned. This does not end now, next generation RF transceivers will set even more demanding challenges to comply with requests to meet more stringent KPIs.

In this talk, we will give an impression about the comple-xity of a state of the art cellular transceiver chip. We will show what kind of engineering resources and disciplines (e.g. analog, digital, RF and software design) are involved and why their tight cooperation is necessary to map the extremely complex requirements to a successful product operated in modern cellular phones.

Timo Gossmann received his diploma in electrical engineering from TU Darm-stadt in 1995.

As student he was working at Panaso-nic and worked on the first 100Hz digital signal processing chip sets and started his professional career at SIEMENS

semiconductor in Munich when Microelectronics was still on um-scale.

Joining embedded DRAM product design group, he was designing full custom and semicustom digital circuits and more ‘analog’ blocks like IO drivers.

Lacking some required ingredients for the assigned work packages, he became also involved in synthesis library development and design flow topics.In 1997 he joined SIEMENS semiconductor RF design group, extending his CMOS/digital-centric expertise towards BiCMOS technolo-gies, RF- and mixed signal design.

After initially working on car radio applications, he soon transitioned to cellular product development, right before the SMARTi cellular RF transceiver product line activities were started.

Since then he actively contributed to design and producti-zation of many SMARTi versions throughout the years with SIEMENS, Infineon and currently Intel.

He also e also held several technical lead and line manage-ment positions in Germany and several foreign countries and is currently leading the transmitter sub-project in the next ramping high volume product.

Jakob M. Tomasik received his diploma and his PhD degree from the Hamburg University of Technology (TUHH) in 2004 and 2010, respectively.

His PhD topic was focused on the re-search of low-noise and low-power ana-log circuits for biomedical applications.

From 2010 to 2013 he worked as an R&D engineer at EPCOS GmbH & Co. KG, Duisburg, on automotive and industrial microcontroller solutions. In 2013, he joined Intel Deutschland GmbH in Duisburg where he was responsible for the design of RF circuits for cellular products.

Since 2017 he is a team lead for RF circuit design at Intel in Munich.

■ ANALOG 2018 – Invited Talks

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■ ANALOG 2018 – Invited Talks

Design Challenges and Methodology Considerations for Highly-Integrated mm-Wave Systems in Silicon- Based Technologies

Presenter: Vadim Issakov, Infineon Technologies, Neubiberg

The recent advances in silicon-based semiconductor pro-cesses and packaging technologies enable high-level in-tegration of system on chip (SoC) and system in package (SiP) solutions for millimeter-wave (mm-wave) communi-cation or radar applications. These solutions find growing interest due to the increasing demand for a lowest bill of materials. The amount of external components shall be re-duced by integrating more and more analog, digital, power management and RF functional blocks on the same chip, on a smallest chip area and at a lowest price. The demon-stration of Silicon-Germanium (SiGe) HBT or even CMOS integrated transceiver circuits at millimeter-wave frequen-cies has given rise to the sales volumes of classical and emerging applications.

This talk focusses on design considerations of highly-integrated mm-wave transceiver chipsets in silicon-based technologies. The speaker will discuss circuit design consi-derations and challenges related to critical building blocks. Particularly, high sensitivity of key performance parameters to layout parasitics at mm-wave frequencies is discussed. Additionally, challenges related to accurate extraction of pa-rasitics are addressed. Next, chip-package-PCB co-design and co-simulation methodology by means of accurate EM modelling for RF systems is presented. Furthermore, cros-stalk mechanisms related to coupling between integrated inductors/transformer and coupling via substrate at mm-wave frequencies are discussed. Finally, examples of mm-wave radar and communication systems at frequencies above 60 GHz are presented.

Vadim Issakov was born in the Russian Federation in 1981

He received M.Sc. degree (cum laude) in microwave engineering from the Techni-cal University of Munich and Ph.D. de-gree from the University of Paderborn, Germany (summa cum laude) in 2006

and 2010, respectively.

He is a principal engineer for mm-wave circuit design at Infineon Technologies AG in Neubiberg, Germany. He is a technical lead of a research group working on mm-wave circuit design in CMOS and SiGe technologies for radar and communication applications.

■ ANALOG 2018 – Invited Talks

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■ ANALOG 2018 – Invited Talks ■ ANALOG 2018 – Invited Talks

Improving Test Coverage and Eliminating Test Escapes Using Analog Defect Analysis

Presenter: Walter Hartong, Art Schaldenbrand, Vladimir Zivkovic, Cadence Design Systems

Complex systems, like cars or planes, consist of thousands of sub components. If a single sub-block fails, the whole system is at risk. Consequently, the system integrators have a 0-defect goal for the sub components. How can IC companies achieve this level of quality? While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of analog centric tools to analyze the test coverage during design has made it difficult for designers to address the issue. More-over, manufacturing test is a critical step to ensure quality. Test costs make up a significant portion of the die recurring cost and is directly proportional to the time spent on the tester. This demands more attention on optimizing the test program and testability early in the design cycle.

Analog fault simulation has been proposed for many years but the technology has not proliferated much so far. The lack of analog fault models and a standard methodology have proved to be a challenge when trying to evaluate test coverage. The solution has been to refine the problem. Instead of starting with hard to define analog faults, manu-facturing defects are modelled and their effect on the cir-cuit is simulated. Defect-oriented test evaluates the ability of the test program to identify and eliminate manufacturing defects. Currently the IEEE P2427 Working Group is stan-dardizing this methodology and new tools and simulation environments – like Cadence® Legato™ Reliability Solution – become available commercially.

Moving forward the related functional safety question will in-fluence the analog working environment significantly.above 60 GHz are presented.

Walter Hartong studied Electrical Engi-neering/Microelectronics at the Universi-ty of Hannover.

He worked as a research assistant at the Institute of Microelectronic Systems and finished his PhD in Computer Science in 2002.

Since 2002, he has been with Cadence Design Systems in Munich, initially as application engineer. His current role is Product Engineering Architect focusing on analog simulati-on environment and verification.

He is one of the core drivers in the ADE Verifier develop-ment and contributes to Explorer and Assembler as well. Walter is also interested in mixed-signal topics, analog fault simulation and behavioral modeling.

Art Schaldenbrand

Vladimir Zivkovic

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Allgemeine Hinweise

Tagungsorganisation (Anmeldung)

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Die Anmeldung zur Fachtagung ANALOG 2018 erfolgt über den VDE-Konferenz-Service. Das entsprechende Anmelde-formular finden Sie auf der Homepage der Veranstaltung unter www.analog-fachtagung.de.

Dort können Sie sich auch online anmelden.

Ihren Tagungsausweis und Ihre Tagungsunterlagen erhalten Sie im Tagungsbüro vor Ort vor Beginn der Veranstaltung.

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Teilnehmer, die sich erst vor Ort anmelden, müssen damit rechnen, dass ihnen kein Tagungsband ausgehändigt wer-den kann.

Stornierung

Bei Stornierung bis zum 10.08.2018 wird die Teil-nahme-gebühr abzüglich € 50,- für Bearbeitungskosten zurücker-stattet. Bei Stornierung nach diesem Zeitpunkt kann eine Rückerstattung der Teilnahmegebühr nicht mehr vorge-nommen werden. Der Tagungsband wird dann nach der Veranstaltung zugesandt. Es ist jedoch möglich, einen Er-satzteilnehmer zu benennen.

Telefonische Erreichbarkeit während der Tagung

Ab 13.09.2018 befindet sich das Tagungsbüro in München/ Neubiberg.

Das Tagungsbüro erreichen Sie dann unter

Tel.: 0171 4695 118 (Dr. R. Schnabel).

Tagungsort

Mittwoch, 12. September 2018:

Tutorials am Stammgelände der TU München, Arcisstr. 21, 80333 München,Seminarraum 2999

Navi: Arcisstraße 21, München, oder Theresienstraße 90, München, eingeben

Öffentlicher Nahverkehr: U2 Haltestelle Theresienstraße

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Lagepläne in verschiedenen Maßstäben zur Lokalisierung des Seminarraums finden Sie auf der Homepage der Ver-anstaltung www.analog-fachtagung.de unter der Website „Veranstaltungsort“

ANALOG-Tagung bei Infineon am Donnerstag und Frei-tag, 13. - 14. September 2018:

Infineon, Am Campeon 1-12, 85579 NeubibergKonferenzzone im Gebäude 02

Navi: Am Campeon 1-12, Neubiberg bei München

Öffentlicher Nahverkehr: S3, Haltestelle Fasanenpark (ACHTUNG: nicht verwechseln mit vorheriger/nächster Haltestelle Fasanengarten)

Anfahrtshinweise zu Infineon finden Sie auf der Homepage der Veranstalutng unter www.analog-fachtagung.de unter der Website „Veranstaltungsort“

Zimmerreservierungen

Die Unterkunft ist nicht Teil der Konferenzregistrierung.

Hotelbuchungen können über die üblichen Reiseportale vorgenommen werden.

Wegen des anschließenden Oktoberfests (22.09.-09.10.2018) wird dringend empfohlen, frühzeitig zu buchen.

Hotels in der Nähe des Konferenzorts Campeon (Infineon, Am Campeon 1-12, 85579 Neubiberg), sind beispielsweise:

• Holiday Inn München-Unterhaching Inselkammerstraße, 282008 Unterhaching Tel.: 089 66 69 10 info@holiday-inn-muenchen.de Einzelzimmer pro Nacht € 130.- 5 km Entfernung zum Campeon 25 Min. mit den ÖPNV zum Campeon

• nh-Hotel München Unterhaching Leipziger Straße, 82008 Unterhaching Tel.: 089 99 34 56 77 reservations.muenchen@nh-hotels.com Einzelzimmer pro Nacht € 130.- 2 km Entfernung zum Campeon 15 Min. mit den ÖPNV zum Campeon

Weitere Hotelempfehlungen in München:

• Leonardo Hotel & Residenz München Heimgartenstr. 14, 81539 München Tel.: 089 62 03 90 info.muenchenresidenz@leonardo-hotels.com Einzelzimmer pro Nacht € 115.- 10 km Entfernung zum Campeon 20 Min. mit den ÖPNV zum Campeon

• Derag Livinghotel am Deutschen Museum Rabistraße 10, 81669 München Tel.: 089 45 83 00 res.amdeutschenmuseum@derag.de Einzelzimmer pro Nacht € 110.- - 160.- 10 km Entfernung zum Campeon 20 Min. mit den ÖPNV zum Campeon

• Novotel München City Hochstraße 11, 81669 München Tel.: 089 66 10 70 h3280@accor.com Einzelzimmer pro Nacht € 340.- 11 km Entfernung zum Campeon 20 Min. mit den ÖPNV zum Campeon

• Holiday Inn München - City Centre Hochstraße 3, 81669 München Tel.: 089 48 03 44 44 postoffice@muchb.holidayinn.com Einzelzimmer pro Nacht € 180.- - 205.- 11 km Entfernung zum Campeon 20 Min. mit den ÖPNV zum Campeon

Abendveranstaltung

Dienstag, 13.09.2018, 20:00 Uhr

Donisl – Traditionswirtshaus am MarienplatzWeinstraße 2, 80333 München Tel. 089 2429 39-0www.donisl.com

Für die Abendveranstaltung der ANALOG 2018 haben wir das Traditionswirtshaus Donisl ausgewählt, direkt im Herzen von München.

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