AN2408/D: Examples of HCS12 External Bus Designkxc104/class/cse472/09f/lec/HCS12... · Examples of...

Freescale SemiconductorApplication Note

AN2408/DRev. 2, 8/2004

Examples of HCS12 External Bus DesignA Companion Note to AN2287/D

By Jim Williams8/16 Bit Products DivisionApplications Engineering

Introduction

The examples in this application note are intended to supplement the content of AN2287/D: HCS12 External Bus Design. Use these examples to assist your understanding of the concepts detailed in AN2287.

There are two significant advantages of the external bus interface on the HCS12 Family of MCUs:

• The ability to run the external bus at full speed without sacrificing performance when in emulation environments or accessing external devices.

• The incorporation of internal visibility capability. The IVIS function allows real-time internal bus functionality to be monitored externally. System designers should consider this capability in their overall system design because it allows dramatic improvement in software development and debug capability, improving overall time to market.

The high-performance of this MCU family presents challenges when designing external interfaces that operate at maximum bus speed. In-depth knowledge of the system performance requirements and experience in high-speed buses, transmission lines, and analog design are necessary in order to understand and create a successful system.

This application note primarily uses random access memory (RAM) in the design examples because of its speed and well-known architecture. It also provides information necessary to implement other architectures.

© Freescale Semiconductor, Inc., 2004. All rights reserved.

This product incorporates SuperFlash technology licensed from SST.

Example #1 — Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated

Precepts

These precepts apply to all the following examples:

• In some of the designs, there is no data buffer. These designs assume that the VOH levels of the external device match those of the MCU. Do not attempt to use resistive pull-up devices on a fast high-capacitance bus to match I/O levels. With high-speed static memories, a data buffer may be required to interface with a 5 V powered MCU. Verification of the external device’s VOH levels is required. Lower voltage MCUs may not require a bus buffer. High-speed SRAM with tEHOZ < 8 ns must be used to ensure that the SRAM bus is three-state prior to the next MCU address drive.

• The MCU reset signal is not gated with the SRAM selects. This does not present a problem in these designs because the external bus (and consequently the external device) will be “off line” during reset. During the power-up sequence, external devices may become active before the MCU. In some modes, the MCU’s ECLK will start up prior to the release of reset while the R/W signal is still low, causing external memory corruption. Some designs, especially emulation systems, may require gating with reset.

• There will be occasional bus contention in these designs if the IVIS bit in the MODE register is set, as the NOACC signal is not implemented. Any MCU “free” cycle preceded by a data fetch could be interpreted as a valid external read access by the SRAM. Though this will not corrupt external memory, it will increase power consumption.

• Address decoding is implemented to ensure writes to replaced ports (A, B, E, K) and their configuration registers do not corrupt SRAM locations. Errant writes to these registers will be echoed externally for possible port replacement and may cause external memory corruption. If software is configured to protect against errant accesses, the decode is not necessary.


The following schematic is one of the simplest examples of HCS12 interfacing. A small 8-bit wide SRAM device is attached to the external bus in expanded narrow mode. This SRAM device could represent the interface of other devices with small memory-mapped or byte-oriented I/O.

Comments:

• It is assumed that the memory area from $4000–$7FFF is clear of internal FLASH by setting the ROMHM bit in the MISC register.

• The active-high chip-enable signal that is available on these low-density SRAMs is important to the design, because the ECLK signal is used as the enable to signal the completion of access to the SRAM. If MCU signals that are gated with logic are used, the MCU data may be released before these gated control signals negate, causing SRAM data corruption.

• The ‘374 type latch and the SRAM access speed will require at least one additional MCU clock stretch to access these devices or reduced MCU speed.

• Memory is available from $4000–$5FFF.

Examples of HCS12 External Bus Design, Rev. 2

2 Freescale Semiconductor


Figure 1. Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated

Figure 2 is a logic analyzer trace showing the narrow mode access. It was generated by a word access to the external memory space configured in narrow mode. Notice that the MCU automatically breaks the write into two appropriate byte accesses and that the R/W signal is not negated.

PA1 MCU ADDR[10]

MCU ECLK

PA7

PA3

MCU ADDR[4]

PB7

MCU ADDR[1]PA1

PB5

DATA[7]

MCU ADDR[3]

PA0

MCU ADDR[12]

MCU ADDR[15]

U4C74FCT00

9

108

U4A74FCT00

1

23

PB4

DATA[6]

PA0

PA2

MCU R/W

PB2

MCU ADDR[11]

DATA[4]

MCU ADDR[2]

PB3

MCU ADDR[8]

PA4

DATA[2]

PB6

PE2

U2

74FCT374

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

PA5

U4B74FCT00

4

56

MCU ADDR[7]

MCU ADDR[9]

MCU ADDR[14]

DATA[0]MCU ADDR[0]

WE*

PB0

PA3

DATA[1]

PA6

PA7

MCU ADDR[6]

PE4

OE*

DATA[3]

U3A

74FCT139

23

1

4567

AB

G

Y0Y1Y2Y3

MCU ADDR[5]

PA2

DATA[5]

PA6

PA5MCU ADDR[13]

U1

6264/S0

109876543

25242123

2

2026

2227

1112131516171819

A0A1A2A3A4A5A6A7

A8A9A10A11A12

CS1CS2

OEWE

D0D1D2D3D4D5D6D7

PB1

PA4


Freescale Semiconductor 3


Figure 2. Byte-Wide SRAM Interface (Word Write $AAAA) as Two Access Cycles



Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated


The following schematic demonstrates the interface of two 8-bit SRAMs to provide word access to the external memory interface. It uses expanded wide mode in order to support word (x16) access to the external device.

Comments:

• The least significant address line is used to implement byte access to the word wide memories. The MCU’s LSTRB signal and the ADDR[0] signals are used to select high and low byte access to the external devices. If this is not required (as in the case of read only memory), these signals are not needed.


• Memory is available from $4000–$7FFF.

Figure 3. Word-Wide SRAM Interface (Wide Mode) ECLK Gated

The following figures are logic analyzer traces showing the wide mode access available. The Figure 4 was generated by a word access to the external memory space configured in wide mode. Figure 5 is an even byte access, and Figure 6 is an odd byte access. Notice the behavior of the ADDR0 and LSTRB signals that control the byte accesses.

ADDR[10]

$4000

OE*

PB5

ADDR[1]

PB3

ADDR[5]

DATA[5]

ADDR[12]

PA0

PA3

PA1

PE2

DATA[1]

ADDR[4]

ADDR[6]

DATA[8]

PE4

ADDR[11]

MCU ADDR[8]

ADDR[5]

PA1

PA5

PA6

PA4

ADDR[3]

DATA[12]

DATA[7]

ADDR[4]

ADDR[2]

DATA[2]

PA6

ADDR[2]

PA2

MCU ADDR[0]

ADDR[12]

ADDR[10]

ADDR[13]

ADDR[7]

ADDR[12]

MCU ADDR[7]

U9C

74FCT374/SO

9

108

PB2

PB2

PB4

PA5

ADDR[8]

DATA[4]

ADDR[7]

DATA[10]

MCU ADDR[6]

DATA[9]

DATA[13]

ADDR[5]

PA7

PB6

PB1

MCU ADDR[2]

PA4

MCU ADDR[4]

MCU ADDR[1]

ADDR[9]

ADDR[13]

MCU ADDR[11]

ADDR[1]

MCU ADDR[15]

ADDR[10]ADDR[11]

PB3

U9B

74FCT374/SO

4

56

U6

74FCT16374/SO

124

2548

2356891112

1314161719202223

4746444341403837

2627293032333536

1OE2OE

2CLK1CLK

1Q11Q21Q31Q41Q51Q61Q71Q8

2Q12Q22Q32Q42Q52Q62Q72Q8

1D11D21D31D41D51D61D71D8

2D82D72D62D52D42D32D22D1

ADDR[6]

U8A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

ADDR[7]

ADDR[0]

ADDR[11]

PA0

PB0

ADDR[3]

PB4

ADDR[3]

MCU ADDR[9]

DATA[3]

U8B

74FCT139A/SO

1413

15

1211109

AB

G

Y0Y1Y2Y3

PB6

MCU ADDR[12]

MCU ADDR[10]

MCU R/W

ADDR[6]

MCU ECLK

WE*

DATA[6]

U5

6264/SO

109876543

25242123

2

1112131516171819

22272026

A0A1A2A3A4A5A6A7A8A9A10A11A12

D0D1D2D3D4D5D6D7

OEWECS1CS2

PA3PB5DATA[11]

PB7ADDR[8]

U7

6264/SO

109876543

25242123

2

1112131516171819

22272026

A0A1A2A3A4A5A6A7A8A9A10A11A12

D0D1D2D3D4D5D6D7

OEWECS1CS2

DATA[14]

ADDR[15]

ADDR[4]

ADDR[9]

MCU ADDR[14] ADDR[14]

PB1

PB7

MCU ADDR[3]

ADDR[1]

U9A

74FCT374/SO

1

23

PB0

ADDR[2]

PA2

MCU ADDR[13]

MCU LSTRB

ADDR[9]DATA[15]

ADDR[13]

ADDR[8]

MCU ADDR[5]

PA7

PE3

DATA[0]




Figure 4. Expanded Wide Word Access ($1234)




Figure 5. Expanded Wide Even Byte Access ($AA)



Example #3 — Byte-Wide SRAM Interface with Paging

Figure 6. Expanded Wide Odd Byte Access ($55)


In the following schematic, a 128K SRAM device is attached to the external bus in expanded narrow mode. The design introduces the paging capability of the HCS12 Family. Eight 16K pages of RAM are added to the $8000–$BFFF window at page address $00–$07. Accesses to $20–$2F page will result in invalid external accesses.

Comments:

• The active-high chip-enable signal that is available on these SRAMs is important to the design, because the ELCK signal is used as the enable to signal the completion of access to the SRAM. If MCU signals that are gated with logic are used, the MCU data may be released before these gated control signals negate, causing SRAM data corruption.





Figure 7. Byte-Wide SRAM Interface with Paging

Figure 8 details memory implementation of Example #3. Notice the external memory will mirror from x to x + 8, x + 16, x + 24 pages, as only ADDR19 is used for decoding, and ADDR17 and ADDR18 are not implemented.

Figure 8. Memory Map of Figure 7

ADDR/DATA10

ADDR8

ADDR10

ECLK

ADDR13

0

ADDR/DATA12

ADDR16

1

1

ADDR/DATA12

PK4

ADDR/DATA3

WE

U10

74FCT821/SO

23456789

1011

1

13

23222120191817161514

D1D2D3D4D5D6D7D8D9D10

OE

CLK

Q1Q2Q3Q4Q5Q6Q7Q8Q9

Q10

ADDR/DATA8

ADDR9

0

U11

AS7C1024/SOJ

12111098765

272623254

283

312

1314151718192021

2230

2429

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

CE1CE2

OEWE

R/W

PA0

PA7

R/WXADDR19

ADDR/DATA6

XADDR14

PK3

ADDR/DATA9

PB0

PB4

ADDR/DATA14

XADDR15

0

ADDR8

1

XADDR19

ADDR/DATA1

ADDR12

ADDR/DATA10

ADDR14

U12A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

PB1

ADDR/DATA11

X

ADDR/DATA5

ADDR/DATA9ADDR/DATA0

ADDR/DATA10

ADDR9ADDR16

ADDR/DATA13

ADDR/DATA0

PB3

1

1

ADDR/DATA11

ADDR13

1

0

PK5

ADDR15

ADDR/DATA1

PK2

ADDR/DATA8

1

PK1

1

XADDR15

0

1 0

OE

XADDR16

ADDR/DATA5

ADDR11


XADDR16

PB6

1

ADDR12

ADDR/DATA12

1

ADDR/DATA15

ADDR/DATA2

ADDR/DATA4

XADDR19PA1

X1

ADDR10

PB5

01

PA2

XADDR14

ADDR/DATA9

0

ADDR/DATA13

ADDR/DATA15

ADDR/DATA11

ADDR14

0

ADDR11

0


PB2

GND

ADDR/DATA8

PA3

ADDR/DATA4

PA6

PK0

ADDR/DATA2

PA4PA5

ECLK

ADDR15ADDR/DATA14

ADDR/DATA3

PB7

03

0B

131B

External RAM

Memory Map

04

0C

141C

38 05

0D

151D

PPAGE39

Note: Shadow Pages

3A 3B 06

0E

161E

3C 07

0F

171F

3D30 3E31 3F32

3F

33 00

08

1018

0000

34 35 01

09

1119

36

FFFF

37

Internal Flash

02

0A

121A



Example #4 — Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated


The following schematic demonstrates the interface to a 8-bit SRAM to provide word access to the external memory interface. It uses expanded narrow mode in order to support byte (x8) access to the external device. It has the addition of logic to support additional banks of external memory.

Comments:

• The XCS or ECS signal is required because the external device does not possess the active-high chip-enable needed for using the ECLK signal to activate the external device. If the ECS signal is implemented, the ROMON bit must be clear, as internal memory has precedence over external memory. Because not all HCS12 Family members have the XCS signal, this design will not be applicable in all instances. The system designer should assess the overall design to determine applicability.

• This design introduces memory paging. An additional latch is provided to acquire the extended address lines XAD[19..14]. This latch is not required in all instances. The system designer should carefully study the device specifications and relevant errata to verify the system design.

• The ECS/XCS signals improve access time. Replacing the ‘374 type latches with a ‘373 transparent device allows the address to be presented to the memory device in advance of the rising ECLK edge. This enhancement and careful memory selection will allow higher speed access to the external device.




Figure 9. Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated


PA7

ADDR[7]

DATA[9]

PA3

ADDR[13]

1

XADDR[19]OE

PA0

PE2

MCU_XADDR[16]

DATA[8]

PB3

ADDR[9]

PA5

MCU_XADDR[18]

XADDR[16]

A to B

MCU ADDR[15]

PTK6/7

U15

74FCT16373/SO

23568911121314161719202223

47464443414038373635333230292726

2548

241

1Q11Q21Q31Q41Q51Q61Q71Q82Q12Q22Q32Q42Q52Q62Q72Q8

1D11D21D31D41D51D61D71D82D12D22D32D42D52D62D72D8

2LE1LE

2OE1OE

0

MCU ADDR[7]

B to A

XADDR[18]

ADDR[4]PB4

MCU ADDR[3]

1

PA0

U14

74FCT373/SO

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

0

PA1

DATA[11]

ADDR[12]

MCU_XADDR[17]

PA7

1

MCU ADDR[9]

0

PTK5

MCU ADDR[8]

DATA[13]

PA3

PA1

1

MCU ADDR[2]

1

PA6

ADDR[8]

PB2

MCU_XADDR[14]

1

MCU ADDR[4]

DATA[10]

MCU ADDR[11]

ADDR[0]

ADDR[15]

XADDR19

MCU ADDR[10]

PTK1

PB6

00

DATA[14]

PA4

MCU ADDR[1]

U17A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

1

ADDR[3]

MCU_XADDR[19]

PB5

1

ADDR[1]

PTK0

R/W1

1

MCU XCS

PTK4

PB0

DATA[12]

PA2

0

ADDR[2]

MCU ADDR[5]

A to B

1

WE

MCU ADDR[13]ADDR[14]

MCU ADDR[6]

PB1

PTK3

MCU ADDR[14]

ADDR[11]

0

A to B

MCU ADDR[12]PA4

X

A to B

MCU R/W

ADDR[5]

PA6

PE4MCU ECLK

XADDR[14]MCU_XADDR[15]

1

DATA[15]

10

ADDR[10]

DIR

PTK2 XADDR[17]

U16

AS7C4096/SO

12345

31

34

141516171820212223243233

35

136

78111225262930

A0A1A2A3A4

OE

A17

A5A6A7A8A9A10A11A12A13A14A15A16

A18

WECE

I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8

PA2

PA5

0

ECLK

ADDR[6]

MCU ADDR[0]

PB7

XADDR[15]

X0

FFFF

3F38

3E0C

11

37

1A

0F

3A

03 08

Memory Map

17

32 PPAGE3B35

01 06

Internal Flash

05

1B18

0E

3C

3F

04 09

16

33

15

39

10

0D

3D

0000

0702

14 19

0A00

36

0B

External RAM30

1E 1F13

3E34

1D12

31

1C




Figure 11 is a logic analyzer trace showing the narrow mode access with ECS gating. This word access is divided into two 8-bit accesses by the MCU. Notice that the ECS signal is negated between memory accesses.

Figure 11. Expanded Narrow Word Access with ECS/XCS

Figure 10 details memory implementation of Example #4. Notice the external memory will mirror from x to x +16 pages as this is an 8-bit memory and only ADDR19 is used for decoding

Figure 12 illustrates a sample timing analysis for Figure 9. It was generated with a commercially available timing tool.




Figure 12. Example Timing Analysis

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 S0 S1

EXTERNAL READ CYCLE EXTERNAL WRITE CYCLE EXTERNAL WRITE CYCLE INTERNAL CYCLE

tZtZtZtZtGHQZ

tGLQV

tAVQV

tELQV

tP:373

tP:373tP:373

tP:373tP:373

tP:373

tPtPtPtP

tRWD

tRWH

tRWHtRWD

tDHWtDDW

tMAH

tAD

tDHW

tDDW

tMAHtAD

tZtZ

tMAH

tAD

tCSHtCSD

tCSH

tCSD

tCSH

tCSD

tDSR

ADDR ADDR MCU DATA

RAM DATA

RAM DATA ADDR MCU DATA

MCU DATA MCU DATA

0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns

SYSCLK

ECLK

ECLK

ECS/XCS

ADDR/DATA

R/W

RAM_R/W

LATCHED_ADDR

RAM_DATA



Example #5 — Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated


The following schematic demonstrates the interface to a 16-bit SRAM to provide word access to the external memory interface. It uses expanded wide mode in order to support word (x16) access to the external device. It has the addition of logic to support additional banks of external memory.

Comments:


• This design introduces memory paging. An additional latch is provided to acquire the extended address lines XAD[19..14]. This latch is not required in all instances. The system designer should carefully study the device specifications and relevant errata to verify the system design.

• The ECS/XCS signals improve access time. Replacing the ‘374 type latches with a ‘373 transparent device allows the address to be presented to the memory device in advance of the rising ECLK edge. This enhancement and careful memory selection will allow higher speed access to the external device.

• U22 — (FCT139) may be replaced with NAND gate decoding, if an extra NAND is required for system design. See Figure 3 U9 — (FCT00) for implementation.

Figure 13. Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated

ADDR[6]

MCU ADDR[0]

XADDR[17]

PA7

PA4 ADDR[13]

PE2

MCU ECLK

MCU_XADDR[18]

PB0

PA4

DATA[14]

ADDR[1]

DATA[12]DATA[13]

PA0

DATA[6]

PTK4

PTK6/7

PB3

PA7

PA2

MCU ADDR[2]

MCU ADDR[11]

OE*

PB6PB7

MCU LSTRB

DATA[15]

ADDR[9]

$8000

DATA[8]

ADDR[2]

U18

74FCT373/SO

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

XADDR[16]

PB5

PA5PA3

ADDR[0]

MCU_XADDR[16]

DATA[11]

PB2

ADDR[14]

PTK0

PA6

PB1

U20

AS7C4098/SO

12345

617

39

4041

7891013141516

18192021222324252627

293031323536373842

4344

A0A1A2A3A4

CEWE

LB

UBOE

DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8

A5A6A7A8A9A10A11A12A13A14

DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQ16A15

A16A17

PB2

XADDR[14]

MCU ADDR[12]

MCU ADDR[6]

MCU R/W

PTK2

PA6

$8000

XADDR[18]

PA3

ADDR[10]

MCU ADDR[8]

DATA[2]

PTK5MCU_XADDR[19]

U19

74FCT16373/SO

23568911121314161719202223

47464443414038373635333230292726

2548

241



2LE1LE

2OE1OE

DATA[4]PB4

ADDR[7]

PA1

PB3

MCU ADDR[3]

PB4

PTK3

MCU_XADDR[14]

MCU ADDR[7]

MCU ADDR[5]

U21B

74FCT139A/SO

1413

15

1211109

AB

G

Y0Y1Y2Y3

PA2

PB0

MCU_XADDR[17]

DATA[10]

XADDR[15]

DATA[7]

MCU ADDR[4]

PTK1

XADDR[19]

ADDR[4]

MCU_XADDR[15]

DATA[5]

U22A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

ADDR[15]

DATA[9]

MCU ECS/XCS

PB6PB7

PE4

MCU ADDR[13]

MCU ADDR[15]

DATA[0]

MCU ADDR[9]

PA5

ADDR[12]

U21A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

PB5

ADDR[3]

PA0

PB1

ADDR[8]

MCU ADDR[1]

PE3

PA1

MCU ADDR[14]

DATA[3]

WE*

ADDR[5]

DATA[1]

ADDR[11]MCU ADDR[10]




Figure 14 is a logic analyzer trace showing expanded wide mode access with ECS gating. Notice that even though the clock stretching is enabled, significant reduction in access time is available, depending on SRAM access speed.

Figure 14. Expanded Wide Word Access with ECS/XCS


FFFF

3F38

3E0C

11

37

1A

0F

3A

03 08

Memory Map

17

32 PPAGE3B35

01 06

Internal Flash

05

1B18

0E

3C

3F

04 09

16

33

15

39

10

0D

3D

0000

0702

14 19

0A00

36

0B

External RAM30

1E 1F13

3E34

1D12

31

1C



Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated

Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated

The following schematic demonstrates the interface to a 16-bit FLASH memory device to provide word wide access. It uses expanded wide mode in order to support word access to the external device. It has the addition of logic to support additional banks of external memories.

Comments:


• Byte access is not required, as the MCU will ignore the unneeded byte of a word transaction. Therefore the LSTBR and ADDR0 signals are not implemented.

• This interface will not be able to run at full bus speed, as the access time of external FLASH memory has not reached the capabilities of internal memories. The HCS12 MCU supports as many as three additional clock stretch cycles to support interfaces to these devices.

• Data bus buffers will be required in this type of design due to the tEHOZ timing of current FLASH devices. They cannot three-state the data bus prior to the MCU next address access.

Figure 16. Word-Wide FLASH Interface with Banking — XCS/ECS Gated

PE2

0

DATA[6]

XADDR[17]

U23

74FCT373/SO

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

PA5

OE

PB2PB0

DATA[12]

B to A

PTK6/7

DATA[2]

MCU RESET

PTK0

0

WE

VCC

MCU ADDR[8]

ADDR[3]

0

XADDR[19]

PTK2

OE*

PA6

1

ADDR[0]

DATA[9]

DATA[5]

A to B

MCU ADDR[9]

PB1

XADDR19

PA1

PA3

MCU_XADDR[16]

ADDR[5]

RST

MCU_XADDR[18]X

XADDR[16]

PTK4 1

ADDR[11]

PA7

DIR

DATA[3]

MCU_XADDR[17]

1

ADDR[2]

1

MCU ADDR[13]

PB3

PB6

MCU ADDR[14]

DATA[0]

DATA[10]

0MCU_XADDR[19]

ADDR[12]

ADDR[9]

PA4

0 1

MCU ADDR[4]

PA6

MCU ADDR[3]

ADDR[6]

MCU ADDR[2]

XADDR[18]

PB5

ECLK

MCU ECS/XCS

PA4

1

X

U24

74FCT16373/SO

23568911121314161719202223

47464443414038373635333230292726

2548

241



2LE1LE

2OE1OE

XADDR[15]

ADDR[1]

PB6

PA0

PTK1

A to B

0 0

MCU ADDR[15]

PB4

ADDR[13]

ADDR[8]

PB3

MCU ADDR[11]

DATA[11]

U27A

74FCT139A/SO

23

1

4567

AB

G

Y0Y1Y2Y3

11

MCU ADDR[6]

1

PA2

MCU ADDR[1]

PB4

ADDR[15]

PB7

0

1

DATA[7]

ADDR[10]

U25

AM29F400AB/SO

3536373839404142

4344

2

456789

1011

12

14

15

16

17

18

19

20

21

22

24

25

26

27

28

29

30

31

33

343

A15A14A13A12A11A10A9A8

WERST

RY/BY

A7A6A5A4A3A2A1A0

CE

OE

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

BYTE

A16A17

PB1

PB7

PTK5 0

A to B

MCU R/W

PB5

MCU ADDR[5]

PA2

MCU ADDR[7] ADDR[7]

1

MCU ADDR[0]

DATA[1]

MCU_XADDR[14]

PA3

A to B

XADDR[14]

PA5

1

DATA[15]

DATA[13]

PA0

PA7

PB0

DATA[4]

0

U26

74FCT1624/SO

1

235689

1112

24

2548

4746444341403837

262729303233353613

14161719202223

1DIR

1B11B21B31B41B51B61B71B8

2DIR

2OE1OE

1A11A21A31A41A51A61A71A8

2A82A72A62A52A42A32A22A12B1

2B22B32B42B52B62B72B8

PB2

R/W

ADDR[14]

PA1

MCU_XADDR[15]

MCU ADDR[12]

MCU ADDR[10]

DATA[14]

ADDR[4]

MCU ECLK

DATA[8]

1

PTK3

PE4



Example #7 — Word-Wide External Device Interface – 100BASE-T Ethernet



Figure 18 demonstrates the interface to a 16-bit Ethernet device to provide word access. It uses expanded wide mode in order to support word (x16) access to the external device.

Comments:

• Only the bus interface to the external device is shown. Additional external devices are required to implement a fully functional Ethernet system. Please refer to the external device’s specifications for these details.

• The data bus from the MCU is flipped (low byte to high byte) to accommodate the interface to big Endian data bus of the external device. While this is not absolutely necessary, it will make the software interface cleaner.

• This external device has internal address latching to interface to a multiplexed bus. The address latches are used in this design to delay the addresses in order to meet the setup/hold time requirements of the external device’s internal address latch.

12

02

36 PPAGE

03 07

31 37

0C00

Memory Map

30 32 33

1C

3D

1E

3F

3E

1D

Internal Flash

15 19

08

3F3A

11

0501

1F18 1B

06 0B

34

0F0D

FFFF

13

3B

16

0E

0000

1A

38

3E

3C

04

17

09

External FLASH

10

35

14

39

0A




Figure 18. Word-Wide External Device Interface — 100BASE-T Ethernet

Software

Application note AN2287 details the signals necessary to implement the external interfaces that the first part of this note uses for example interfaces. This section will detail the four MCU registers that control these interfaces. AN2287 suggests booting the device in normal single-chip mode and then adjusting these registers with software for the proper operating mode. Refer to the device user guide concerning the writeability of all the registers. On most devices, these registers can only be written to once and only under special circumstances.

VCC3.3V

EAD5

XPAD12

EAD15

PAD4

C200.1uF

INTRQ0

XPAD9

Voltage levelshifting

PAD8PAD9

EAD1

PAD2

PAD5

EAD12

RESET

PAD12

U31A

MC74HC00AD

1

23

147

PAD[0..15]

VCC_5V

PAD14

EAD4

EAD13

EAD8

XPAD14

C190.1uF

C140.1uF

GND

VCC_5V

RESET

XPAD10

XPAD1

PAD0

EAD8

U29

74ABT16373B DGG

2356891112

1314161719202223

4746444341403837

3635333230292726

2548

241

4 10 15 21 28 34 39 45

7 18 31 42

1Q11Q21Q31Q41Q51Q61Q71Q8

2Q12Q22Q32Q42Q52Q62Q72Q8

1D11D21D31D41D51D61D71D8

2D12D22D32D42D52D62D72D8

2LE1LE

2OE1OE G

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VC

CV

CC

VC

CV

CCPAD0

XPAD0

EAD4

U31B

MC74HC00AD

4

56

147

EAD7

VCC_5V

XPAD[0..15]

U3074ABT16245B DGG

235689

1112

4746444341403837

4101521

2834

3945

3635333230292726

1314161719202223

124

4825

7183142

1B11B21B31B41B51B61B71B8

1A11A21A31A41A51A61A71A8

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

2A12A22A32A42A52A62A72A8

2B12B22B32B42B52B62B72B8

1DIR2DIR

1OE2OE

VC

CV

CC

VC

CV

CC

EAD7

PAD14

ECLK

VCC_5V

EAD5

PAD4

XPAD6

EAD14PAD7

RESETn

EAD0

XPAD14

PAD11

XPAD2

PAD10

C120.1uF

XPAD4

EAD9

XPAD8

EAD1

C140.1uF

EAD9PAD6

MEMRn

XPAD9

EAD11

EAD10

XPAD7

XPAD0

PAD8PAD9

PAD15

XPAD3

C210.1uF

These buffers will create desired delayfor address bus

GND

EAD3

EAD6

PAD3

EAD12

MEMWn

PAD10

MEMRn

EAD10

EAD15

EAD0

EAD[0..15]

U31D

MC74HC00AD

12

1311

147

C180.1uF

XPAD15

PAD2

EAD13

PAD11

XPAD5

LSTRBn

GND

XPAD7

PAD[0..15]

PAD5

MEMWn

RWn

XPAD11

EAD6PAD7

PAD1

EAD2

PAD15

XPAD2

GND

VCC3.3V

RWn

GND

PAD13

XPAD1

XPAD4XPAD3

XPAD13

XPAD13

EAD3

C130.1uF

GND

PAD1

XPAD10

VCC_5V PAD3

U31C

MC74HC00AD

9

108

147

C110.1uF

EAD11

BUS INTERFACE

PHY

MII INTERFACE

SERIAL

EEPROM

U28

LAN91C111-NE

1 33 44

62 110

77

120

98 11

16

14151718

20

28

94959697

41

787980818283848586878889909192

10710610510410210110099767574737170696866656463616059585655545351504948

3037423846432945313234353640

24 39 52 57 67

72 93

103

108

117

13

19

47

127

128

2

345678910

21

12

2223

121122123124

113114115116

111

112119

12512625

2726

118109

VD

DV

DD

VD

DV

DD

VD

D

VD

D

VD

D

VD

D

AV

DD

AV

DD

TPO+TPO-TPI+TPI-

LNKn

CNTRLn

nBE0nBE1nBE2nBE3

AEN

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31

RESETADSnLCLKARDYnRDYRTNnSRDYINTR0nLDEVRDnWRnDATACSnCYCLEnW/RnVLBUSn

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

AV

SS

AV

SS

X25OUT

XTAL1

XTAL2

CSOUTn

IOS0IOS1IOS2

ENEEPEEDOEEDIEESKEECS

LBK

RBIAS

LEDALEDB

RXD3RXD2RXD1RXD0

TXD3TXD2TXD1TXD0

TXEN100

COL100CRS100

RXDVRXER

MDI

MCLKMDO

RX25TX25

GNDXPAD8

EAD14

PAD6

PAD12

XPAD5

EAD2

XPAD6PAD13

ECLK

XPAD11

GND

GND

XPAD12

XPAD15




/* Expansion Bus settings *//**************************************************************************/ Regs.pear.byte = 0x0C; // %00001100// ||||||||// |||||||+-Reserved// ||||||+--Reserved// |||||+---RDWE----Read / Write (R/W) pin Enabled // ||||+----LSTRE---Low Strobe (LSTRB) pin Enabled // |||+-----NECLK---External E clock is enabled// ||+------PIPOE---IPIP0,1 indicate the instruction queue// |+-------Reserved// +--------NOACCE--No CPU free cycle visibility.

The PEAR register is known as the port E assignment register. It is used to control the setting of the external bus dedicated to port E. It controls which of the external bus control signals are driven from port E. Any signals that are not required for a particular interface may be used as general-purpose I/O. Notice that setting the NOECLK bit turns off the external ECLK. All other signals are enabled by setting the appropriate bit. In the above assignment the ECLK, LSTRB, and R/W signals are activated.

Regs.mode.byte = 0xE3; // %11100011// ||||||||// |||||||+-EME-----PORTE and DDRE are removed from memory // ||||||+--EMK-----PORTK and DDRK are removed from memory // |||||+---Reserved// ||||+----IVIS----No visibility of internal ops on ext. bus// |||+-----Reserved// ||+------MODA--\// |+-------MODB----Normal Expanded Wide// +--------MODC--/

The MODE register controls the MCU external bus capability, internal visibility, and port emulation settings. The MODC, MODB, and MODA bits represent the mode setting detailed in the device user guide and AN2287. IVIS enables all internal data accesses to be echoed externally for data acquisition or logic analysis, depending on security settings.The EMK and EME bits enable port K and port E register accesses to be echoed externally for port replacement.

Regs.ebictl.byte = 0x00; // %0000001// ||||||||// |||||||+-ESTR----E stretches for external access.// ||||||+--Reserved// |||||+---Reserved// ||||+----Reserved// |||+-----Reserved// ||+------Reserved// |+-------Reserved// +--------Reserved

The EBICTL register is used to turn the ECLK output into a free-running clock source. In most external environments the ESTR bit should remain clear. It may however, be useful for emulation systems, or systems without external devices that require a clock source.



Example #8 — Software External Interface

Regs.misc.byte = 0x07; // %00000111// ||||||||// |||||||+-ROMON------- Turn on internal flash// ||||||+--ROMHM------- Make $4000-$7FFF external// |||||+---EXSTR0----\_ Set Stretch to one cycle // ||||+----EXSTR1----/ // |||+-----Reserved// ||+------Reserved// |+-------Reserved// +--------Reserved

The MISC register is used to control some of the miscellaneous functions needed for bus control. The EXSTR1 and EXSTR0 bits control the amount of clock stretching used during external bus accesses. If the ESTR bit of the EBICTL register is set, these bits have no effect. These bits can be used to enable as many as three addition clock cycles for each external access. The ROMHM (ROM high memory) bit can be used to disable a device’s internal FLASH in the $4000–$7FFF address space. This is a good way to interface devices with small memory maps. The ROMON bit controls whether the on-chip FLASH is available. If the ROMON bit is cleared, the entire on-chip FLASH memory is disabled and the entire FLASH memory space is available for external use or emulation.

The ROMON bit may be affected by the ROMCTL pin of the device. Refer to the device user guide for details on active level.


The final example is presented for two basic reasons:

• To present the simplest available interface which requires only the external device and simple software to control it.

• To inspire thought as to the real system goal. What are the real throughput requirements? Is the external memory required for data storage such as data-logging or system calibrations that will only be used once or twice during boot up?

The simplest external interface can be accomplished with just the external device and the general-purpose I/O capabilities of the MCU. The following software example and simple schematic demonstrate how efficient the interface could be. While the example shows a simple FLASH interface, the design can be modified for any external device.

The following routine executes in 33 HCS12 cycles (1.3 µs at 25 mHz, approximately 1.5 MB per second):




;/********************************************************** 5;** Flash software interface 6 ;********************************************************* 7;tU16 Flash_Read(tU32 address) 8;{ 9;tU16 data; ;enter with addr on stack 10;Pim.pth.byte = address>>16; 1000 [05] 180D8102 11 movb 1,sp,pth ;move A0-A7 to port H 60 12;Pim.ptp.byte = address>>8; 1005 [05] 180D8202 13 movb 2,sp,ptp ;move A8-A15 to port P 58 14;Pim.ptj.byte = address; 100A [05] 180D8302 15 movb 3,sp,ptj ;move A16,17 to port J 68 16; Flash_WEHI;Flash_CSLO; 100F [04] 4C0804 17 BSET porte,4 ;set r/w high 1012 [04] 4D0810 18 BCLR porte,16 ;set chip select low 19;data = (Regs.porta.word); 1015 [03] DE00 20 LDX porta ;load D0-D16 21;Flash_CSHI; 1017 [04] 4C0810 22 BSET porte,16 ;disable chip select 23 24;return (data); 101A [01] B754 25 TFR X,D ;return with data in D 26;} 101C [02] 1B83 27 LEAS 3,SP ;de-allocate stack 101E [06] 0A 28 RTC



Conclusion

Figure 19. Software Flash Interface

The actual external access only requires about 20 cycles. If block transfers are implemented, the interface will operate faster (about one-tenth the rated speed of low-cost 70 ns FLASH memory). This is approximately equivalent to a 2.5 MB per second transfer rate.

Conclusion

Freescale Semiconductor’s HCS12 external bus enables the designer to create an expanded device system for situations where a single-chip solution is impractical due to cost or availability of peripherals. Using the HCS12 external bus to create an expanded device system means the designer can add to the functions available on a single MCU.

This page is intentionally blank.

DATA[10]

ADDR[10]

PTH6

PE4

PB7

PTJ1

PTH0

ADDR[15]

ADDR[13]

DATA[14]

ADDR[8]

PA5

PTH4

PTP1

PA6ADDR[16]

PTH3

ADDR[6]

ADDR[11]

U32

AM29F400AB/SO

3536373839404142

4344

2

456789

1011

12

14

15

16

17

18

19

20

21

22

24

25

26

27

28

29

30

31

33

343

A15A14A13A12A11A10A9A8

WERST

RY/BY

A7A6A5A4A3A2A1A0

CE

OE

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

BYTE

A16A17

DATA[8]

ADDR[1]

PTP0

PTJ0

PTP3

PB0

PTP4

DATA[1]

DATA[11]

PTH2

PTP6

PB2

ADDR[5]

ADDR[7]

ADDR[18]

PB4

DATA[3]

PTP7

PA0

VCC

RESET

DATA[15]

DATA[5]

DATA[13]

PB3

DATA[2]

DATA[9]

ADDR[4]ADDR[3]

PB6

PA7

WE*

PA4

PB1

PTP2

DATA[4]

DATA[12]

PE2

PE3

PA1

PB5

DATA[7]

OE*

DATA[6]

ADDR[2]

ADDR[17]

PA3

DATA[0]

ADDR[14]

PTH7

PA2ADDR[12]

CE*

ADDR[9]

MCU RESET

PTH5

PTH1

PTP5



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AN2408/DRev. 2, 8/2004

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