An Ultra-Low-Power TemperatureCompensated Voltage Reference GeneratorGiuseppe De Vita Giuseppe IannacconeCustom Integrated Circuits Conference 2005 Proceedings of the IEEE 2005

國 立 彰 化 師 範 大 學積 體 電 路 設 計研究所指導教授 林志明 教授研 究 生 曹 元 志 學 號 95662011

OUTLINE Introduction Circuit Description Temperature Compensated Experimental Results References

Introduction The widespread use of battery-operated systems A typical approach consists in using a bandgap ref

erence Other voltage references exploit the principle of th

reshold voltage difference based on the weighted gate-source voltage differe

nce between two NMOS transistors

Circuit Description

Circuit Description

u carrier mobility in the channel

VT thermal voltage

Vth threshold voltage W channel width L channel length

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

OUTLINE Introduction Circuit Description Temperature Compensated Experimental Results References

Introduction The widespread use of battery-operated systems A typical approach consists in using a bandgap ref

erence Other voltage references exploit the principle of th

reshold voltage difference based on the weighted gate-source voltage differe

nce between two NMOS transistors

Circuit Description

Circuit Description

u carrier mobility in the channel

VT thermal voltage

Vth threshold voltage W channel width L channel length

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Introduction The widespread use of battery-operated systems A typical approach consists in using a bandgap ref

erence Other voltage references exploit the principle of th

reshold voltage difference based on the weighted gate-source voltage differe

nce between two NMOS transistors

Circuit Description

Circuit Description

u carrier mobility in the channel

VT thermal voltage

Vth threshold voltage W channel width L channel length

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Circuit Description

Circuit Description

u carrier mobility in the channel

VT thermal voltage

Vth threshold voltage W channel width L channel length

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Circuit Description

u carrier mobility in the channel

VT thermal voltage

Vth threshold voltage W channel width L channel length

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Circuit Description

Has to be very small

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Circuit Description M7 and M8 operate in the s

aturation region

determine the minimum value of the bias current

Equation (5) limits the minimum power consumption of thevoltage reference generator

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Circuit Description transistor M2 has a drain-source voltage of at least

100 mV

The maximum supply voltage is imposed by the maximum drain-source voltage allowed for MOS transistors

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Temperature Compensated Threshold voltage of an NMOS transistor decrease

s linearly with the temperature

Kt1 BSIM3v3 coefficient that models the temperature dependence of the threshold voltage

AMS 035 μm CMOS IC technology such parameter is033 mVdegC for an NMOS transistor and 045 mVdegC for aPMOS transistor

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Temperature Compensated From (3) (4) and (9) and assuming that (5) is fulfilled we can

derive the following expression for the reference voltage

Differentiating (10) with respect to the temperature and takinginto account (8) one obtains

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Temperature Compensated Equating (11) to zero we obtain

Because of the channel modulation effectcalculating VGS7 and VGS8 from (1) and substituting them in(4)

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Experimental Results

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Experimental Results

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

Experimental Results

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4

References [1] BS Song PR Gray ldquoA precision curvature-compensated CMOS bandgap reference

rdquo IEEE Journal of Solid State Circuits vol DC-18 pp634-643 December 1983 [2] KN Leung PKT Mok ldquoA sub-1 V 15 ppmdegC CMOS Bandgap Voltage Reference with

out requiring Low Threshold Voltage Devicerdquo IEEE Journal of Solid State Circuits vol 37 pp 526-530 April 2002

[3] RA Blauschild PA Tucci RS Muller RG Meyer ldquoA new NMOS Temperature Stable Voltage Referencerdquo IEEE Journal of Solid State Circuits vol SC-13 pp 767-774 December 1978

[4] H Tanaka Y Nakagome J Etoh E Yamasaki M Aoki K Miyazawa ldquoSub-1 μA Dynamic Reference Voltage Generator for battery-operated DRAMsrdquo IEEE Journal of Solid State Circuits vol 29 pp 448-453 April 1994

[5] MC Tobey DJ Gialiani PB Askin ldquoFlat-Band Voltage Referencerdquo US Patent 3 975 648 August 1976

[6] HJ Oguey B Gerber ldquoMOS Voltage Reference based on polysilicon gate work function differencerdquo IEEE Journal of Solid State Circuit vol SC-15 pp 264-269 June 1980

[7] KN Leung PKT Mok KC Kwok ldquoCMOS Voltage Referencerdquo US Patent 6 441 680 August 2002

[8] KN Leung PKT Mok ldquoA CMOS Voltage Reference Based on Weighted 1049083VGS for CMOS Low-Dropout Linear Regulatorsrdquo IEEE Journal of Solid State Circuits vol 38 pp 146-150 January 2003

[9] H Banba et al ldquoA CMOS Bandgap Reference Circuit with Sub-1V Operationrdquo IEEE Journal of Solid State Circuits vol 34 pp 670-674 May 1999 754 26-5-4