AN INTEGRATED ADAPTIVE BIAS SOLUTION FOR ZERO PASSIVE COMPONENT COUNT HIGH-PERFORMANCE MIXED-SIGNAL ICS
by
requirements for the degree of
Doctor of Philosophy in Electrical Engineering
School of Electrical and Computer Engineering
Georgia Institute of Technology
AN INTEGRATED ADAPTIVE BIAS SOLUTION FOR ZERO PASSIVE COMPONENT COUNT HIGH-PERFORMANCE MIXED-SIGNAL ICS
Approved by: ___________________________
2.2 State of the Art in Biasing Techniques.................................................................. 17
2.2.1 Trimable MOSFETS for Current Calibration .............................................. 17
2.2.2 Off-chip Reference Sources and Bandgap References ................................ 21
2.2.3 Switched Capacitor Bias Sources................................................................. 22
2.2.4 Feedback as a Means of Trimming Analog Circuitry .................................. 22
2.2.5 Regulated Cascode Current Mirror Memory Circuit ................................... 23
Chapter 3: Choice of DAC Architecture ........................................................................... 27
3.1 Motive ................................................................................................................... 27
3.2 Digital-to-analog Converters................................................................................. 29
3.3 Monte Carlo Analysis as a Cornerstone of the Design Process ............................ 38
3.4 Consideration of Currently Available DAC Architectures ................................... 55
3.4.1 Types of Digital-to-analog converter architectures...................................... 55
3.4.2 Switched Current DAC Layout to Minimize Error in Current Cells ........... 56
3.4.3 CMOS layout to minimize the effects of process variations........................ 59
3.4.4 Consideration of Transistor Mismatch in the Design of DACs ................... 66
3.4.5 Over-sampled Digital-to-analog Converters ................................................ 71
3.5 Characterization of the DAC Circuit..................................................................... 73
3.5.1 Monte Carlo Analysis of the Selected DAC Topology................................ 73
3.5.2 Characterization of the Original DAC Circuit in a 0.8-micron CMOS
Process............................................................................................................. 81
3.5.3 Further Design Choices for the 0.8-micron CMOS Process DAC design ... 93
3.5.4 Characterization of the New DAC Circuit in a 0.8-Micron CMOS
Process............................................................................................................. 96
Chapter4: Building High Resolution Bias Sources with the Simple Five-Bit DAC....... 102
4.1 The Overlapping DAC Scheme........................................................................... 102
4.1.1 An Example application of the Overlapping DAC Trimming Scheme in
0.8-micron CMOS......................................................................................... 103
4.1.2 Experimental Precision of Overlapping DACs in 0.8-Micron CMOS....... 111
4.2 Limitations on the Application of the Technique of Overlapping DACs (A
Statistical Approach) ........................................................................................... 120
4.4 An extension of the overlapping DAC scheme................................................... 137
4.4.1 Taking Advantage of Some Free Area in the Standard Bias-Bus Design.. 137
4.4.2 A Uniform Current Density Approach to DAC Design............................. 138
Chapter 5: Applications of the CMOS Bias-Bus ............................................................ 145
5.1 Five-bit DAC grayscale Control of an 8x8 Array of Resonant Cavity
Enhanced Light-Emitting Diodes........................................................................ 145
5.2 A CMOS optical transmitt/receive chip with adapative biasing ......................... 153
5.2.1 Biasing Requirements of the TXRX System.............................................. 153
5.2.2 CMOS Bias-Bus Circuitry ......................................................................... 159
5.2.2 Results of measurements performed on the TXRX system ....................... 165
5.3 Bias Support of a VLSI Bipolar Analog to Digital Converter ............................ 174
5.4 Applications to Analog Computing..................................................................... 176
Chapter 6: Conclusions ................................................................................................... 178
APPENDIX A: Results of measurements made on a sample set of seven-bit digital-to-
analog converters in a 0.8-micron CMOS process.................................................... 181
APPENDIX B: Results of measurements made on a sample set of minimum-
geometry 0.8-Micron CMOS five-bit digital-to-analog converters .......................... 196
B.1 Maximum percent error in a set of 30 measured 0.8-micron five-bit DACs
over a range of reference currents ....................................................................... 196
B.2 Output Current in a set of thirty measured 0.8-micron five-bit DACs using
50uA reference currents ...................................................................................... 199
B.3 Lab-View Program for Automated Measurements of Digital to Analog
Converters ........................................................................................................... 203
APPENDIX C ................................................................................................................. 205
C.1 PSPICE circuit file for the two-micron five-bit DAC Monte Carlo simulation. 205
C.2 Output current from PSPICE Monte Carlo simulation of the two-micron five-
bit DAC ............................................................................................................... 215
APPENDIX D ................................................................................................................. 221
APPENDIX E.................................................................................................................. 225
E.1 Measurements to verify functionality of the TXRX Bias-Bus ........................... 225
E.2 Measurements demonstrating digital control of TXRX emitter-driver using
the Bias-Bus ........................................................................................................ 227
E.3 'C' Computer Program Written To Control Data Entry to TXRX Bias-Bus....... 229
E.4 Documentation of Digital (RSIM) Simulation of Bias-Bus system ................... 232
E.5 HSPICE simulation of CMOS Bias-Bus ............................................................ 234
APPENDIX F.................................................................................................................. 237
LIST OF FIGURES
Number Page Figure 1. Trimable MOSFET............................................................................................ 19
Figure 2. Circuit diagram of a regulated cascode current source memory cell................ 26
Figure 3. Single cascode current mirror ........................................................................... 28
Figure 4. Ideal two-bit digital-to-analog converter .......................................................... 32
Figure 5. Schematic of an example two-bit DAC using single cascode current mirrors . 33
Figure 6. Acceptable error limits for a two-bit DAC ....................................................... 34
Figure 7. Input-output relation of several two-bit DACs................................................. 36
Figure 8. Error in several example two-bit DACs ........................................................... 37
Figure 9. Photograph of fabricated test structures............................................................ 40
Figure 10. PMOS minimum-geometry cascode current mirror ....................................... 45
Figure 11. Layout of PMOS minimum-geometry cascode current mirror....................... 46
Figure 12. PSPICE Monte Carlo simulation of minimum-geometry PMOS cascode
current mirror .................................................................................................. 47
Figure 13. Mean percent error in 50 simulated PMOS minimum-geometry cascode
current mirrors................................................................................................. 48
Figure 14. Standard deviation of error in 50 simulated PMOS minimum-geometry
cascode current mirrors ................................................................................... 49
Figure 15. Maximum magnitude (percent) error in fifty simulated PMOS minimum-
geometry cascode current mirrors ................................................................... 50
Figure 16. Probe output of simulation of four times minimum-geometry cascode
current mirror .................................................................................................. 51
Figure 18. Standard deviation of error in four-times minimum-geometry cascode
current mirror .................................................................................................. 53
Figure 19. Maximum (percent) error in four times minimum-geometry cascode
current mirror .................................................................................................. 54
Figure 20. DAC switching circuit using a dummy load to optimize speed ..................... 58
Figure 21. An example of gradient error in a set of current sources................................ 62
Figure 22. An example of symmetrical error in a set of current sources ......................... 62
Figure 23. Example statistical DAC layout schemes ....................................................... 65
Figure 24. Differential amplifier ...................................................................................... 68
Figure 25. Differential amplifier designed using common orientation layout rules ........ 69
Figure 26. Differential amplifier designed without applying common orientation
layout rules ...................................................................................................... 70
Figure 28. Layout of the five-bit two-micron DAC......................................................... 75
Figure 29. Results of Monte Carlo analysis of two-micron five-bit converter ................ 76
Figure 30. Step size of the fifty simulated two-micron DACs........................................ 77
Figure 31. Mean error from simulation of two-micron five-bit DAC.............................. 78
Figure 32. Standard deviation of error from simulation of two-micron five-bit DAC .... 79
Figure 33. Maximum error from simulation of two-micron five-bit DAC ...................... 81
Figure 34. Photograph of 0.8-micron DAC test structures .............................................. 84
Figure 35. Layout of the seven-bit 0.8-micron DAC ....................................................... 85
Figure 36. Schematic diagram of the 0.8-micron seven-bit DAC.................................... 86
Figure 37. Measured performance of several 0.8-micron CMOS seven-bit DACs ......... 87
Figure 38. Results of measurements made on a typical five-bit converter in the 0.8-
micron test fabrication..................................................................................... 88
Figure 39. Results of measurements made on a typical six-bit converter in the 0.8-
micron test fabrication..................................................................................... 89
Figure 40. Error from best-fit line in a typical 0.8-micron five-bit converter.................. 90
Figure 41. Error from best-fit line in a typical 0.8-micron six-bit converter ................... 91
Figure 42. Circuit diagram of the basic five-bit digital-to-analog converter cell ............ 95
Figure 43. Layout of the five-bit 0.8-micron DAC.......................................................... 98
Figure 44. Input-output relation of a sample 0.8-micron five-bit DAC, along with a
best-fit line....................................................................................................... 99
Figure 45. Error measured in a 0.8-micron five-bit DAC.............................................. 100
Figure 46. Error Vs reference current in a measured set of 30 0.8-micron five-bit
DACs............................................................................................................. 101
Figure 47. Results of measurements performed on a typical eleven-bit converter ........ 106
Figure 48. Error, as the difference between the measured value and the "target slope"
line, in the eleven-bit converter..................................................................... 107
Figure 49. Graphical representation of the example converter overlap scheme ............ 109
Figure 50. Overall architecture of eleven-bit DAC with the overlapping DAC
correction scheme.......................................................................................... 110
Figure 51. Photograph of the 64-output CMOS bias-support chip ................................ 114
Figure 52. Step size in the 50uA/8uA corrected DAC................................................... 117
Figure 53. Step size in the 50uA/4uA corrected DAC................................................... 118
Figure 54. Range and resolution of the elements of the 50uA/4uA overlapping DAC . 119
Figure 55. Error statistics verses bias current in a set of 30 0.8-micron five-bit DACs 122
Figure 56. Percent error in 30 measured DACs ............................................................. 125
Figure 57. Percent error in a sub-set of the measured DACs......................................... 126
Figure 58. Mean normalized step size for a family of reference currents in 30
measured DACs............................................................................................. 128
Figure 59. Standard deviation of normalized step size for a family of reference
currents in 30 measured DACs...................................................................... 129
Figure 60. Cumulative error distribution in a set of thirty measured DACs.................. 132
Figure 61. Three-DAC overlap example........................................................................ 134
Figure 62. Two alternative layouts of the CMOS Bias-Bus cell.................................... 140
Figure 63. Schematic diagram of the uniform current density DAC circuit design....... 143
Figure 64. Results of Monte Carlo simulations of the four current mirrors discussed .. 144
Figure 65. Systematic diagram of the CMOS circuitry used in the 8x8 grayscale LED
array............................................................................................................... 147
Figure 66. Layout of grayscale cell ................................................................................ 148
Figure 67. Layout of the grayscale array chip................................................................ 149
Figure 68. Photograph of the eight by eight array chip with integrated infrared LEDs. 150
Figure 69. Photograph of several sections of the 8x8 grayscale IR-LED array............. 151
Figure 70. Photograph of the eight by eight grayscale array displaying a Georgia
Tech logo....................................................................................................... 152
Figure 72. Graphical view of three-DAC lash up .......................................................... 159
Figure 73. Systematic diagram of the CMOS bias bus system ...................................... 161
Figure 74. Bias-Bus cell circuit layout including five-bit DAC, shift register, and
memory register............................................................................................. 162
Figure 75. Layout of the shift register and memory cell ................................................ 163
Figure 76. Layout of the clock generator cell ................................................................ 164
Figure 77. Measured step sizes of the TXRX Bias-Bus................................................. 168
Figure 78. Results of first measurement of TXRX emitter-driver with Bias-Bus ......... 170
Figure 79. Results of second measurement of TXRX emitter-driver with Bias-Bus..... 171
Figure 80. TXRX emitter-driver output current percent error ....................................... 172
Figure 81. Bias-Bus control of the TXRX receiver offset ............................................. 173
Figure 82. Bipolar high precision high speed analog to digital converter chip ............. 175
Figure 83. Screen capture of the Lab-View program written to control the DAC
measurements ................................................................................................ 204
Figure 84. Equivalent circuit of current switching DAC output .................................... 223
Figure 85. Regulated cascode current source................................................................. 224
Figure 86. Measurements of five five-bit DACs from the TXRX chip ......................... 226
Figure 87 RSIM simulation of CMOS TXRX Bias-Bus ................................................ 233
Figure 88. HSPICE graphical output of simulation of CMOS Bias-Bus for TXRX
project............................................................................................................ 235
Figure 89. PSPICE Monte Carlo simulation of 8X minimum-geometry PMOS
cascode current mirrors ................................................................................. 240
Figure 90. Mean percent error in 50 simulated 8X minimum-geometry cascode
current mirrors............................................................................................... 241
Figure 91. Standard deviation of percent error in 50 simulated 8X minimum-
geometry cascode current mirrors ................................................................. 242
Figure 92. PSPICE Monte Carlo simulation of 16X minimum-geometry PMOS
cascode current mirrors ................................................................................. 243
Figure 93. Mean percent error in 50 simulated 16X minimum-geometry cascode
current mirrors............................................................................................... 244
Figure 94. Standard deviation of percent error in 50 simulated 8X minimum-geometry
cascode current mirrors ................................................................................. 245
Number Page Table 1. Input-output relation of an ideal two-bit DAC................................................... 30
Table 2. Input-output relation of several two-bit DACs .................................................. 35
Table 3. Statistical distributions for two-micron CMOS transistor models..................... 41
Table 4. Five-bit DAC percent error statistics at 60uA input current ............................ 130
Table 5. Least-significant-bit current for a given Iref in a five-bit DAC....................... 156
Table 6. Specified and measured example BIAS requirements ..................................... 158
Table 7. Specifics of three-DAC lash-up of Table 6...................................................... 158
Table 8 DAC measurements ........................................................................................... 225
Table 9. Measurement of TXRX using 1 VDC emitter-driver input voltage
approximation................................................................................................ 227
Table 10. Measurement of TXRX using 1.37 VDC emitter-driver input voltage
approximation................................................................................................ 228
11
ACKNOWLEDGMENTS
Ravi Poddar provided the CMOS models used in the Monte Carlo simulations
performed in this research. A large number of test structures were fabricated and
measured to provide a statistical basis for the models. Mr. Poddar organized the
measurements and the database, as well as constructed and tested the models.
Abelardo Lopez-Lagunas provided assistance with the digital circuits used. The
shift register and memory register cells are directly based on his circuit designs.
John Dorsey provided the opportunity and motivation for me to enter graduate
school.
1.1 INTRODUCTION
The objective of this research has been to provide an integrated adaptive bias solution
for zero passive component count high-performance mixed-signal ICs. The solution is
applicable to circuit designs requiring a large number of adaptive bias sources. Also,
circuits requiring adaptive control are accommodated. The solution allows for dramatic
reductions in pad counts of chips requiring multiple bias sources. To keep pad count low,
the system is controlled via a serial input and shift register, allowing implementation with
a minimum number of bonding pads. The circuitry implemented consumes a minimum
amount of chip area. Additionally, it is compatible with standard digital CMOS
processes and is a scalable solution.
The system employs a large number of minimum-geometry digital-to-analog
converters and digital control logic. To achieve the resolution necessary in a wide variety
of applications, the system utilizes the overlapping DAC scheme herein presented. This
system provides a superior solution to analog feedback in many cases where parameter
adjustment must rely on signals that are not necessarily analog in nature. Additionally,
an adaptive trimming algorithm has been devised to control the system in a real-time
14
mode. The developed system, as used in a number of systems fabricated as part of
ongoing research at Georgia Tech, been come to be know as the CMOS ‘bias bus’.
One example of a system that must be designed with adaptive bias is an optical
transmit/receive chip designed at Georgia Tech. This is a system of optical emitters and
detectors placed on top of digital CMOS processing and support circuitry. The support
circuitry includes emitter drivers, detector receivers, and amplifiers, as well as biasing
support circuits. In this case, the system will require a total of 36 adjustable bias current
sources and nine adjustable voltage bias sources. The precision and adjustability required
by systems such as this make demands that cannot be achieved with designs relying
solely on component matching in a standard CMOS process. Additionally, it is usually
undesirable to provide an off-chip biasing solution at the expense of, in the above
example, at least 36 bonding pads and external bias sources. This project and the work
leading up to it have been the driving forces behind this research.
Multichip modules are in common use in the manufacture of radio frequency and
microwave systems. These often consist of a millimeter wave IC, a number of external
passive components, and several digital and analog ICs.1 Precision bias sources are
usually provided as part of the multichip module, but not as part of the actual millimeter
wave IC. Current technology allows for the inclusion of packaged high-precision DACs
as bias sources. A promising area is the thin film integration of a microwave circuit on
top of a silicon CMOS chip.2 Using the proposed biasing scheme could result in the
elimination of costly bipolar DAC chips. This will reduce the cost, size, and complexity
15
of the multichip module. In some cases, where the only discreet components of the
module are biasing related (and not, for instance, capacitors in the RF path), the need for
a multichip module could be eliminated. The cost and size advantages of this can be
tremendous.
2.1 THE NEED FOR ACCURATE BIAS SOURCES
A basic problem in the design of compact high-resolution, high-precision CMOS
circuits is the need for accurate bias sources. Constant technological advances in
semiconductor fabrication methods allow as well as demand smaller, faster, denser, and
more complex circuits. Analog circuits built in a digital CMOS process as part of a
mixed-signal system often present the major performance barrier. To construct high-
performance analog circuits in a CMOS process not well suited to analog design would
be greatly aided by more advanced biasing techniques.
Much research effort as of late has been focused in the area of optoelectronic
circuits, both for signal processing and interfacing.3, 4 It is now common to encounter
circuits that must amplify or process extremely small signals recovered from optical
detectors. In many cases, this will require circuitry with adjustable bias points.5
Particularly sensitive circuits may require a large number of bias sources to operate.6, 7
This may be to establish an operating point under static or dynamic constraints, or for
other goals, such as adaptive power consumption control.
17
Several methods of providing current trimming are presently popular. These
methods are now discussed and the individual merits of each are examined. This is done
to substantiate the claim that no present method is capable of providing a similar amount
of precision bias trimming without a substantial increase in chip area. Recognizing the
fact that good linear passive components are not available in the CMOS processes of
interest in this research, biasing schemes relying on passive component precision will not
be considered.
2.2.1 TRIMABLE MOSFETS FOR CURRENT CALIBRATION
Currently, several methods of biasing in CMOS circuits are in wide use. One
scheme adjusts a bias current by applying binary summing of multiple identical current
sources. This central circuit element utilized in this method has been referred to in the
literature as a ‘trimable MOSFET’.8 The schematic of a trimable MOSFET is supplied in
Figure 1. Here, the transistor Mmain is supplying the bulk of the current, and the
remainder of the transistors, Mi, i=1...9, each supply a sub-binary weighted current.
These currents are chosen such that I(Min) > I(Min+1), where I(Mi1) < 0.05xI(Mmain). The
area used by the entire adjustable MOSFET will be approximately 1.1 times that of Mmain.
This scheme does require a complicated calibration algorithm. A counter and supporting
digital logic, plus memory, must be used to sweep the trimable MOSFET until a
18
comparator indicates that a satisfactory current error tolerance has been reached.
Although, once stored in the digital memory the calibrated value will suffer no change
due to leakage currents, as in the case of a system based on voltage sampling capacitate
memory. Periodic re-calibration of the trimable MOSFET system will still be necessary
to overcome thermal changes if high-resolution performance is to be achieved from the
DAC. The complexity of the digital support circuitry involved in the calibration process
of this design cannot be considered if building a very small high-resolution bias source is
a design goal. This method is not capable of simultaneously providing the precision and
range available from a DAC of similar circuit area.
19
2.2.2 OFF-CHIP REFERENCE SOURCES AND BANDGAP REFERENCES
Another popular method of bias trimming involves an off-chip reference. In many
cases, external resistors are utilized to provide a base for internal reference sources.
Some of these circuits use an internal CMOS or BiCMOS bandgap reference to supply a
reference voltage to the external resistors.9 While bandgap references are stable with
temperature, the output value cannot be reliably predicted to within 10%.10 Therefore,
laser trimming is usually necessary before operating the fabricated chip. The range of the
current available in the DAC-based scheme allows for a wide enough design margin such
that laser trimming is usually not necessary. The DAC-based system was designed with a
laser trimming option for the central reference current source to increase versatility and
add an extra level of robustness to the test fabrications.
Bandgap references ultimately require a precision reference. In fact, there are
examples in the literature of CMOS bandgap references, which are provided with a DAC
reference source.11 One of the most reliable bandgap references in the literature applies
the techniques of micro-machining to thermally isolate the bandgap reference circuitry by
means of a small “moat.” 12 The DAC-based biasing system requires no post process
micro-machining. The ability to operate the DAC-based biasing scheme without the need
for off-chip components is, in most cases, a clear advantage. This is also dictated by the
packaging specifications of many of the projects driving this research.
22
2.2.3 SWITCHED CAPACITOR BIAS SOURCES
Switched capacitor circuits or charge pumps are yet another popular method of
constructing bias sources.13, 14 The passive components required for switched capacitor
designs pose a clear disadvantage in many designs, particularly where space is at a
premium. Additionally, switched capacitor designs require a linear capacitor, which is
not available in a standard digital CMOS process.
2.2.4 FEEDBACK AS A MEANS OF TRIMMING ANALOG CIRCUITRY
Another solution for circuitry requiring extreme precision is to design with analog
feedback. Feedback can in fact be used in some cases to establish and adapt a bias input
based on the state of an analog output. According to Ogata, Feedback is an “… operation
which, in the presence of disturbances, tends to reduce the difference between the output
of a system and the reference output … and which does so on the basis of this output”.15
The main drawbacks of feedback are as follows. First, huge passive components are
required, which must usually be supplied off-chip. Of specific importance to the cases
involved in this research, large valued linear passives are not available in standard CMOS
processes. Second, the feedback signal is limited to an analog output. In the optical
transmit-receive system described above, it is desired to feed back a bit indicating the
state of the BER (bit error rate) of a communications channel. Third, analog feedback
has the inherent risk of instability. A ‘digital feedback’ system still has issues of
23
stability, but the solutions are more robust by virtue of the fact that hysteresis may be
included in the feedback mechanism. This means that the digital trimming circuitry can
reach a stable point and stop trimming for long periods of time.16
Continuous digital trimming can, in many cases, feed back much more meaningful
information. For example, in a digital communications channel, the fact that the output
has a zero-value time average is not an indication that the lowest BER has been achieved.
This information would typically be returned as binary data, or a good/bad decision. The
returned signal can be used to initiate the trimming process. In contrast to analog
feedback, the returned signals can come from arbitrarily long distances.
To realize the range and resolution of the DAC-based trimable biasing method, the
currently available biasing methods all require significantly more chip area.
2.2.5 REGULATED CASCODE CURRENT MIRROR MEMORY CIRCUIT
Several popular methods of providing trimmed bias sources involve utilizing a
voltage stored on a capacitance to set a calibrated current. In most cases this involves a
single output transistor, with the gate-source capacitance acting as the memory element
(an example circuit can be seen in Figure 27).
The shortcoming of the single transistor method is that if the drain source voltage
during the output phase differs from that during the calibration phase, the CMOS channel
24
length modulation effect will cause an error in the current value actually delivered to the
load. To reduce this error, Vds can be stabilized by using a cascode current source to
increase output resistance.17, 18 A method, which provides even higher output resistance,
is to include the single current source in an output voltage stabilizing feedback loop. This
can be accomplished either by the use of an op-amp, or the regulated-cascode circuit.58
A regulated cascode current source memory cell is presented in Figure 2. The regulated
cascode current source provides significantly higher output resistance than does the
single transistor CMOS current source.19, 20, 21 A brief discussion of the merits of the
regulated cascode current source are presented in APPENDIX D.
The circuit of Figure 2 functions as follows. The switches are both placed in the j1
position. This allows the reference source, Icalibrate to program a voltage onto the memory
capacitor Cgs. When the switches are placed in the j2 position, the circuit delivers the
programmed current to Iout. The voltage on the capacitor must be periodically refreshed.
Also, a 'stand-in' current source must be supplied to bias the supported circuit during the
period of time when the source is off line being programmed.
The bias source that is required in this research must be able to deliver output
current over a large range. While the regulated cascode current mirror memory can be
used to design a bias source with a high level of precision, it has very limited output
range. The circuit also lacks the ease of adjustability available with a digital-to-analog
converter based solution. The regulated cascode current mirror memory could be used as
25
the basis for the construction of a DAC, but the resulting design would not qualify as a
small-area circuit. For these reasons, the regulated cascode current mirror memory has
not been adopted for use in the bias bus design.
26
cascode current source memory cell
27
ARCHITECTURE
3.1 MOTIVE
The issue of how to build compact, precise Digital-to-analog converters in short
channel CMOS processes has been driven by the need to fabricate large arrays of such
converters.22 The first step in the design process has been to characterize the CMOS
process to be used. (We are currently using a 0.8-micron CMOS process.) We have
accomplished this by fabricating and measuring of test structures relevant to the proposed
DAC architecture. Of primary interest were the capabilities of the CMOS single cascode
current mirror. A circuit diagram of a CMOS single cascode current mirror is presented
in Figure 3.
Extensive predictive modeling, using HSPICE Monte Carlo simulations, has been
performed. By comparing the simulated and measured data of the CMOS single cascode
current mirror, valuable insight has been gained into the validity of the models used in the
HSPICE Monte Carlo simulations. This has allowed for fine tuning the models used. A
valid model for a single cascode current mirror was a prerequisite to running Monte Carlo
simulations on proposed converter designs.
28
29
3.2 DIGITAL-TO-ANALOG CONVERTERS
Before an analysis of the test fabrications can be undertaken, an understanding of
the basics of digital-to-analog converter (DAC) design must be established.
Consider the example of a simple two-bit DAC. Here we will define the value of
the most-significant-bit (MSB) to be 1.0. In the case of an ideal two-bit converter, the
least-significant-bit (LSB) will be the immediately adjacent bit to the MSB, and will have
a value of ½. The output of a DAC is a stair-step, where the value of the LSB determines
the smallest increment of the step. This converter will have two binary inputs, one each
to turn on and off the LSB and MSB, and one output. The output is simply the binary-
weighted sum of all the bits of the DAC, in this case the LSB and the MSB.
The example ideal two-bit converter is capable of producing four distinct output
levels depending on the binary inputs. This is detailed in Table 1. The ideal two-bit
converter, constructed using ideal current sources, is presented in Figure 4. The non-
ideal two-bit converter, constructed using single cascode current mirrors, is presented in
Figure 5.
The number of bits in a DAC, provided that the output meets error definitions,
defines the resolution of the DAC. For a two-bit converter to be considered acceptable,
the error in the DAC output must fall within a certain limit. Here, the maximum
acceptable DAC output error, for any input combination, is defined as one-half of one
30
LSB. Therefore, for a two-bit converter with an LSB of ½, the maximum acceptable
DAC output error is ¼. This is presented graphically in Figure 6, where the dashed lines
indicate a band of acceptable error in a non-ideal two-bit DAC.
LSB binary input 0 1 0 1
MSB binary input 0 0 1 1
DAC output 0 ½ 1 1 ½
Table 1. Input-output relation of an ideal
two-bit DAC
Input-output relations of one ideal, and two non-ideal converters are presented in
Table 2, and graphically in Figure 7. The error for both of the example non-ideal two-bit
DACs is presented in Table 2 and in Figure 8. While the difference in the error of DAC 2
and DAC 3 in Table 2 is slight, as can be seen graphically in Figure 8, the output of the
two DACs, as seen in Figure 7 is markedly different. In fact, DAC 3 is exhibiting non-
monotonic behavior. In Figure 7, ‘series 1’ represents an ideal DAC, while series 2 and 3
represent the non-ideal DACs 2 and 3.
31
With an understanding of basic digital-to-analog converter operation in hand, the
next important task is to gain an understanding of what can actually happen in a real
converter. A real converter is subject to process parameter variations and will exhibit
less than ideal performance. An understanding of the statistics of the fabrication process
is prerequisite to an understanding of the performance of a real DACs.
Monte Carlo analysis is an important tool in understanding, and in fact predicting,
the performance of a set of identical circuits from a particular fabrication run. In the next
section, experimentally generated device statistics are combined with Monte Carlo
analysis. The results yielded have enabled important decisions to be made about the
DAC circuitry prior to committing financial resources to fabrication.
32
converter
33
DAC using single cascode current mirrors
34
bit DAC
35
LSB MSB ideal DAC 2 Error 2 DAC 3 Error 3
0 0 0 0 0 0 0
1 0 0.5 0.25 0.25 0.77 -0.27
0 1 1 1.25 -0.25 0.73 0.27
1 1 1.5 1.5 0 1.5 0
Table 2. Input-output relation of several
two-bit DACs
two-bit DACs
DACs
38
3.3 MONTE CARLO ANALYSIS AS A CORNERSTONE OF THE DESIGN
PROCESS
Monte Carlo analysis, performed within PSPICE, has been a valuable tool in this
research. It has doubtless saved time and money in allowing a great deal of insight into a
design before committing to fabrication. Monte Carlo analysis allows simulation of
electronic circuits to be performed while varying, among other things, transistor model
parameters. The transistor parameters may be varied according to a statistical
distribution. An extensive database has been compiled from measurements made on
actual transistors. Fabrications of chips containing large numbers of minimum-geometry
transistors were done in the two-micron CMOS process specifically for this purpose.23
From this database, a statistical model for the minimum-geometry two-micron transistor
was derived. The complete models, as well as the PSPICE source file, are included in
APPENDIX C.1. A photograph of several of the test transistors is presented in Figure 9.
The usefulness of the two-micron process is somewhat limited by the fact that the
two-micron channel is not that short in relation to the target processes. However, the
two-micron process does provide an easy and inexpensive means of fabricating initial test
structures. The results obtained have been used as building blocks to proceed with the
0.8-micron designs.
39
The normal distribution mean and standard deviation for the PMOS and NMOS
models are included in Table 3. Both PMOS and NMOS are level three models, with
device widths of three-micron and lengths of two-microns.
40
structures
41
Mean 0.7144 6.8e-5 0.5728 -0.9002 3.4454e-5 0.4895
std. dev. 0.9% 1.7% 2.7% 1.7% 2.5% 3%
Table 3. Statistical distributions for two-
micron CMOS transistor models
As an example Monte Carlo simulation, consider the simulation of the simple
PMOS minimum-geometry cascode current mirror of Figure 10. An image of the layout
of the PMOS cascode current mirror is presented in Figure 11. The circuit was simulated
fifty times, to observe the variation of the current mirror gain with an input current range
of 0 to 200uA. In each run, every transistor was assigned a unique set of parameters by
the PSPICE Monte Carlo software according to the model parameters set forth in Table 3.
The PSPICE probe output of this simulation is included in Figure 12. In this simulation,
the input current was varied from 0 to 150uA. As there is a single minimum-geometry
input device, the current-density varied directly with the input current.
42
The data that was gathered from this simulation was distilled to yield the mean
percent error, standard deviation of the percent error, and the maximum (percent)
magnitude error. Graphs of these results are presented in Figure 13, Figure 14, and
Figure 15. From Figure 15, it can be determined that the optimum performance is
obtained from the current mirror in the neighborhood of 70uA of input current. Over the
range of input currents from 25uA to 90uA, the current mirror gain is within six percent
of unity. The five-bit DAC of Figure 42 has a PMOS cascode current mirror input, which
is constructed by placing four minimum-geometry mirrors in parallel. For the five-bit
DAC of Figure 42 constructed in a two-micron CMOS process, this indicates that the
reference current that will most reduce error in the few most-significant bits is 280uA.
The maximum error is of interest in the preliminary design of a current mirror based
DAC. This is because until a clear picture of the current mirror statistics is in hand a
worst case design approach can be used.
As a precursor to simulation of the complete DAC, a second Monte Carlo
simulation was performed on a cascode current mirror identical to the input stage of the
five-bit DAC of Figure 42. In this simulation, the input current range was scaled to 0 to
600uA in order maintain the same range of current densities as the previous simulation.
As there are four parallel minimum-geometry input devices, the current-density varied as
one-fourth the input current. The PSPICE probe output of this simulation is included in
Figure 16. The PSPICE input '.cir' file for the 4X current mirror is included in Appendix
G.
43
The mean and maximum gain error, as well as the standard deviation of the error
are presented in Figure 17, Figure 18, and Figure 19, respectively. As can be seen in
Figure 19, over the range of input currents from 100uA to 360uA, that the four times
minimum-geometry cascode current mirror gain is within 3.5 percent of unity. This is a
170 percent improvement in gain precision over the minimum-geometry cascode mirror.
Again, as in the case of the minimum-geometry cascode current mirror, an optimal
current of approximately 70uA is indicated for static operation.
The reason that the four times minimum-geometry cascode current mirror has
improved performance over the minimum-geometry version is embedded in the statistics.
The four times circuit in effect takes an average of four minimum-geometry circuits, each
behaving according to the same statistical (output current) distributions. While the mean
of the distribution remains the same, the standard deviation is divided by 42 (as predicted
by the law of large numbers 24). Also, the four mirrors in parallel present a lower output
resistance then the single mirror, and thus a more stable output current as output load
voltage changes.
In essence, the bell curve representing the normal distribution of the output currents
has become more peaked in case of the four times mirrors. Here the assumption is made
that the output current distribution is a normal distribution, which is generally a sound
assumption to make. Also, the further assumption is made that each device is statistically
independent. This in fact is not the case generally. However it is believed that at this
scale (minimum-geometry) most of the process effects contributing to current mismatch
44
are random edge effects, which are not dependent on mask fluctuations. This issue will
be discussed in greater detail in section 4.2.
45
geometry cascode current mirror
of minimum-geometry PMOS cascode
simulated PMOS minimum-geometry
cascode current mirrors
simulated PMOS minimum-geometry
cascode current mirrors
error in fifty simulated PMOS minimum-
geometry cascode current mirrors
four times minimum-geometry cascode
minimum-geometry cascode current mirror
four-times minimum-geometry cascode
times minimum-geometry cascode current
3.4 CONSIDERATION OF CURRENTLY AVAILABLE DAC ARCHITECTURES
A basic problem in the design of compact high-resolution, high-precision CMOS
digital-to-analog converters is the need for accuracy in excess of what can be achieved
with designs relying solely on matching of components in a standard CMOS process. A
solution to this problem is to provide continuous on-chip automatic calibration of each bit
in the DAC circuit.
Early attempts at applying self-calibration techniques to digital-to-analog, as well
as analog to digital, converters were limited to low-speed applications.25, 26 To apply the
techniques of automatic calibration to high speed DACs requires an understanding of the
pitfalls of high speed DAC design. Therefore, the basic design concepts, aside from self-
calibration methods used, will now be examined from a number of cases.
3.4.1 TYPES OF DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES
There are two primary categories of DAC architectures to be considered, voltage
switching and current switching. Voltage switching DACs are based on resistive or
capacitate selection networks. Using high-precision resistive and capacitate elements,
these networks will be intrinsically monotonic, thus lending themselves to construction of
56
DACs with a high degree of linearity. However, DACs so constructed will require a
large number of switches, large amounts of area, and post-process adjustment. Several
permanent post-processing options are available, such as laser trimming of resistors and
capacitors, or the selective destruction of zener diodes. Additionally, high-precision
linear resistors and capacitors are not available in standard digital CMOS processes. For
this reason, these component-matching based strategies will not be considered further.
DAC design methods which rely primarily on component matching include; ladder-
network digital-to-analog Converters, voltage divider digital-to-analog converters,
Shannon-Rack digital-to-analog converters, and charge Redistribution digital-to-analog
Converters.27
Alternative DAC design methods must now be considered to determine any that
will provide a significant increase in resolution without a disproportionate increase in
circuit area.
3.4.2 SWITCHED CURRENT DAC LAYOUT TO MINIMIZE ERROR IN CURRENT CELLS
The current switching DAC has been shown to be the topology with the highest
potential conversion rates. Examples include; an eight-bit 80 MHz DAC (1986) 28, a 10-
bit 70MS/s DAC 29 (1990), a 10-bit 50 MHz DAC (1990) 30, and a 10-bit 100 MHz DAC
(1994)31. Also, a current based DAC design is more compatible with circuits designed
and built in digital CMOS processes. The design of current switching DACs is a trade-
57
off among such factors as size, speed, and performance. It has been demonstrated that
the best way to ensure linearity in the design of a switched current DAC is to employ
combinations of identical current sources, each delivering a current value of one LSB, in
the construction of the necessary bits.32, 33 Examples include a 12-bit bipolar DAC
(1979) 34 and an 18-bit CMOS DAC (1994) 35. In such a design a primary factor
determining linearity is the management of the mismatch among the individual members
of the large set of current sources. These designs consume a large amount of area, and
therefore were not considered as design options for the small-area minimum-geometry
DAC design sought.
It has also been demonstrated that the fastest CMOS digital-to-analog converters
are built using a binary weighted current switching architecture which switches the
currents between an actual load and a dummy load 28, 29. A diagram of a single LSB
valued bit including dummy load switching is presented in Figure 20. In the research at
hand minimizing the size of the DACs is a priority. The operating speed demands are not
such that the use of dummy switching loads warrants the extra chip area required.
58
dummy load to optimize speed
59
3.4.3 CMOS LAYOUT TO MINIMIZE THE EFFECTS OF PROCESS VARIATIONS
A careful consideration of the elements which cause variations in the performance
of CMOS transistors led to the development of what will herein be called ‘statistical
DAC’ design.34 Statistical DAC design consists of the application of common-centroid
layout distributions combined with special switching strategies. It has been reported 29
that using this method, a 10 bit CMOS DAC with 70 MS/sec switching speed has been
constructed by applying the principles of statistical DAC design, however at the price of
a significant increase in circuit area.28
There are two basic types of error, symmetrical and gradient, for which statistical
DAC layout techniques can be effective. The principal mechanisms which contribute to
mismatch in CMOS circuits are; photolithography fluctuations, non-uniformity of etch
rate, contact resistance variations, ion-implantation non-uniformity, and sheet resistance
variations (often the result of temperature gradients).36
When a set of CMOS current sources is assembled in a line, the currents delivered
from these sources will often show a linearly graded distribution when operated at low
current levels.37 Primarily, gradient type error arises from oxide thickness variations.
Additionally, this type of error can be caused by a gradient change in doping level across
the area of the set of current sources.30 Various schemes for switching of bits
(constructed of multiple equal valued current sources) to combat both symmetrical and
60
gradient error have been proposed.29, 28 A symmetrically distributed layout combined
with symmetrical switching will eliminate the effects of gradient type error. The
characteristic of gradient error is depicted in Figure 21. In a symmetrically distributed
layout each bit in the DAC has its component one LSB current source parts located
symmetrically about a center common point. This is shown in Figure 23, as the ‘simple
symmetrical layout distribution’. Here, the numbers represent twin-pairs of transistors.
For example, 4a and 4b represent a single electrical device, separated into two identical
physical parts. In addition, the LSB, composed of only one current source, would be
located at the common center point. It has been shown 38, however, that while simple
symmetrical distribution and switching of the current sources compensates for gradient
type errors, it does not compensate for errors that are symmetrical in nature.
Symmetrical errors arise primarily from non-uniform thermal distributions over the
area of a circuit. These thermal variations arise primarily from differing current densities
across the area of the DAC. An example distribution of symmetrical error is presented in
Figure 22.
To correct for symmetrical error, a more radical layout distribution and switching
strategy has been utilized. This is shown in Figure 23 as ‘type a hierarchical layout
distribution’. Numbered a-b pairs represent the distributed current sources. The
symmetrical error cancellation is done at the current source level (distributed about the
quarter points of the set of sources), while the gradient error is canceled on the source-
pair level (distributed about the center of the set of sources). An example is the use of
61
current sources 1a-b and 2a-b as a pair of pairs to cancel error while constructing the bit
b2 = 4 x LSB (where the LSB is b0, and the MSB is bn). Another layout method is shown
in Figure 23 as ‘type b hierarchical layout distribution’. In this case the gradient error is
canceled at the current source level (distributed about the center of the set of sources) and
the symmetrical error is canceled at the current source pair level (distributed about the
quarter points of the set of sources). The application of the statistical DAC design
principles provides an important tool in overcoming the effects of statistical process
variations of the performance of large-area DACs fabricated in standard CMOS
processes.
62
set of current sources
in a set of current sources
63
However this method is does have shortcomings. Statistical DAC design principles
employ a switching strategy developed through an analysis of the uncorrected output of
an individual DAC. The main drawback to this scheme is the need to make a large set of
measurements for each individual DAC to be constructed. Having done this, the data
must be analyzed, and an individual switching algorithm must be designed for each chip.
Typically, the transistor distribution schemes are significantly more complex then the
one-dimensional examples given in Figure 23, often dividing each transistor into tens, if
not hundreds, of distributed parts. Not surprisingly, the emphasis in the development of
this approach has been to advance and employ efficient methods of measurement of data,
and more importantly, efficient methods for design of the switching algorithms.39
However, in a mass production application, a stand-alone self-calibration design would
be preferable.
There is evidence however that the statistical DAC design method are not effective
when applied to the design of small-area CMOS circuits.40 This evidence indicated that,
as long as a common orientation rule and a uniform direction of current flow (i.e. do not
swap drains and sources) was applied during layout, that statistical layout had no affect
on the performance of small area circuits. This is by virtue of the fact that as circuit area
shrinks, the factors contributing to mismatch for which statistical DAC design
compensates become less significant. For this reason, and to avoid the increase in chip
area, statistical DAC design methods have not been adopted in the design of thew small-
area minimum-geometry DAC for the CMOS bias bus.
64
To date, most statistical DAC design work has been done in bipolar processes. In a
bipolar fabrication, mask alignment fluctuations do not contribute significantly to device
mismatch. This is because the junctions of bipolar junction transistors rely on diffusion,
and not on mask alignment. In a CMOS process, all of the junctions rely on mask
alignment. In the case of minimum-geometry CMOS transistors, tiny mask alignment
fluctuations will be the dominant cause of transistor mismatch. It is probable that
fabricating the two-micron small-area minimum-geometry DAC structures in a 0.25-
micron process without scaling would yield a DAC with 10 bits of precision. The 0.25-
micron circuit would be the same physical size as the two-micron circuit, and thus the
0.25-micron devices would be eight times larger than minimum-geometry. In this case,
somewhat less than 10 bits would be realized by the large-area 0.25-micron DAC. With
devices eight times as large, it is possible that the symmetrical and gradient error would
dominate, in which case statistical DAC design would be useful.
65
schemes
66
3.4.4 CONSIDERATION OF TRANSISTOR MISMATCH IN THE DESIGN OF DACS
As the size of the CMOS transistors used is decreased mismatch of both threshold
voltage (VT) and transconductance (gm) becomes more pronounced, leading to a loss of
linearity in the DAC.41, 30 As an example, a value for the standard deviation of VT for
4um/4um p-type transistors in a 2.5um CMOS process has been calculated to be
8.75mV.42 Here the relation: σ( )T VTOV A
WL ≈ , has been used for the standard
deviation of VT (AVTO is a process dependent parameter). Using this value and the
equation: σ σ( ) ( )MSB m T nI g V= −22 , a value for the standard deviation of the
MSB current of a DAC consisting of simple current sources constructed of these
transistors can be determined.37 In the example of a 10 bit converter (n=10) with a full-
scale value of 20mA, the standard deviation of the MSB current is found to be 3.47uA, or
a worst case error of 1%. Increasing the length of the transistors to 16um (W/L =
4um/16um) would result in an increase in accuracy to 0.5%. (The use of more active area
to improve performance will be discussed in Section 4.4.) One common method used
extensively in circuitry requiring matching is to adopt an exclusive orientation of the
CMOS transistors used in the layout.43 This is generally accepted as a “golden rule” of
analog CMOS circuit design, and has been applied in the design of the small-area
minimum-geometry DACs. The common orientation rule must be applied with a
common current flow direction.
67
As an example of the application of common orientation layout rules, consider the
differential amplifier of Figure 24. An example of the application of the common
orientation layout rules, using a differential pair is presented in Figure 25. An alternative
layout for the differential amplifier, designed without applying common orientation
layout rules, is presented in Figure 26. Either of these layouts may have an advantage as
regards size or convenience of shape. However, the layout employing common
orientation layout rules will produce superior performance in terms of matching.
68
70
rules
71
A popular method of constructing high-precision DACs involves a calibrated
current source and an over-sampled five-bit DAC.35 The calibration circuitry for such a
DAC is presented in Figure 27. Here, the voltage Vnom, causes a constant current to flow
in M1 which is approximately 90% of the desired value, Ical. Upon closing M3 by raising
the voltage at its gate, and throwing the switch Scal to the Ical terminal, M2 is forced to
deliver a current equal to Ical -I(M1). After allowing enough time for the voltage at the
gate of M2 to settle, M3 is opened, and then Scal is thrown to the Iout termination. Cgs, the
gate-source capacitance of M2, then acts as a memory element to maintain the calibrated
current until the next calibration period begins.
The disadvantage of this DAC design is the presence of many high-frequency
components and the resulting intermodulation distortion resulting from the over-sampling
process. Extensive noise shaping, or delta-sigma modulation, must be performed to
confront this problem.25, 44, 45 Additional stability concerns arise in the implementation
of the delta-sigma modulators.46, 47 To realize the widest possible dynamic range from
this type of DAC, physical separation of the analog and digital circuitry onto a separate
die is necessary.48 The high-speed over-sampling and noise shaping digital circuitry
required in this scheme indicate that power consumption will be high. Therefore, do to
power dissipation and compactness goals, this scheme is not suitable for small-area
minimum-geometry DAC design.
sampled DAC
3.5 CHARACTERIZATION OF THE DAC CIRCUIT
The circuit topology used for the DAC portion of the bias bus system is that of the
simple current mirror DAC. This circuitry is scalable and has been shown to work
equally well in two-micron, 0.8-micron, and 0.5-micron CMOS.49 The basic circuit
element employed is the CMOS cascode current mirror. To achieve compactness, only
minimum-geometry devices have been used in the design. A reference current must be
generated for each output bit of the converter. One solution is to introduce a reference
current to the circuit, equivalent to the least-significant-bit and successively multiply this
reference by two to obtain all the necessary reference currents. The use of a divide-by-
two scheme produces a converter with a more acceptable level of error in the bits than
does the multiply-by-two arrangement, as successive multiplication produces
geometrically increasing noise and error components.
3.5.1 MONTE CARLO ANALYSIS OF THE SELECTED DAC TOPOLOGY
Monte Carlo analysis has been performed on the chosen DAC topology to predict
actual performance variations of the circuits to be fabricated. The results obtained from
simulation of the cascode current mirror circuit established a basis for device current
densities to be used throughout the two-micron five-bit DAC design. An image of the
two-micron DAC layout is presented in Figure 28.
74
Device tolerance statistics that were compiled locally from exhaustive statistical
testing were used for this analysis.23 In general, the results of this simulation showed that
the circuit was fairly insensitive to process parameter variations. This ultimately
conformed to measured experimental data, in which all of the fabricated five-bit
converters worked as predicted by the simulations. Figure 29 presents the results of the
Monte Carlo analysis performed on a five-bit converter. Each curve represents the same
DAC circuitry run with a different set of CMOS transistor parameters. To determine if a
DACs behavior is monotonic, the step size from one binary input to the next must be
examined. If the DAC is monotonic, all step sizes will have the same algebraic sign. For
the DAC outputs of Figure 29, the step sizes are presented in Figure 30. The DACs
simulated each exhibit monotonic behavior.
The maximum error, as indicated in Figure 33, is 3.8uA. The full-scale current in
the DAC in this case was 250uA, indicating an LSB value of 7.813uA. Ideally, the
maximum error should be less than one-half of one LSB. In this case, a ratio of 0.486
was achieved. This indicates that consistent yield of useable five-bit DACs should be
possible with the chosen design, in the two-micron CMOS process.
75
micron DAC
of two-micron five-bit converter
two-micron DACs
two-micron five-bit DAC
simulation of two-micron five-bit DAC
80
81
of two-micron five-bit DAC
3.5.2 CHARACTERIZATION OF THE ORIGINAL DAC CIRCUIT IN A 0.8-MICRON CMOS
PROCESS
The first important issue to be resolved was how many bits of precision can be
expected from the CMOS process. A single cascode current mirror, while simple, has
been the most important test structure fabricated. This is because the basic cascode
current mirror is used throughout the converter and therefore will have a large influence
on the precision of the converter.
The design constraints are to use only simple circuitry, minimum-geometry
devices, and the 0.8-micron CMOS process. 0.8-micron converters with from five to 13
bits were fabricated to study the effect of cumulative error due to the successive division
of the reference current necessary in the chosen topology. The 0.8-micron 13-bit
converter samples allowed measurement of the effects of the switching elements on
converter performance. While 13 bits is far beyond what one can hope to achieve from
an uncorrected small-area digital-to-analog converter in the short channel CMOS
processes 22, the test structure provides necessary insight into what process variations
must be taken into account. A photograph of the fabricated 0.8-micron DAC test
82
structures is presented in Figure 34. These test structures included several variations of
the basic cascode current mirror used, as well as five, nine, and 13 bit DACs.
The initial fabrication included several DACs with varying numbers of bits. The
most important, in terms of characterizing the chosen DAC topology, was initially the
seven-bit DAC. An image of the layout of the seven-bit DAC is presented in Figure 35.
A schematic diagram of the seven-bit DAC circuit is presented in Figure 36.
Figure 37 displays the measurements made on four DACs, each with seven bits,
which were fabricated in the 0.8-micron CMOS process. This original converter design
had an output current summing circuit. This accounts for the fact that the full-scale
output current is not equal to twice the reference current. This output summing circuit
was abandoned in the final design.
As can be seen from a qualitative examination of Figure 37, the gross error, and
thus the non-monotonic behavior of the seven-bit DAC are most evident in the MSB and
the second most-significant-bit. The jump at the midpoint of the DAC curves is due
primarily to the switching of the MSB, with a significant contribution from the switching
of the second most-significant-bit. The two jumps at the quarter points of the curves are
due to the switching of the second most-significant-bit. The remaining, relatively flat
sections of the plots represent inherently monotonic five-bit sections. This information
established the premise that acceptable minimum-geometry devices for digital circuit use
in mature CMOS processes requires a tolerance that tends to yield a small-area
83
minimum-geometry DAC of about five bits. It of course remained to demonstrate this
experimentally. A more complete record of the measurements made on the seven-bit
DACs are included in APPENDIX A.
The results obtained from the 0.8-micron test structures have been used by another
researcher to perform an extensive statistical study in a 0.5-micron process. That study
ultimately supported the conclusion of the 0.8-micron study.49
Results of measurements made on a typical five-bit converter from this 0.8-micron
fabrication run are presented in Figure 38. The straight line in Figure 38 is a best-fit line
to the output of the actual DAC. The X-axis in this figure represents the binary DAC
input, while the Y-axis represents the DAC current output (in amps). Results for a six-bit
converter are presented in a similar format in Figure 39.
The resolution of the measured five-bit DAC can be determined from the DAC
output current error. Here, the error is defined as the difference between the actual DAC
output and a best-fit line. This error is presented for the five-bit DAC in Figure 40, and
for the six-bit DAC in Figure 41. The X-axis in both figures represents the binary DAC
input, while the Y-axis represents the error.
The maximum allowable error in a DAC is typically defined as one-half of one
LSB. In the case of a five-bit DAC, this translates to 3.125%. The basic cascode current
mirrors measured exhibited a mean error of well below the 3.125% needed to construct
the five-bit DAC circuit.
test structures
micron DAC
micron seven-bit DAC
88
on a typical five-bit converter in the 0.8-
micron test fabrication
on a typical six-bit converter in the 0.8-
micron test fabrication
typical 0.8-micron five-bit converter
typical 0.8-micron six-bit converter
92
93
3.5.3 FURTHER DESIGN CHOICES FOR THE 0.8-MICRON CMOS PROCESS DAC DESIGN
The design ultimately chosen for the DAC circuitry of the bias bus was developed
at the time when the 0.8-micron CMOS fabrication process first became available to the
Georgia Tech Analog Design Group. In fact, the original design of Figure 36 was
intended for fabrication in a two-micron CMOS process. The decision to move
immediately to the 0.8-micron CMOS process was made when funding became available.
In moving from the original DAC design to a new 0.8-micron design, a much more
compact and simpler DAC was developed. This new DAC uses the same basic circuit
element as the two-micron design, the simple cascode current mirror. Whereas the
original DAC design was expandable to any number of bits, the new design gives up this
expandability feature. Therefore, the new design is only able to deliver five bits. The
simpler circuit allows the elimination of several current mirrors, and results in a circuit
with improved performance.
A schematic of the basic DAC cell used is presented in Figure 42. Here, the MSB
control of the DAC is labeled ‘b4’, and the LSB control is labeled ‘b0’. A current, Iref , is
supplied to the DAC, and sets the values of the individual bits. The MSB will have a
value approximately equal to Iref, while the LSB of the five-bit DAC will have a value
approximately equal to 1/24(Iref). The nth bit has a switch associated with it, which
controls the output state of the bit according to the state of bn. The converter uses
negative logic. This means that the minimum output is obtained by setting the bits b4
94
through b0 to the binary value 11111, while the binary value 00000 yields the maximum
output. The five-bit DAC will have an output range from zero to approximately twice
Iref, in steps of [1/(24)](Iref).
The extra single cascode current mirror outputs (the 1/8(I) valued PMOS and the
1/16(I) valued NMOS ‘bits’ without switches) are used to null the current when the input
code is set to 11111. In this stare, b4, b3, and b2 will be off, and b1 and b0 will be on.
Then the output current will be I(+1/8 –1/16 –1/16) which equals zero. The optimum
output load is 2.5 Volts D.C., but the converter will function over a range of output
voltages from one Volt D.C. to four Volts D.C. while satisfying the previously defined
error requirements. The DAC uses a single five Volt D.C. power supply.
95
bit digital-to-analog converter cell
96
3.5.4 CHARACTERIZATION OF THE NEW DAC CIRCUIT IN A 0.8-MICRON CMOS PROCESS
After Monte Carlo analysis of the several DAC circuits, with varying numbers of
bits, it was predicted that the resolution of the largest stand-alone, uncorrected, Digital-
to-analog converter exhibiting acceptable error characteristics that can be built within the
design constraints is five-bits. Again, these constraints are to use only simple circuitry,
minimum-geometry devices, and the 0.8-micron and smaller CMOS processes. This
conclusion was borne out by statistical analysis of the measurements made on 16
individual fabricated 0.8-micron chips. (A photograph of the fabricated chip is presented
in Figure 51, in section 4.2 Limitations on the Application of the Technique of
Overlapping DACs.) An image of the five-bit 0.8-micron DAC layout is presented in
Figure 43. This circuit occupies a chip area of 42.5 microns by 145 microns (34λ by
181λ). A schematic for the five-bit 0.8-micron DAC was presented in Figure 42.
Results of measurements made on a typical five-bit converter from this 0.8-micron
fabrication run are presented in Figure 44. The straight line in Figure 44 is a best-fit line
to the output of the actual DAC. The X-axis in this figure represents the binary DAC
input, while the Y-axis represents the DAC current output (in amps). The DAC had a
full-scale output current of approximately 90uA.
The resolution of the measured five-bit 0.8-micron DAC can be determined from
the DAC output current error. Here, the error is defined as the difference between the
actual DAC output and a best-fit line. This error is presented for the five-bit DAC in
97
Figure 45. The X-axis in this figure represents the binary DAC input, while the Y-axis
represents the error (in amps).
The maximum allowable error in a DAC is typically defined as one-half of one
LSB. In the case of a five-bit DAC, this translates to 3.125% The DACs measured
exhibited a mean error of well below the needed to construct the five-bit DAC circuit. In
the typical example of Figure 45, the maximum error was 1.04%. The error in the set of
30 measured 0.8-micron five-bit DACs is presented in Figure 46. The error is plotted for
a family of DAC reference currents, distributed along the x-axis. Note that the DACs
should be operated with at least 45uA of bias current to ensure that DAC error is below
3.125%. The increase in error at low levels is addressed in section 4.2 Limitations on the
Application of the Technique of Overlapping DACs. The maximum error for a family of
bias currents in 30 measured five-bit 0.8-micron DACs is included in APPENDIX B.1.
The measured output currents for the same set of DACs biased at 50uA is included in
APPENDIX B.2.
From this data, an important conclusion can be drawn. This applies to the
fabrication of minimum-geometry small-area digital-to-analog converters in the short
channel CMOS processes. In such a case, the largest DAC that can be built reliably with
less than ½ of one LSB error is five bits.
98
DAC
99
0.8-micron five-bit DAC, along with a
best-fit line
five-bit DAC
measured set of 30 0.8-micron five-bit
DACs
4.1 THE OVERLAPPING DAC SCHEME
As discussed above, the CMOS processes of interest allow for only five bits of
resolution in digital-to-analog converters constructed exclusively with minimum-
geometry devices and a minimum of area. To meet the demands of designs requiring
greater resolution, an overlapping DAC scheme will be employed. The approach here is
to use multiple five-bit DACs, with appropriately scaled reference currents, such that
both the magnitude and resolution requirements of the supported system are met. Often
in this research it has been required, in support of other circuits and systems, to operate
the digital-to-analog converters as individual five-bit units. In this situation, the full-scale
output current has typically been around 145uA. This has been to accommodate a
nominal bias current of 100uA, while providing the necessary range resolution and
headroom. For a full-scale output current of 145uA, the reference current supplied to the
each five-bit DAC must be approximately 75uA. This provides 30-two possible bias
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currents, which can be varied from approximately zero to 145uA in steps no greater than
5uA.
The second most common application has required considerably more precision
than 5uA per step. To provide the additional resolution, while maintaining the required
range, the overlapping DAC technique has been applied.
4.1.1 AN EXAMPLE APPLICATION OF THE OVERLAPPING DAC TRIMMING SCHEME IN 0.8-
MICRON CMOS
As an example, consider the case of a 0.8-micron digital-to-analog converter with
11 bits, constructed using only the simple topology of the basic five-bit DAC of Figure
42 (page 95). Such a converter has been fabricated and measured as part of the original
0.8-micron test structures chip of Figure 34 (page 84). The 11 bit DAC is simply an
extended version of the basic five-bit DAC of Figure 42. The results of measurements
made on a 0.8-micron eleven-bit DAC are presented in Figure 47. Also included is a
superimposed “target slope” line. This line represents an ideal eleven-bit converter that
could be constructed by adding additional current at each point on the actual DAC output
curve. The error in this case is always positive, as it is the difference between the target
slope line and the actual eleven-bit DAC output. This error is presented in Figure 48.
In order to make this eleven-bit DAC more accurate, corrections to the measured
output currents must be provided. These correction currents are essentially the inverse of
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the output current errors. A circuit capable of delivering the range of currents defined by
the error in the eleven-bit DAC must be provided.
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performed on a typical eleven-bit converter
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line, in the eleven-bit converter
The range of error for which correction must be provided must now be defined.
From Figure 48, the largest supplemental current that must be provided to correct the
eleven-bit DAC output is 24.1uA. Taking twice this value, as a design safety margin, this
example will provide for correction currents as large as 48.2uA. The LSB for the eleven-
bit converter was 0.26uA, and the MSB was 269uA. The smallest error for which
correction must be provided is defined to be less-than-or-equal-to one-half of the LSB of
the eleven-bit converter, or 0.13uA.
It is intended that this case be viewed as a specific example of the technique. The
eleven-bit converter is used here as an example system requiring correction. Any number
of systems could be used to demonstrate the technique, however the eleven-bit DAC is
both appropriate and convenient to this research. The general case will be presented in
the following sections. There the appropriate statistical analysis will be presented
relevant to the generalized application of the overlapping DAC technique using multiple
five-bit converters exclusively.
The system architecture consists of two main elements. The first is a converter of
11 bits which lacks precision beyond the five bits of resolution available from the 0.8-
micron (or shorter channel) CMOS process. To increase the resolution of this converter,
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a second section is added, consisting of several five-bit converters in parallel. The 0.8-
micron five-bit correction converters each have a different reference current, to allow for
correction of the entire range of errors inherent in the main eleven-bit converter. These
reference currents have been determined by observing the range of errors that must be
corrected for in the main eleven-bit converter. The outputs of the main and correction
segments are then summed to produce the linearized output. The correction converters
must provide the additional current to bring all main eleven-bit DAC output levels up to
within less than an LSB of a “target slope” line.
Figure 49 shows graphically how the two linear five-bit converters are used to
correct over the range of errors present in the eleven-bit converter. The reference
currents for the correction DAC cells were chosen to exceed the necessary correction
range. Additionally, the reference currents were selected to fall on a value which was an
integer multiple of the reference current of the main eleven-bit cell. This is done to
facilitate the synthesis of the necessary reference currents using current-mirror division.
The reference current of the main eleven-bit converter is 133uA. The precise value of
reference current in the five-bit DACs is not important, as long as together they span the
‘error space’ of the eleven-bit converter. The reference current of the fine and course
five-bit correction DACs is 1.6uA and 26.9uA, respectively. The overall architecture of
the corrected eleven-bit DAC converter is presented in Figure 50.
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example converter overlap scheme
scheme
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A testing-training scheme is employed to establish proper correction for the
Digital-to-analog converter. This consists of initially measuring the input-output
relationship of the main converter, with all correction bits off. The pre-determined
“target slope” line is then employed to determine the corrections necessary. Finally the
necessary correction currents are generated using the correction DAC elements, and, after
being confirmed, written to ROM. During actual use, the ROM serves to map the inputs
of the main Digital-to-analog onto those necessary for the correction segment of the
Digital-to-analog to linearize the overall converter performance.
4.1.2 EXPERIMENTAL PRECISION OF OVERLAPPING DACS IN 0.8-MICRON CMOS
30 DACs with five-bit architecture fabricated in support of a project for the
Lockeed-Martin Corporation were measured. In this case, a large bipolar integrated
circuit required off-chip adaptive biasing to trim the individual bits of a large, high-
resolution analog to digital converter. The specifications were to trim reference inputs
such that output bits attained 14 bits resolution. These DACs were fabricated through the
MOSIS service, in the HP 0.8-micron digital CMOS process. A photograph of the
fabricated CMOS bias-support chip is presented in Figure 51.
The measurements of this chip were performed using a personal computer
controlling a National instruments DIO-96 card and a GPIB bus interface card. The DIO-
96 is a 96 digital input/output card designed to work with a standard PC motherboard.
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The DIO-96 was used to provide all of the digital control to the chip during testing. The
GPIB card was used to control several Kiethly Source-Measure units. National
Instruments Lab-View software was used to control the measurement process. A
screen capture of the Lab-View program written to control these measurements is
included in Appendix B.3.
The power consumption and operational specifications of the system in this
application set the possible range for the CMOS Bias-Bus. The maximum input of the
DAC current reference for the Bias-Bus is 60uA. The Bias-Bus chip in Figure 51 has 64
adjustable bias-source outputs. In this particular application, a 10-bit parallel data bus
input was specified. Each bias cell is comprised of a two five-bit DACs and a ten-bit
wide memory-register. The outputs of the DACs are connected in parallel to the output
pad. The inputs to the two converters are delivered from the ten-bit data-bus by way of
the ten-bit memory register. The two DACs are paired together to construct an
overlapping DAC. The current references for the two converters are derived from a
current source delivered from the supported bipolar chip. The bipolar reference current is
adjustable by means of a thermometer code DAC on the CMOS chip. Adjustment is
provided for both of the reference currents provided to the overlapping DAC. In testing,
a pair of external connections was utilized to inject precision currents to facilitate rapid
automated testing of all 128 five-bit DACs on the chip.
As stated above, the maximum input current is 60uA. This is equivalent to a
current-density of 15uA in the input current mirrors of the DACs. An increase of input
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current-density to as high a figure as 85uA (340uA input current) will produce improved
DAC linearity. However, nothing will be gained that the overlapping DAC cannot
accomplish at the lower current level. Power consumption is another factor to be
considered before increasing the input reference current. A good estimate of the
maximum power consumption of the chip can be obtained from an examination of an
individual output cell. In one output cell, the DAC with the larger input current will at
maximum contribute approximately twice the input reference current to the output. The
DAC with the smaller reference current will contribute approximately one-eighth of that
value. An estimate of the maximum current consumption (at five volts D.C.) is then
(1+(1/8))(64)(Iref). For the input reference value of 60uA this becomes 4.32mA. If the
input current were increased to 340uA, this figure becomes 24.48mA. Of course these
are only maximum possible values, and it is unlikely that all of the bias sources would be
called on simultaneously to deliver maximum current.
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CMOS bias-support chip
115
From a large set of data collected from this chip, one set of DAC measurements
was chosen at random for the purpose of investigating the overlapping DAC correction
scheme. Each of the 64 DACs was measured with 18 bias currents ranging from
0.125uA to 60uA. A sample DAC measurement with 50uA bias current was chosen as
the largest DAC in this particular experiment. This gives a theoretical LSB and hence a
theoretical maximum step size of 3.125uA. The input-output relation of this five-bit
DAC was presented in Figure 44, where ‘Series 2’ is the DAC output current, and ‘Series
1’ is a “best-fit” line to the measured data. The error from a best-fit line for this DAC
was presented in Figure 45. This error is defined as the percentage difference between
the actual and best-fit data. The maximum step size in the sample five-bit DAC was
found to 3.88uA. This indicates a ‘dead zone’ between levels in the main DAC, which
can be reduced by adding another DAC with smaller bias current.
A second DAC was chosen at random from the set of data to be used for correction.
For this second, or correct