IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 1

An Extended CMOS ISFET Model Incorporatingthe Physical Design Geometry and the Effects on

Performance and Offset VariationYan Liu, Student Member, IEEE, Pantelis Georgiou, Member, IEEE, Themistoklis Prodromakis, Member, IEEE,

Timothy G. Constandinou, Senior Member, and Christofer Toumazou, Fellow, IEEE

Abstract—This paper presents an extended model for theCMOS-based Ion-Sensitive-Field-Effect-Transistor (ISFET), in-corporating design parameters associated with the physicalgeometry of the device. This can, for the first time, provide agood match between calculated and measured characteristics bytaking into account the effects of non-idealities such as thresholdvoltage variation and sensor noise. The model is evaluatedthrough a number of devices with varying design parameters(chemical sensing area and MOSFET dimensions) fabricated ina commercially-available 0.35µm CMOS technology. Thresholdvoltage, subthreshold slope, chemical sensitivity, drift and noisewere measured and compared to the simulated results. Thefirst and second order effects are analysed in detail and it isshown that the sensors’ performance was in agreement with theproposed model.

Index Terms—ISFET, CMOS, geometry, drift, noise, chemicalsensor, threshold voltage, subthreshold slope, passivation capac-itance

I. INTRODUCTION

THE Ion-Sensitive-Field-Effect-Transistor (ISFET) wasfirst introduced by Bergveld in the 1970s [1] and sincethen has been used widely in numerous sensing applications[2]–[4]. In recent years, the ISFET has been implementedin commercially-available CMOS technologies [3], [5]. Im-plementation in CMOS is highly desirable due to the ad-vantages of significantly reduced manufacturing complexityand therefore cost, as well as the option for integration, i.etogether with instrumentation or in large sensor arrays [4],[6]. However CMOS based ISFETs suffer from a numberof non-ideal characteristics [3], [7]–[9], such as thresholdvoltage variation, drift and noise. In recent years there hasbeen increasing interest in investigating the source of theseeffects and although the fundamental underlying mechanismsare understood, there has been little effort in characterizing andminimizing these [7], [9], [10]. Furthermore, although ISFETshave been fabricated in CMOS for a variety of physicalgeometries [5], [7], [11], [12], it has not yet been reportedhow design dimensions impact sensor characteristics. This isa key challenge in designing chemical sensors with reduceddimensions, which are particularly useful in applications such

Manuscript received XXX, XXX; revised XXX, XXX.All authors are with the Centre for Bio-Inspired Technology, Department of

Electrical and Electronic Engineering and Institute of Biomedical Engineering,Imperial College of Science, Technology and Medicine, London SW7 2AZ,United Kingdom. (e-mail:yan.liu06@imperial.ac.uk)

as large-scale, highly-integrated chemical sensor arrays [4],[6].

In this paper we present an extended model for CMOS-based ISFETs to include both the first order effects, (i.e.intrinsic dimension-related characteristics) and second ordereffects, (i.e. non-linear characteristics). By focusing on theeffect of varying the design parameters (i.e physical dimen-sions) a capacitance-based model is derived which includes allcapacitive structures, the values of which are directly relatedto physical dimensions. Based on this, threshold voltage,subthreshold slope, chemical transconductance, drift and noiseare analyzed to establish a extended model for CMOS ISFETs.A test chip, including six specific devices with varying core-MOSFET (W/L) and the chemical sensing area (Wc/Lc) hasbeen prototyped to evaluate this model. The measured resultsdemonstrated a good agreement between the proposed modeland the performance of fabricated sensors.

The paper is organized as follows: Section II proposes theextended CMOS ISFET model incorporating all the designparameters, while Section III explains the research method-ology and the sensors implementation. Section IV presentsmeasured results with detailed discussion on both the firstand the second order effects. Finally Section V concludes thisstudy and indicates how this model can aid sensor and readoutcircuit design with reduced calibration effort.

II. AN EXTENDED CMOS ISFET MODEL

A. Overview

Traditionally, ISFETs devices have been fabricated as MOS-FET devices with the gate metal and oxide being replacedby an insulating sensing membrane [1]. CMOS ISFETs arefabricated by extension (i.e. electrical connection) of the MOS-FET poly-silicon gate (IPG) to the top metal layer [3], [5],utilizing the intrinsic passivation as the sensing membrane, asillustrated in Fig. 1. Compared to an intrinsic MOSFET device,a CMOS-ISFET is essentially a floating-gate MOSFET withone floating remote gate voltage influenced by the referencevoltage and electrochemical potential. Therefore in a similarmanner to the MOSFET model, the drain current of theISFETs can be represented as a function of the floating gatevoltage VFG and design dimensions [10]. VFG is modulatedby the chemical potential Vchem and the voltage bias appliedon the reference electrode. Vchem is a combination of thepotential drop between the interface and pH induced potential,

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 2

Fig. 1: CMOS ISFET structure.

as given in [3]. Since the potential of the reference electrodemust remain constant with varying pH, the potential across theelectrolyte-insulator is the only value influenced by change inpH [3].

The chemical gate voltage, and the electrical terminalvoltages are coupled to IPG via different series of capaci-tors. These capacitors exhibit non-linear effect on the overallsensor performance such as variation of capacitance [12]and trapped charge [13], [14]. Among them, passivationcapacitance (Cpass) is of great importance, it couples thechemical potential and then influence sensor chemical re-sponse directly. In [10], a basic CMOS ISFET model basedon passivation capacitance for weak inversion was proposedillustrating transconductance efficiency reduction compared tothe corresponding MOSFET characteristic. In this work, wedevelop a more complete model that focuses on the impactof the stacked capacitance on the sensor characteristics andthe relationship between capacitance and design dimensions(W/L and Wc/Lc).

Fig. 2 illustrates the proposed model that incorporates thevarious capacitances including trapped charge to analyze theelectrical performance of the devices. The parameters aredetailed in Appendix A. This model includes both the intrinsicand parasitic capacitors and provides a clear relationshipbetween biasing voltage and floating gate voltage. We inten-tionally omit the parasitic capacitance seen from either floatinggate or passivation to the channel, since this capacitance isrelatively small compared to the gate-oxide capacitance and istherefore negligible. The faradaic impedance of the electrolyteand reference electrode is also neglected in this model, sincethey have negligible effect on the electrical performance ofthe devices. Parasitic capacitances coupled to the floating gateinclude two parts: overlap capacitance within the transistor,and extrinsic parasitics caused by extended metal gate(EMG).The first value is embedded within the MOSFET model, whilethe second term can be extracted by either simulation tools

Fig. 2: CMOS ISFET stack capacitors model

or experiments [15]. At the passivation node the parasiticcapacitances can be estimated by the simple parallel platecapacitor model, resulting in a relatively smaller than thechemical capacitance CGouy and CHelm [10], [16].

When modelling the passivation capacitance of an ISFET,a simple parallel plate capacitance model is not sufficient,since the corresponding fringing fields are considerably largedue to the large metal to dielectric thickness ratio. Detailedanalytical derivation is beyond the scope of this paper. Instead,we used a finite element analysis tool (Ansoft Maxwell 3D)[17] to simulate a simple chemical sensing area model, usingSiO2 and Si3N4 as the dielectric medium and two aluminiumplates as the electrodes, representing the floating metal andelectrolyte. Depending on the FEA (Finite Element Analysis)results, the passivation capacitance for a common CMOStechnology with SiO2 and SixNy as passivation layer canbe simplified to:

Cpass =CSiO2 + CSixNy

=εSiO2εSixNy

εSiO2dSixNy + εSixNydSiO2(WcLc)

β (1)

Where εSiO2 and εSixNy are the dielectric constant, d is thethickness for corresponding layers and β is the chemical areascaling factor due to non-linear effect such as the fringing field.Therefore, the drain current of ISFETs can be represented by afunction of design dimensions, biasing, ion concentration (i.e.pH in this paper) and ISFET threshold voltage:

ID = f(W,L,WC , LC , VD, VS , VB , Vref , pH, VthISFET )(2)

In order to incorporate the sensors into a measurement system,the threshold voltage, transconductance, drift and noise arerequired for readout or calibration circuits design, and will bediscussed in the following sections.

B. Threshold Voltage

The ISFET threshold voltage VthISFET is defined as theremote gate to the source voltage required for turning on theunderlying transistor. This value, however, commonly exhibitsa non-pH related large threshold voltage variation [3], [10].This can prevent its operation when standard supply voltagesare used, in addition to limiting output resolution and accuracy.Reasons for this effect are reported to be due to trapped chargeeither within the passivation layer and/or the EMG connected

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 3

For the passivation:

Cpass(VFG −Vpass) +Cchem(Vref +Vchem −Vpass) +Cps(VS −Vpass) +Cpb(VB −Vpass) +Cpd(VD −Vpass) +Cpsub(Vsub −Vpass) = QTCp (3)

QTCp is the trapped charge within the passivation; Vpass is the potential drop across the passivation layer; Vref is the reference voltage in bulk solutionand Vsub is the substrate voltage.

For the floating gate:

Cpass(Vpass − VFG) + Cfgs(VS − VFG) + Cfgd(VD − VFG) + Cfgb(VB − VFG) + Cfgsub(Vsub − VFG) + Cox(ψsa − VFG) = QTCfg (4)

QTCfg is the trapped charge within the floating gate; ψsa is the surface potential of the channel.

VFG = [(Cchem(Vref + Vchem) +∑

CiVi +QTCp)Cpass

CTp+

∑CjVj +QTCfg]

CTp

CTpCTfg − C2pass(5)

Vth−ISFET =Vth−MOSFETCTfgCTCp

CchemCpass︸ ︷︷ ︸MOSVth contribution

+(V sCTfg −

∑CjVj)

CTCpCpass

−∑CiVi

Cchem︸ ︷︷ ︸Parastic contribution

−QTCfg

CTCpCpass

+QTCp

Cchem︸ ︷︷ ︸Trapped charge contribution

+ κ︸︷︷︸Chemical contribution

(6)

to the IPG [11]. UV irradiation [18] and hot electron injection[11] have been used to remove this and thus reduce anythreshold mismatch.

In order to determine the origin of the threshold voltagevariation, charge equilibrium is established on the floatingnodes (both the floating gate and passivation), as describedin equations (3) and (4), then the floating gate voltage of thedevice was derived, shown in Eq. (5). The floating gate voltageVFG and threshold voltage for the MOSFET Vth, as describedin [19], can be combined to form Eq. (6). It should be notedthat the pH-related term is accounted for in κ, which containsVchem and Cchem [20], [21]. In this section only the firstorder DC characteristics are considered and therefore it canbe assumed that κ and Cchem are constant.

From Eq. (6), it can be seen that the four factors influencingthe threshold voltage of the device are: the intrinsic Vth ofthe MOSFET enhanced by the capacitance ratio, the parasiticeffect of constant biasing due to floating gate nodes, thetrapped charge within both the floating gate stack and thepassivation; the chemical related constant κ. Simulated resultsusing the proposed model with a sensor dimension of 10 µm× 10 µm are shown in Fig. 3. It can be found that for largechemical area and terminal voltages, the VthISFET increasesnon-linearly.

Fig. 3: Threshold voltage simulation results. The solid linesshow Vth change with regards to VD and chemical dimensions,when VS=3.3V for a 10µm × 10µm electrical area.

C. Transconductance and Subthreshold slope

Due to the existence of passivation capacitance, thetransconductance of ISFETs seen referring to the remote gateare scaled down compared to MOSFETs with identical designdimensions. By combining Eq. (5) and transconductance insaturation for MOSFET [19], the transconductance of ISFETcan be derived as:

gmISFET = k′ CchemCpassCTpCTfg − C2pass

W

L(7)

By assuming that the depletion capacitance remains constant indeep weak inversion, the subthreshold slope can be representedby:

Sub slope =dVGS

d(log IDS)=

dVGSdVpass

dVpassdVFG

dVFGd(log IDS)

= 2.3nUt(CTpCchem

+CpassCchem

CpassCTfg

)CTfgCpass

(8)

D. Chemical Transconductance

In addition to electrical transconductance reduction, thechemical transconductance is scaled compared to custom IS-FET sensors [22], which is given by:

gpH = 2.3αVtk′ CchemCpassCTpCTfg − C2pass

W

L(9)

where α is the scaling factor due to double layer model [16].This value indicates a non-linear reduction effect betweenthe chemical transconductance of CMOS ISFETs and custommade ISFETs .

E. Drift and Noise

Due to the poor quality of the passivation layer as sensingmembrane, CMOS-based ISFETs suffer from many non-idealeffects, including: drift, noise and temperature instability. Thedrift mechanism has been described as the dispersive trans-portation [9], also combined with other effects, such as leakageacross the reference electrode [8]. In general, the variationof the surface hydrated layer thickness changes the effective

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 4

thickness of the passivation, hereby altering the potential dropacross the insulator:

∆VG(t) = −

(εins − εSLεinsεSL

)χSL(t)

∑Q (10)

where∑Q is both intrinsic and trapped charge in this

structure, εins and εSL are the dielectric constants of pHsensing membrane and modified layer respectively, while χSLrepresents the depth change of this layer. This change isessentially applied at the remote gate, which can be combinedwith Eq.(7), causing long term sensors output drift.

Although ISFET thermal noise is present in a wide spec-trum, within the chemical signal spectrum, the flicker-likenoise dominates and alias slow chemical response. Low fre-quency noise is studied in [7], [8], [23], in which a 1/f noisepattern was found when the gate leakage is lower than 1nA.It was stated that the measured noise indicates the intrinsicMOSFET noise, provided the gate leakage through the refer-ence electrode was minimal [8]. Moreover, it is believed thatthe ISFET has similar noise power compared to the MOSFETflicker noise [8].

In similar fashion to CMOS MOSFETs, we propose thatISFETs flicker-like noise is due to both intrinsic channel flickernoise and chemical noise:

V 2n (ISFET ) = V2n (MOSFET ) + V

2n (Chem)

= (CTfgCpass

)2Kf

WLC ′oxf+K

f

(11)

Where K is the chemical related effect due to long-termelectrode degradation and surface chemical noise. A qualitativestudy is provided in section IV.

III. METHODOLOGY

In order to evaluate the proposed model, a series of CMOSISFETs with varying transistor channel size and chemicalsensing area need to be fabricated and measured. Since thepassivation capacitance is the essential parameter, Eq. (1)can be evaluated by Cpass calculated by the subthresholdslope using Eq. (8), whilst the parasitic and gate insulatorcapacitance are either simulated or measured from fabricateddevices. The threshold voltage of individual sensors can thenbe derived using the proposed model and compared against themeasured results. Evaluation of drift and noise characteristicscan be performed by long-term measurement. FurthermoreMOSFETs of comparable same electrical dimension need to befabricated on-site to provide an authoritative comparison withthe traditional MOSFET model. The two following subsectionsdetail the methodology with respect to the sensor developmentand experimental setup.

A. Sensor Implementation

All ISFET devices presented in this paper have been fab-ricated in a commercially available 0.35µm 2P3M CMOStechnology. P-type MOSFETs have served as the core devicesfor all ISFETs for establishing a VSB = 0 to minimizeany body-effects. A continuous metal stack has been used tocouple the IPG to the top metal layer [5]. The passivation

layer of this technology, consisting of SiO2 and SixNy , wasused to sense pH Eq.(2) with total thickness of 2 2µm. Forcharacterization purposes, all the bulk and source terminalswere tied together in a common source terminal. This schemehas been employed since the drain current is the only quantityrequiring investigation.

Two sets of electrical dimensions and three sets of chemicaldimensions have been used, resulting in a total of six differentcombinations. To distinguish between the various sensors,the devices were labelled as shown in Table I. Fig. 4 is athe microphotograph of the fabricated sensors with Fig. 4.bshowing the cross section. The pitch between adjacent sensorshas been set to twice the chemical dimension to minimize anycrosstalk. MOSFETs of identical dimensions have also beenfabricated on the same die.

Fig. 4: Microphotograph of Chip layout

TABLE I: ISFETs dimension and name codingElectrical W×L ISFET devices short names MOS

100 × 1µm2 D1 1 D1 2 D1 3 PMOS 110× 10µm2 D2 1 D2 2 D2 3 PMOS 2

Chemical Wc × Lc µm2 10× 10 100 × 10 100 × 100 N/A

Experimental setupAfter fabrication, the chips were directly mounted onto a

printed circuit board (PCB), wire-bonded and encapsulated[24] with the sensing areas clearly exposed. Both the drainand common source of the sensors were connected to asemiconductor characterization system (SCS) Keithley 4200,and ESD protection was provided by using a source measureunit (SMU) Keithley 2602. During the test, the packagedsensors were immersed into electrolytes of known pH values.An Ag/AgCl reference electrode was used as the remote gate,providing the gate reference voltage through the electrolyte.A calibrated pH meter was also immersed into the electrolytealongside the DUT (Device Under Test) to monitor the pHchange for comparison against the ISFETs results. A magneticstirrer was used to ensure a uniform distribution of ions in theliquid. The entire experimental setup was enclosed within aFaraday cage, to shield environmental electrical noise. Thetemperature of the electrolyte during the experiments wasmaintained at T=27◦C.

IV. RESULTS AND VALIDATION OF THE MODELA. Overview

The overall electrical functionality of the ISFETs is provedby ID − VGS sweep, which are shown in Fig. 5a and 5b,

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with the corresponding MOSFET devices as references. The

PMOS_2D2_1D2_2D2_3

- 8 - 6 - 4 - 2 0 2 4 6 8 10 121x10- 12

1x10- 10

1x10- 8

1x10- 6

1x10- 4

1x10- 2

(a).

- 8 - 6 - 4 - 2 0 2 4 6 8 10 121x10- 12

1x10- 10

1x10- 8

1x10- 6

1x10- 4

1x10- 2

PMOS_1D1_1D1_2D1_3

(b).

Fig. 5: ID/VGS curves for CMOS ISFETs of different chemicalsensing area with underlying electrical a. W/L=100/1µm andb.W/L=10/10µm

relevant chemical responses are shown in Fig. 6, in which theISFET output current tracks the pH change continuously. Theoverall chemical responses referred to the gate voltage are alsolisted in Table II.

TABLE II: ISFETs pH sensitivityElectrical(W×L)

Average chemical sensitivity(mV/pH) Total

100 × 1µm2 33.58 52.77 33.33 µ=35.5710 ×10µm2 26.95 34.12 42.59 σ=14.04Wc × Lc µm2 10× 10 100 × 10 100 × 100

B. First order effects

1) Subthreshold slope: The subthreshold slope can be ex-tracted from the IV sweep, which are listed in Table. III.What can be observed is that the subthreshold slopes of theISFET devices are much larger than those of the correspondingMOSFETs. Additionally these values are observed to beinversely proportional to the chemical sensing areas.

TABLE III: Sub-threshold slopes of ISFETs and correspondingMOSFETs

Electrical W×L ISFET devices subthreshold slope MOSFET100 × 1µm2 2.003 0.343 0.160 0.07910× 10µm2 1.248 0.289 0.400 0.079Wc × Lc µm2 10× 10 100 × 10 100 × 100 N/A

Vs(

V)

Time (S)

pH

VspH

-0.10

-0.20

0 400 800 1200-0.30

12

10

8

6

4

2

0.00

(a)

V = -0.032pH + 0.093Vs (

V)

pH

-0.2

2 4 6 8

0

1210-0.3

-0.1

(b)

Fig. 6: ISFET pH response. Shown are: (a) ISFET outputversus pH in time domain and (b) ISFETs pH sensitivityextracted from linear fitting.

2) Passivation capacitance: By using Eq. (8), the passiva-tion capacitance, based on measured results, is calculated andillustrated in Fig. 7 for an increasing chemical area. Simulatedresults using Eq. (1) and FEA tool are shown in the same graphas a reference. The geometric parameters used in FEA tool areidentical as the physical dimension of the sensors.

Pas

siva

tion

capa

cita

nce

(F)

Electrical 100x1Electrical 10x10Simulation resultsFit of measured capacitanceFit of Simulation1E-13

1E-14

1E-15

1E-12

100001000100Chemcial Area( )

Fig. 7: Extracted passivation capacitance

Using a polynomial fit to the experimental data, this in-dicates that the effective capacitance increases by chemicalarea by a power of 0.7. This is in agreement with FEAsimulated results. The only discrepancy was a shift in absolutecapacitance. Possible reasons include inaccurate estimation ofthe dielectric medium thickness (due to the surface abrasionduring chemical mechanical polishing) and/or parasitics omit-ted from the previous assumption. Moreover, the includedparasitic capacitance coupled to the floating gate can be muchbigger than the EDA simulated results.

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3) Threshold voltage: Using the constant current methoddescribed in [25], the threshold voltages of the devices wereextracted. The same method was also used for the intrinsicMOSFET devices, whose Vth was consistent with the simula-tion results based on the BSIM 3v3 model [26]. The currentlimit to detect threshold voltage is 1µA for 100µm × 1µmelectrical dimensions and 100nA for 10µm × 10µm devices.

Fig. 8 exhibits the distribution of threshold voltage ofall the fabricated sensors when exposed to a pH7 buffer.The threshold voltages were found to be distributed acrossa broad range of -14V to +8V, without any obvious statisticalcorrelation. This is believed due to trapped charge and parasiticeffect shown in Eq.(6). For comparison, the correspondingMOSFET devices exhibited consistent threshold voltage ofaround 0.6V with small deviation (standard expected mis-match). Fig. 9 compares measured results (solid dots) with

4

8

12

-14 -6 -2 2 6 10-100

Counts

MOSFETISFET

Fig. 8: Variation of threshold voltage of characterized CMOSISFETs compared to their MOSFET counterparts.

calculated threshold voltage (dashed area) using the proposedmodel, in which a fairly good compliance can be found. Thedashed area also illustrates the trapped charge error, whichwill be discussed under the second order effects section.

Vth error caused by floating gate trapped charge

100x110x10

Chemical area

Vth

(V)

Vth

(V)

10

5

0

-5

-10

4

0

-4

-8

-12

8

1000 10000100

Fig. 9: Threshold voltage range versus chemical area

4) Drift and noise: It was found that the drift of CMOS-based ISFETs had a negligible dimensional relationship tothe physical dimensions. The drift distribution and average

drift are illustrated in Fig. 10, with the red line indicatingthe corresponding MOSFETs. It is evident that the drift ofISFETs is distributed from 1.5mV to 8.5mV per hour (withaverage results of 5.8mV/hr). This is at least 3 times larger thanthe corresponding MOSFETs (which had 0.2mV/2000sec).The trend of ISFETs drift exhibited a relaxed-exponentialcharacteristic, which is in accordance with Eq. (10).

Volta

gedr

ift(V

)

Time (S)

0.007

0.006

0.005

0.004

0.003

0.0020.001

10 100 1000

0.000

0.008

Drift distributionMOSFET average driftISFET average drift

Fig. 10: Long term drift of ISFETs and MOSFETs fabricatedon the same process.

Fig. 11 illustrates the low frequency noise, where thedashed line indicates the simulation results of correspondingMOSFETs, and the solid line illustrates the measured results ofMOSFETs fabricated on the same die. The scattered dots showthe measured low frequency noise, with red dots indicatingthe average value and grey area for the noise distribution.It was found that the measured MOSFET noise is 1 orderof magnitude larger than simulation results. This can beattributed to the localized temperature drift and measurementsystem noise. This noise level is considered to be the baselineof this measurement system. There can be seen no clearrelationship between noise magnitude and chemical sensingarea within the devices tested. Therefore, according to theEq. (11), the chemical flicker-like noise dominates withinthe tested spectrum. From empirical observation throughoutour specimens, we estimate K=1nV 2Hz severing as possibledetection limit of ISFETs measurement limit, as well as theaverage exhibited noise floor. This confines that applicationsrequiring measurement accuracy of 5mV/hr or lower canindeed be very challenging.

10-4 10-3 10-2 10-1 10010 -7

10 -6

10 -5

10 -4

10 -3

10 -2 Estimated low frequency noise region for ISFET

Measured ISFETsAverage ISFETsSimulated MOSFETsMeasured MOSFETs

(V/Hz)

1/fN

oise

Frequency (Hz)

Fig. 11: Low frequency noise of ISFETs with identical elec-trical area.

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C. Second order effects

This paper has largely focused on the first order effects,while non-ideal factors are also considered and included inthe proposed model. This final section discussed second ordereffect with comparison to the experiment’s results.

1) Chemical capacitance: The chemical capacitance, in-cluding double layer capacitance and Faradic impedance isnot directly related to the design parameters. However, inlow frequency spectrum, where most chemical reaction takingplace, the Warburg capacitance effect in the proposed modelis negligible [27]. According to [28], the chemical capacitanceCchem including Helm capacitance CHelm (the double platecapacitance) and Gouy capacitance CGouy , (the double layerdistribution capacitance) is approximately 1pF/µm2. Consid-ering Cps+Cpd+Cpsub as a parallel plate capacitor, from toppassivation to the substrate, the chemical capacitance is at least3 orders of magnitude larger than the sum of all other parasiticcapacitances. Therefore, it has negligible effect in Eq. (7), (8),and (6).

2) Trapped charge: There are two possible mechanisms oftrapping: floating gate charge, and dielectric trapped chargeon the passivation. In the floating gate it is caused by residualelectrons during fabrication [29], giving an offset VthFGMOSof a several hundred mili-volts [30]. In the passivation QTCpis due to intrinsic dangling bonds within SixNy , buried site orsurface defects caused by extrinsic dangling bonds [31], [18].From Eq. (6), and [30], the estimated ISFET Vth variationcaused by floating gate trapped charge is illustrated by theshadowed area in Fig. 9. This demonstrates that devices witha small chemical area exhibit offsets of up to 2 Volts. Thiscan be reduced to a negligible level simply by increasing thechemical area.

However, compared to the deviation in the measurement,for larger chemical areas, QTCp is the more dominant, asthe measurement deviation becomes 10 times larger than theestimation. This demonstrates that the effect of trapped chargewithin the passivation layer can be equivalent or even higherthan the effect of trapped charge in the EMG.

V. CONCLUSION

This paper has, for the first time, presented a model forCMOS-based ISFET sensors that incorporates physical designgeometry. It has been shown that this model can be usedto provide a measure for non-ideal effects such as thresholdvoltage variation, drift and noise. This model has been verifiedby testing a number of CMOS-based ISFETs with varying theelectrical (W/L) and chemical sensing area (Wc/Lc). Mea-sured results show that the sensors do exhibit an inversion re-gion and chemical sensitivity as expected, however, with lowertransconductance and sub-threshold slopes when comparedto their MOSFET counterparts. The passivation capacitance(extracted from the sub-threshold slope) is in a good agreementwith simulation results. Threshold voltage extracted frommeasured results were in accordance with simulated resultswith reasonable error due to trapped charge. The measureddrift varied from 1µV/sec to 4µV/sec and was at least 3orders of magnitude larger than those for the corresponding

MOSFETs. The low-frequency noise magnitude in the deviceshas been found to be one order of magnitude larger than thoseof the intrinsic MOSFETs. Using the model, an empirically-derived value for the chemical noise is estimated, providingthe minimum noise level for fabricated CMOS ISFETs.

Second order effects such as chemical capacitance andtrapped charge influence have also been discussed. By com-paring the calculated VthISFET offset, it has been determinedthat for devices with smaller chemical dimension, the floatinggate charge dominates the offset, where in larger devices, thesurface dielectric trapped charge is more dominant. By usingthis model, a design compromise can be made to dramat-ically reduce sensors offsets and errors. Moreover, a goodestimation of threshold voltage, transconductance, and noisecan be derived, which eases the design specification for on-chip calibration circuits, but also determines the measurementlimit for specific ISFET sensors.

APPENDIXTABLE IV: Table of Parameters

Design and biasing parametersW/L MOSFET channel width and lengthWc/Lc Chemical area dimension(top metal width and length)VFG Floating gate voltage of metal stacksVS , VD, VB Source, Drain, Bulk voltage of transistorVsub Substrate voltage of the chipChemical parametersCHelm Helm capacitance of intrinsic MOSFETCGouy Gouy distribution capacitance of intrinsic MOSFETCchem CHelm + CGouyκ Chemical constant with constant pHFirst order effects related parametersψsa Surface potential of the channelVthISFET ISFET threshold voltageID ISFET drain currentCd Depletion capacitance of MOSFETCox Gate dioxide capacitance of MOSFETCpass Passivation capacitance of sensing membraneCps Passivation to source parasitic capacitanceCpd Passivation to drain parasitic capacitanceCpb Passivation to bulk/well parasitic capacitanceCpsub Passivation to substrate parasitic capacitanceCTp Total capacitance associated to the passivationCfgs Floating gate to source parasitic capacitanceCfgd Floating gate to drain parasitic capacitanceCfgb Floating gate to bulk/well parasitic capacitanceCfgsub Floating gate to substrate parasitic capacitanceCTfg Total capacitance associated to the floating gate nodeCi One of Cps, Cpd, Cpb, or CpsubVi Terminal voltages corresponding to individual CiCj One of Cfgs, Cfgd, Cfgb, or CfgsubVj Terminal voltages corresponding to individual CjSecond order related parametersQTCp Trapped charge in passivationQTCfg Trapped charge in floating gate

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[2] P. Bergveld and A. Sibbald, Analytical and biomedical applications ofion-selective field-effect transistors. Elsevier, 1988.

[3] P. Bergveld, “Thirty years of ISFETOLOGY What happened in the past30 years and what may happen in the next 30 years,” Elsevier Sensors& Actuators: B. Chemical, vol. 88, no. 1, pp. 1–20, 2003.

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Yan Liu (AM’08) received the B.Eng degree in 2006from Process Equipment and Control Engineeringat Zhejiang University, China, and the M.Sc degreein 2007 from Electrical and Electronic Engineeringat Imperial College London. He is now workingtowards the PhD degree in Imperial College London,focusing on the CMOS ISFETs based chemicalsensing systems.

Pantelis Georgiou (AM’05-M’08) received theM.Eng. degree in Electrical and Electronic Engineer-ing in 2004 and the Ph.D. degree in 2008 both fromImperial College London. He then moved to the In-stitute of Biomedical Engineering (also at Imperial)where he was appointed as a Research Fellow untiljoining academic faculty in 2011. He is currentlya lecturer within the Department of Electrical &Electronic Engineering and is also the head of theBio-inspired Metabolic Technology Laboratory inthe Centre for Bio-Inspired Technology and part of

the Medical Engineering Solutions in Osteoarthritis Centre of Excellence. Hisresearch includes bio-inspired circuits and systems, CMOS based lab-on-chiptechnologies and application of micro-electronic technology to create novelmedical devices. He conducted pioneering work on the silicon beta cell andis now leading the project forward to the development of the first bio-inspiredartificial pancreas for Type I diabetes. Dr Georgiou is a member of the IEEEand IET. He has been elected a member of the BioCAS Technical Committeeof the IEEE Circuits and Systems Society.

Timothy G. Constandinou (AM’98-M’01-SM’10)received the B.Eng. degree in Electrical and Elec-tronic Engineering in 2001 and the Ph.D. degreein 2005 both from Imperial College London. Hethen moved to the Institute of Biomedical Engineer-ing (also at Imperial) where he was appointed toResearch Officer in Bionics until joining academicfaculty in 2010. He is currently a lecturer within theDepartment of Electrical & Electronic Engineeringat Imperial College London and is also the deputy di-rector of the Centre for Bio-Inspired Technology. His

Research is in the novel application of microtechnology to develop advancedmedical devices (implantable, wearable and lab-on-chip) and biologically-inspired circuits, devices and systems. Dr Constandinou is an IEEE SeniorMember, an IET Member and a registered Chartered Engineer. He has beenelected a member of the Sensory Systems and BioCAS Technical Committeesof the IEEE Circuits & Systems Society, and also serves on the IET awardscommittee.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 9

Themistoklis Prodromakis (AM’04-M’08) holds aCorrigan research fellowship in nanoscale scienceand technology, funded by LSI Logic Inc. and theCorrigan-Walla Foundation, within the Centre forBio-inspired Technology at Imperial College Lon-don. He received his PhD from the Departmentof Electrical and Electronic Engineering at Impe-rial College in 2008, during which he successfullypioneered the use of interfacial polarisations fordemonstrating miniature passive devices. During hisresearch career he has contributed in several projects

in the areas of RF and Microwave Design and particularly Electron Devices,including: miniaturisation techniques MEMS-based phase-shifting topologies,slow-wave filters on laminar architectures, high-k dielectrics and processingtechniques for engineering polarisation mechanisms. In 2006 he contributedin setting up the Cleanroom facilities and the Microelectronics Laboratory atthe IBE. He recently applied his expertise in the biomedical arena with someexamples involving: the development of integrated CMOS chemical sensors,encapsulation techniques and materials and biologically inspired systems.

Christofer Toumazou (M’87-SM’99-F’01) is a Pro-fessor of Circuit Design, Founder and Executive Di-rector of the Institute of Biomedical Engineering atImperial College London, UK. Professor Toumazouhas made outstanding contributions to the fields oflow power analogue circuit design and current modecircuits and systems for biomedical and wireless ap-plications. Through his extensive record of research,he has invented innovative electronic devices rangingfrom dual mode cellular phones to ultra-low powerdevices for both medical diagnosis and therapy. He

has published over 320 research papers in the field of RF and low powerelectronics and is a member of many professional committees.. He holds23 patents in the field, many of which are now fully granted PCT. He isthe founder of four technology based companies with applications spanningultra low-power mobile technology and wireless vital sign monitors (ToumazTechnology Ltd, UK), biomedical devices (Applied Bionics PTE, Singapore),digital audio broadcasting (FutureWaves Pte Taiwan) and DNA detection(DNA Electronics Ltd, UK). These companies employ over 50 RF/low powerengineers worldwide many of whom are Professor Toumazou’s ex-graduatestudents. Professor Toumazou was invited to deliver the 2003 Royal SocietyClifford Patterson Prize Lecture, entitled “The Bionic Man”, for which he wasawarded The Royal Society Clifford Patterson bronze medal. He was recentlyawarded the IEEE CAS Society Education Award for pioneering contributionsto telecommunications and biomedical circuits and systems, and the SilverMedal from the Royal Academy of Engineering for his outstanding personalcontributions to British engineering. In 2008, he was elected to the grade ofFellow of both the Royal Society and Royal Academy of Engineering.

IntroductionAn Extended CMOS ISFET ModelOverviewThreshold VoltageTransconductance and Subthreshold slopeChemical TransconductanceDrift and Noise

MethodologySensor Implementation

Results and validation of the modelOverviewFirst order effectsSubthreshold slopePassivation capacitanceThreshold voltageDrift and noise

Second order effectsChemical capacitanceTrapped charge

ConclusionAppendixReferencesBiographiesYan LiuPantelis GeorgiouTimothy G. ConstandinouThemistoklis ProdromakisChristofer Toumazou