An Approach to Model Based Code Generation for a ... fileAn Approach to Model Based Code Generation...

An Approach to Model Based Code Generationfor a Specialized Soft Microprocessor

Elena Rozova1, Bernd Däne2

1Software Architectures and Product Lines Group2Computer Architecture and Embedded Systems Group

Technische Universität Ilmenau, Germany

AutSys-2015


2

• Introduction

• Concept of case study

• Overview of the soft microprocessor

• Design flow and detail solutions

• Results

• Conclusion and further work

Topics

Supported by Deutsche Forschungsgemeinschaft (DFG)and by Thüringer Aufbaubank (TAB and EFRE).


3

Introduction

Use of FPGAs (Field Programmable Gate Arrays)in Embedded Systems:

Advantages in performance and flexibility

Algorithms can be implemented directly or with soft microprocessors

Use of FPGAs (Field Programmable Gate Arrays)in Embedded Systems:

Advantages in performance and flexibility

Algorithms can be implemented directly or with

Challenge: Design processes


4

Concept of Case Study

Embedding project: Soft microprocessor LiSARD1

Real-time signal processing (controllers, filters)

Double precision floating point operation

Case study investigates graphical design processusing the LabVIEW tool

Goal: Model based code generation and optimization

1 LabVIEW integrated Softcore Architecture for Reconfigurable Devices


Overview of the Soft Microprocessor

5

Application specific processor architecture Configurable instruction set Omitting unneeded features

Simple pipeline: No dependency logic

Multi-core, shared memory


Pipeline Architecture

6

ProgramMemory

ReadInterface

ProgramMemory

ReadInterface

InstructionFetch

InstructionDecode

OperandFetch Execute Write Back

InstructionDecoder

InstructionDecoder

DataMemory

ReadInterface

DataMemory

ReadInterface

Source2Source1

ExecuteModeWriteBackOperationTarget

ALUALU

MU

XM

UX

DataMemory

WriteInterface

DataMemory

WriteInterface

InputRegisters

InputRegisters

OutputRegistersOutput

Registers


Code Generation and Optimization

7

Fully pipelined operators Exploit micro parallelism by instruction scheduling

Static approach Full timing defined at compile time

Optimization strategies crucial for performance

Explained with simple example program


Example Program

8

in 1 ? x1in 2 ? x2in 3 ? x3in 4 ? x4mul x1 k1 t1mul x2 k2 t2add x1 x2 t3sub x3 x4 t4

11116655

Total, not optimized:

26 clock cycles


9

Source 1 Source 2

Pre-oper. 1 Pre-oper. 2 Instruction Destinat.

Program memory

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

Data memory

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Time

Example Pipeline Optimization


10

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

IN1 - - -

IN 00

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Source 1 Source 2

Pre-oper. 1 Pre-oper. 2 InstructionDestinat.

Program memory Data memory

in 1 ? x1 1 clock cycle



11

IN1 - - -

IN 00

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

IN2 - - -

IN 01

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Source 1 Source 2






12

IN1 - - -

IN 00

IN2 - - -

IN 01

MUL

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

00 08 - -

MUL 04

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Source 1 Source 2



mul x1 k1 t1 6 clock cycles



13

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - -

MUL 04

MUL

MUL

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

01 09 - -

MUL 05

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Source 1 Source 2



mul x2 k2 t2 6 clock cycles



14

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - -

01 09 - -

MUL 04

MUL 05

MUL

MUL

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

IN3 - - -

IN 02

x1

x2

x3

x4

t1

t2

t3

t4

k1

k2

Source 1 Source 2






15

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - -

01 09 - -

IN3 - - -

IN 02

MUL 04

MUL 05

MUL

MUL

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

IN4 - - -

IN 03 t1

x4

x3

x1

x2

t2

t3

t4

k1

k2

Source 1 Source 2






16

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - -

01 09 - -

IN3 - - -

IN 02

IN4 - - -

IN 03

00 01 - -

MUL 04

MUL 05

ADD 06

MUL

MUL ADD

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04 t1

x4

x3

x1

x2

t2

t3

t4

k1

k2

Source 1 Source 2



add x1 x2 t3 5 clock cycles



17

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - -

01 09 - -

IN3 - - -

IN 02

IN4 - - -

IN 03

00 01 - -

02 03 -

MUL 04

MUL 05

ADD 06

07

MUL

MUL ADD

SUB

00 01 02 03 04 05 06 07 08 09 0A 0B

t2 05

t3 06

t4 07

k1 08

k2 09

x1 00

x2 01

02

03

t1 04 ADD

NEG x4

x3

Source 1 Source 2



sub x3 x4 t4 5 clock cycles



18

IN1 - - -

IN 00

IN2 - - -

IN 01

00 08 - - - -

01 09 - - - -

IN3 - - -

IN 02

IN4 - - -

IN 03

00 01 - - - -

02 03 -

NEG MUL 04

- - - -

MUL 05

- - - - - -

- - - -

ADD 06

- - - -

ADD 07

MUL

MUL ADD

SUB

00 01 02 03 04 05 06 07 08 09 0A 0B

05

06

07

08

09

00

01

02

03

04

t2

t3

t4

k1

k2

x1

x2

x3

x4

t1

Source 1 Source 2



Total: 12 clock cycles → Speedup: 2,1



Multi-Core Configurations

19

Multi-core setups: Multiple copies of memory No communication overhead

For n-core configuration:o 2 · n identical copieso 2 · n² individually addressable blocks

Tested so far:o Quad-core, logical memory space: 4,096 cellso Physical memory consumption: 262,144 bytes


Dual-Core Setup

20

Write

Read 1

Core 1

Read 2

Write

Read 1

Core 2

Read 2

Memory 1a

Memory 1b

Memory 2a

Memory 2b

Memory 3a

Memory 3b

Memory 4a

Memory 4b


Multi-Core Optimization

21

Schedule instructions to cores

Schedule variables to memory locations

Calculate dependencies and lifetimes

Duplicate variables if needed


General Design Flow

22

Operator Library

Processor Design

Code Design

Code Converter

Configuration

ofcores

Allocatevariables

Detectionof

dependencies

Searchfree

code line

Insertcode line

Check dependencies

Testbench

Configured

ProcessorMemory Init

DataProgram

Model based (currently)


Detail Solutions

23

Give some impression about graphical approach

Small model parts selected Total size:

o ~30 LabVIEW worksheets (Code Converter)o >100 LabVIEW worksheets (full project)


Code Converter Details

24



25



26


Experimental Results

27

Program Instruct. count Comment

FIR-64 196 Finite Impulse Response filter (64 coeff.)

Kalman-2 350 4x4 Kalman filter, calculated twice

6-Axes 866 Adaptive control algorithm, six channels

Ellipse 364 Ellipse regression for incremental sensors

Ellipse-4 1456 Same as above, four channels


0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized pipeline-optimized

28

Speedup by Pipeline Optimization


0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized 1-core 2-core 4-core

0,0 1,0 2,0 3,0 4,0 5,0 6,0

FIR-64

Kalman-2

6-Axes

Ellipse

Ellipse-4

non-optimized

Speedup by Multicore Optimization

29


Conclusion

30

Graphical approach to classical compiler functions

Efficiency demonstrated

Advantages and weaknesses identified

Contributes to model based design processes

Goals for further research outlined


Further Work

31

Generating source code from models

Model based instruction set synthesis

Combined HW/SW optimization

Integrated configuration management


32

Thank you

for

your kind attention

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