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Transcript of AN 253: Using Selectable I/O Standards in Cyclone Cyclone devices support both input and output...

  • February 2003, ver. 1.1 Application Note 253

    Using Selectable I/O Standards in Cyclone

    Devices

    Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3, and LVDS compatibility allow Cyclone™ devices to connect to other devices on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera® Quartus® II software, the Cyclone device family enables system designers to use low-cost FPGAs while keeping pace with increasing design complexity.

    This application note is a guide to understanding the input/output capabilities of the Cyclone devices, including:

    ■ Supported I/O standards ■ I/O banks ■ Programmable current drive strength ■ Hot socketing ■ Termination guidelines ■ Pad placement and DC guidelines

    In addition, “Quartus II Software Support” on page 16 describes how to use the Quartus II software to specify device and pin options and assign pins to implement the above features of Cyclone devices.

    Supported I/O Standards

    Cyclone devices support the I/O standards shown in Table 1.

    f See the Cyclone FPGA Family Data Sheet for more details on the I/O Standards discussed in this section.

    Altera Corporation 1

    AN-253-1.1

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Notes to Table 1: (1) The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDS input

    or an external clock output. (2) Cyclone devices have dual-purpose differential inputs. Outputs are balanced SSTL outputs requiring an external

    resistor divider.

    3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)

    The 3.3-V LVTTL I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVTTL standard defines the DC interface parameters for digital circuits operating from a 3.0-V/3.3-V power supply and driving or being driven by LVTTL-compatible devices.

    The LVTTL input standard specifies a wider input voltage range of - 0.3 V

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B)

    The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVCMOS standard defines the DC interface parameters for digital circuits operating from a 3.0-V or 3.3- V power supply and driving or being driven by LVCMOS-compatible devices.

    The LVCMOS standard specifies the same input voltage requirements as LVTTL (- 0.3 V

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    The 2.5-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both 2.5-V LVCMOS ranges.

    1.8-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7)

    The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This standard defines the DC interface parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 1.8-V parts. The input and output voltage ranges are:

    ■ The 1.8-V normal and wide range input standards specify an input voltage range of - 0.3 V

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    ■ The 1.5-V normal and wide range input standards specify an input voltage range of - 0.3 V

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Figure 1. SSTL-3 Class I Termination

    Figure 2. SSTL-3 Class II Termination

    Cyclone devices support both input and output SSTL-3 Class I & II levels.

    SSTL-2 Class I & II (EIA/JEDEC Standard JESD8-9A)

    The SSTL-2 I/O standard is a 2.5-V memory bus standard used for applications such as high-speed double data rate (DDR) SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-2 logic switching range of 0.0 V to 2.5 V. This standard improves operation in conditions where a bus must be isolated from large stubs. The SSTL-2 standard specifies an input voltage range of -0.3 V

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Figure 4. SSTL-2 Class II Termination

    Cyclone devices support both input and output SSTL-2 Class I & II levels.

    LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644)

    The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 Mbps. Devices can operate at slower speeds if needed however, and there is a theoretical maximum of 1.923 Gbps. Due to the low-voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than CMOS, TTL, and PECL. This low EMI makes LVDS ideal for applications with low EMI requirements or noise immunity requirements. The LVDS standard specifies a differential output voltage range of 250 mV

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Each Cyclone device supports four I/O banks regardless of density. Similarly, each device I/O pin is associated with one of these specific, numbered I/O banks. To accommodate voltage-referenced I/O standards, each Cyclone I/O bank has a common VREF bus and each bank supports 3 VREF pins (see Figure 5). In the event these pins are not used as VREF pins, they may be used as regular I/O pins.

    Figure 5. Cyclone Power Bank & VREF Arrangement

    B2 B

    1

    B 3

    B4

    VREF2B2 VREF0B2VREF1B2 V

    R E

    F 2B

    1 V

    R E

    F 0B

    1 V

    R E

    F 1B

    1

    VREF2B4 VREF0B4VREF1B4 V

    R E

    F 2B

    3 V

    R E

    F 0B

    3 V

    R E

    F 1B

    3

    8 Altera Corporation

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Altera Corporation 9

    Additionally, each Cyclone I/O bank has its own VCCIO pins. Any single I/O bank must have only one VCCIO setting from among 1.5, 1.8, 2.5 or 3.3 V. Although there can only be one VCCIO voltage, Cyclone devices permit additional input signaling capabilities as shown in Table 2.

    f For more information on acceptable input levels, see AN 258: Using Cyclone Devices in Multi-Voltage Systems.

    Any number of supported single-ended or differential standards can be simultaneously supported in a single I/O bank as long as they use compatible VCCIO levels for input and output pins. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs, 2.5-V LVDS-compatible inputs and outputs, and 3.3-V LVCMOS inputs only.

    Voltage-referenced standards can be supported in an I/O bank using any number of single-ended or differential standards as long as they use the same VREF and a compatible VCCIO value. For example, if you choose to implement both SSTL-3 and SSTL-2 in your Cyclone device, I/O pins using these standards—because they require different VREF values—must be in different banks from each other. However, SSTL-3 and 3.3-V LVCMOS could be supported in the same bank with the VCCIO set to 3.3 V and the VREF set to 1.5 V.

    f See “Pad Placement & DC Guidelines” on page 12 for more information.

    All four I/O banks support all of the I/O standards with the exception of PCI, which is only supported on banks 1 and 3 (see Figure 6).

    Table 2. Acceptable Input Levels for LVTTL/LVCMOS

    Bank VCCIO Acceptable Input Levels

    3.3-V 2.5-V 1.8-V 1.5-V

    3.3-V v v

    2.5-V v v

    1.8-V v v v

    1.5-V v v v v

  • AN 253: Using Selectable I/O Standards in Cyclone Devices

    Figure 6. I/O Standards Supported in Cyclone Devices Notes (1), (2)

    Notes to Figure 6 (1) PCI is not supported on the EP1C3 device. (2) The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDS-

    compatible input or an external clock output.

    Programmable Current Drive Strength

    The Cyclone device I/O standards support various output current drive settings as shown in Table 3. These programmable drive-strength settings are a valuable tool in helping decrease the effects of simultaneously switching outputs (SSO) in conjunction with reducing system noise. The supported settings ensure that the device driver meets the specifications for IOH and IOL of the corresponding I/O standard.

    I/O Bank 2

    I/O B

    an k

    1

    I/O B

    an k

    3

    I/O Bank 4

    All I/O Banks support ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ LVDS ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II

    I/O Bank 1 also supports the 3.3-V PCI I/O Standard

    I/O Bank 3 also supports the 3.3-V PCI I/O Standard

    Table 3. Programmable Drive Strength

    I/O Standard IOH/IOL Current Strength Setting

    3.3-V LVTTL 24, 16, 12, 8, 4 mA

    3.3-V LVCMOS 12, 8, 4, 2 mA

    2.5-V LVTTL/LVCMOS 16, 12, 8, 2 mA

    1.8-V LVTTL/LVCMOS 12, 8, 2 mA

    1.5-V LVCMOS 8, 4, 2 mA

    SSTL-3 class I and II Min. Strength

    SSTL-2