Am486 Microprocessor PCI Customer Development …Am486® Microprocessor PCI Customer Development...

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Am486® Microprocessor PCI Customer Development Platform User’s Manual

© 1998 by Advanced Micro Devices, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of AdMicro Devices, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subdivision (b)(3)(ii) of thetsin Technical Data and Computer Software clause at 252.227-7013. Advanced Micro Devices, Inc., 5204 E. Ben WhitAustin, TX 78741.

AMD, the AMD logo, and combinations thereof, Comm86, E86, E86MON, and PCnet are trademarks of, Am486, Mand PAL are registered trademarks of, and FusionE86 is a service mark of Advanced Micro Devices, Inc.Vantis is a trademark of Vantis Corporation.Microsoft and Windows are registered trademarks of Microsoft Corp.Other product or brand names are used solely for identification and may be the trademarks or registered trademarkrespective companies.

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IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU.The AMD customer service network includes U.S. offices, international offices, and a customer training center. Technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86™ and Comm86™ microcontroller family hardand software development questions.

Frequently accessed numbers are listed below. Additional contact information is listed on theof this manual. AMD’s WWW site lists the latest phone numbers.

Technical SupportAnswers to technical questions are available online, through e-mail, and by telephone.

Go to AMD’s home page at www.amd.com and follow the Service link for the latest AMD technsupport phone numbers, software, and Frequently Asked Questions.

For technical support questions on all E86 and Comm86 products, send e-mail to [email protected] (in the US and Canada) or [email protected] (in Europe and the UK).

You can also call the AMD Corporate Applications Hotline at:

(800) 222-9323 Toll-free for U.S. and Canada44-(0) 1276-803-299 U.K. and Europe hotline

WWW SupportFor specific information on E86 and Comm86 products, access the AMD home page at www.amd.com and follow the Embedded Processors link. These pages provide information on upcoming producreleases, overviews of existing products, information on product support and tools, and a list of tecdocumentation. Support tools include online benchmarking tools and CodeKit™ software—tessource code example applications. Many of the technical documents are available online in PDF

Questions, requests, and input concerning AMD’s WWW pages can be sent via e-mail to [email protected].

Documentation and Literature SupportData books, user’s manuals, data sheets, application notes, and product CDs are free with aphone call. Internationally, contact your local AMD sales office for product literature.

To order literature, call:

(800) 222-9323 Toll-free for U.S. and Canada(512) 602-5651 Direct dial worldwide(512) 602-7639 Fax

Third-Party SupportAMD FusionE86SM program partners provide an array of products designed to meet critical time-to-mneeds. Products and solutions available include emulators, hardware and software debuggers, boproducts, and software development tools, among others. The WWW site and the E86 Family Products Development Tools CD, order #21058, describe these solutions. In addition, mature developmetools and applications for the x86 platform are widely available in the general marketplace.

Am486® Microprocessor PCI Customer Development Platform iv

Contents

About the Customer Development PlatformEvaluation Board Features ................................................................................ xiii

Am486® Microprocessor .............................................................................. xiii

Core Logic Chipset ....................................................................................... xiii

DRAM Main Memory................................................................................... xiv

Boot ROM and Flash Memory...................................................................... xiv

Onboard L2 Cache ........................................................................................ xiv

PC and DOS Compatibility.............................................................................xv

PC-Style Super I/O..........................................................................................xv

Keyboard and Mouse Controller .....................................................................xv

Onboard 10/100-Mbit/s Ethernet .................................................................. xvi

Expansion Bus Support ................................................................................. xvi

Development Support.................................................................................... xvi

Form Factor ................................................................................................... xvi

BIOS and Software ....................................................................................... xvi

Customer Development Platform Documentation ........................................... xvii

About This Manual ...................................................................................... xvii

Suggested Reference Material..................................................................... xviii

Documentation Conventions......................................................................... xix

Am486® Microprocessor PCI Customer Development Platform v

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2-21

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-25

2-27

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Chapter 1

Quick StartSetting Up the PCI CDP .................................................................................... 1-2

Installation Requirements.............................................................................. 1-3

Board Installation .......................................................................................... 1-4

Starting from Diskette ................................................................................... 1-6

Starting from an IDE Hard Drive .................................................................. 1-7

Installation Troubleshooting.......................................................................... 1-8

Chapter 2

Board Functional DescriptionFeature and Layout Diagrams............................................................................ 2-2

Jumper Functions............................................................................................... 2-6

Board Restrictions ............................................................................................. 2-7

Board Features ................................................................................................... 2-7

Am486 Microprocessor (M14)...................................................................... 2-8

Core Logic Chipset (M8, I13, D15) ............................................................ 2-11

Onboard Ethernet Controller (F7) ............................................................... 2-13

4-Kbyte Serial EEPROM (C4) .................................................................... 2-14

Development Support.................................................................................. 2-15

PCI Bus (I7)................................................................................................. 2-19

Level-2 Cache Memory (K19–N19 and N11).............................................2

DRAM Main Memory (P7).........................................................................2

Boot ROM (C16).........................................................................................

ISA Flash Memory (F20) ............................................................................ 2

EIP Flash Memory (L21) ............................................................................ 2

Real-Time Clock (G17)...............................................................................

ISA Bus Interface (A7)................................................................................ 2

Am486® Microprocessor PCI Customer Development Platform vi

2-32

2-33

.. 2-34

2-35

B-2

.B-10

Super I/O (C19)........................................................................................... 2-28

IDE Hard Drive (L4 and M4)...................................................................... 2-31

Keyboard (O1) ............................................................................................ 2-31

Mouse (M1)................................................................................................. 2-31

CPU Voltage Adjustment (Q15–Q16).........................................................

Power Supply Connectors (N2 and P2) ......................................................

Reset and Interrupt Switches and Headers................................................

Resistor Options ..........................................................................................

Appendix A

Default Settings

Appendix B

Bill of Materials and SchematicsBoard Bill of Materials (BOM) .........................................................................

Schematics......................................................................................................

Index

Am486® Microprocessor PCI Customer Development Platform vii

Am486® Microprocessor PCI Customer Development Platform viii

List of FiguresFigure 0-1. PCI CDP Overview............................................................................................. xii

Figure 2-1. PCI CDP Overview (Same as Figure 0-1)......................................................... 2-3

Figure 2-2. PCI CDP Block Diagram................................................................................... 2-4

Figure 2-3. PCI CDP Layout ................................................................................................ 2-5

Figure 2-4. Am486 Microprocessor Block Diagram.......................................................... 2-10

Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)........................................... 2-22

Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory ............................... 2-24

Figure 2-7. Serial Port Connector Pins (J8, J9) .................................................................. 2-29

Figure 2-8. Parallel Port Socket (J4) .................................................................................. 2-30

Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16) ........................................ 2-32

Figure 2-10. Ground Wire Connections ............................................................................... 2-33

List of TablesTable 0-1. Notational Conventions ................................................................................. xix

Table 1-1. Installation Troubleshooting ............................................................................. 1-8

Table 2-1. Board Jumper Summary .................................................................................. 2-6

Table 2-2. PCI Configuration Addressing ........................................................................ 2-11

Table 2-3. Analyzer Headers ............................................................................................ 2-16

Table 2-4. PCI Bus Master Test Points ............................................................................ 2-17

Table 2-5. TIP Interrupt Usage ......................................................................................... 2-18

Table 2-6. PCI Bus Interrupt Routing............................................................................... 2-19

Table 2-7. SIMM Socket Population Chart ...................................................................... 2-21

Table 2-8. Serial Port Pin/Signal Table ............................................................................ 2-29

Table 2-9. Parallel Port Pin/Signal Table ......................................................................... 2-30

Table 2-10. Switch Summary ............................................................................................. 2-34

Table 2-11. Resistor Options ............................................................................................. 2-35

Table A-1. Default Jumper Settings .................................................................................. A-1

Am486® Microprocessor PCI Customer Development Platform ix

Am486® Microprocessor PCI Customer Development Platform x

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About the Customer Development Platform

Congratulations on your decision to design with the Am486® microprocessor. The Am486 microprocessor PCI customer development platform (CDP) provides a reference design for embedded Am486 microprocessor-based systems using the Peripheral Component Interconnect (PCI) bus with an onboard 10- or 100-Mbit/s Ethernet connection.

The PCI CDP includes 9 Mbytes of Flash memory, PCI and ISA expansion connectors, and standard PC peripherals to allow customers to develop and benchmark network-ready firmware and applications for their embedded products. In addition, the platform’s use of low cost, off-the-shelf components makes itsuitable example for use in training or as a reference for customer hardware de

The PCI CDP demonstrates that a fifth-generation x86 microprocessor is norequired to include a PCI bus in customer designs.

Note: Advanced Micro Devices does not assume any responsibility for the maintenance of this evaluation tool. Changes to the schematics will be made only if the board is required to go back through a CAD layout.

Refer to the Am486 microprocessor documentation (listed on page xviii) for detailed information on the Am486 microprocessor.

Figure 0-1 on page xii provides an overview of the PCI CDP’s features.

Am486® Microprocessor PCI Customer Development Platform xi

Figure 0-1. PCI CDP Overview

Am486®

MicroprocessorJTAG PortCPU Logic Analyzer HeadersIn-Circuit Emulator SupportZero-Insertion-Force SocketFan/Heat Sink Included

Level-2 Cache512 KbyteWrite-Back Policy

EIP Flash MemoryAddressed as fourth DRAM bank8-Mbyte Flash MemoryFaster than ISA Bus Flash MemoryCoexists with up to 48 Mbyte of DRAM

Ethernet ControllerAm79C972 Device10/100Base-T PortThree Connection Status LEDsExtra EEPROM for User Data

Boot ROM Socket8 Bits WideBIOS Included

PCI ExpansionTwo PCI Bus Connectors

ISA Flash Memory1 Mbyte, 16 Bits Wide

Hex DisplayI/O Port 80h, 8 Bits WideI/O Port 680h, 8 Bits Wide

Test Interface Port

ISA Bus

CPU Bus

PCI Bus

IDE InterfaceSupports up to Four DevicesTwo Connector Status LEDs

RTCDS1685 Real-Time ClockYear-2000 Compliant242 Bytes Nonvolatile RAM

M5042 Keyboard ControllerAT Keyboard ControllerPS/2 Mouse Controller

ALi M1489Cache, Memory, and DRAM Controller(Northbridge Chip)PCI Bus Logic Analyzer HeadersNMI, SMI, Reset Switches

Super I/OIrDA Module2 Serial Ports with Status LEDs1 Parallel PortFloppy Disk Interface

ALi M1487ISA Bridge(Southbridge Chip)PCI Bus Arbiter

ISA ExpansionTwo ISA Bus Connectors

DRAMThree 72-pin SIMM SocketsSupports 48 Mbytes of EDO or FPM DRAM48 Mbytes of 60-ns DRAM Installed

Am486® Microprocessor PCI Customer Development Platform User’s Manualxii

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Evaluation Board Features This section describes the following features of the PCI CDP:

• Am486® Microprocessor, page xiii• Core Logic Chipset, page xiii• DRAM Main Memory, page xiv• Boot ROM and Flash Memory, page xiv• Onboard L2 Cache, page xiv• PC and DOS Compatibility, page xv• PC-Style Super I/O, page xv• Keyboard and Mouse Controller, page xv• Onboard 10/100-Mbit/s Ethernet, page xvi• Expansion Bus Support, page xvi• Development Support, page xvi• Form Factor, page xvi• BIOS and Software, page xvi

Am486® Microprocessor

• AMD Am486 DX5 microprocessor is included. Supports Am486 DX2, DX4and DX5 microprocessors (168-pin pin-grid array (PGA), 3.3 V or 3.45 V).

• Zero insertion force (ZIF) PGA microprocessor socket for emulator suppo

• CPU voltage is jumper selectable.

Core Logic Chipset

• Acer Labs FINALi 486 PCI chipset

– M1489 Cache, Memory, and PCI Controller

– M1487 ISA Bridge Controller

– M5402 Mouse/Keyboard Controller

Am486® Microprocessor PCI Customer Development Platform xiii

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DRAM Main Memory

• 48 Mbyte of 60-ns EDO DRAM installed.

• Supports one, two, or three banks of 32- or 36-bit-wide DRAM using indusstandard 5-V 72-pin SIMMs. DRAM can be fast page mode (FPM) or extendata out (EDO).

• Supports 1-, 4-, or 16-Mbit technology DRAMs.

• Three SIMM sockets. One or two banks per socket. Three banks DRAM maximum.

• DRAM is accessible by CPU and PCI bus masters.

• L1/L2 cache snoop cycles are generated for PCI master memory accesse

• Wait-state timing is configurable through chipset registers.

Boot ROM and Flash Memory

• Dip socket provided for one 8-bit-wide boot ROM, logically on the ISA bus

• 1 Mbyte of 16-bit-wide Flash memory soldered to the board, logically on ISbus.

• 8-Mbyte Flash memory for execute-in-place (EIP) applications, located onmemory bus in place of one DRAM bank. EIP Flash is implemented using

AMD 22V10 PAL® device for glue logic.

Onboard L2 Cache

• 512-Kbyte cache size, configured as 32-bit-wide memory.

• Write-back or write-through protocol configurable through chipset register

• One 32-Kbyte x8 SRAM for cache tag space, soldered to board.

• Four 128-Kbyte x8 SRAMs for cache data space, soldered to board.

• 2-1-1-1 (read) and 2-2-2-2 (write) burst timing with 15-ns data and 10-ns tSRAMs.

Am486® Microprocessor PCI Customer Development Platform User’s Manualxiv

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the

PC and DOS Compatibility

• IDE interface in chipset.

• Standard chipset configuration registers, known to BIOS and DOS.

• Off-the-shelf PC chipset provides common I/O functions found in a PC:

- Two 82C59 interrupt controllers (SMI, NMI, and INT support)

- One 82C54 programmable interval timer

- Two 82C37 DMA controllers (seven channels)

- External boot ROM chip-select signal

- PC-style real-time clock (RTC) (non-Y2K-compliant, disabled by default

• DS1285 Y2K-compliant RTC chip. The DS1285 RTC can be disabled, andnon-Y2K RTC enabled, by removing one resistor and populating another.

PC-Style Super I/O

• DOS and PC-AT compatible I/O.

• Two 16550-compatible serial ports.

• One parallel port. Supports enhanced parallel port (EPP) and extended capabilities port (ECP) modes.

• Floppy disk interface.

• IrDA port with external transceiver (115 Kbyte/s).

Keyboard and Mouse Controller

• 8042-compatible controller chip (included in chipset).

• AT keyboard interface.

• PS/2 Mouse interface.

Am486® Microprocessor PCI Customer Development Platform xv

ion.

age.

Onboard 10/100-Mbit/s Ethernet

• AMD PCnet™-Fast+ Ethernet Controller Chip, Am79C972.

• 32-bit PCI bus interface with bus mastering capability.

• Integrated 12-Kbyte buffer.

• External PHY transceiver for full duplex operation at 10 or 100 Mbit/s.

• IEEE802.3, PC97, PC98, and NetPC compliance.

• Preprogrammed 1-Kbyte serial EEPROM included for Ethernet configurat

• Extra 4-Kbyte serial EEPROM included for user nonvolatile data.

Expansion Bus Support

• Two PCI 2.0 expansion connectors, desktop PC style.

• Two ISA 16-bit expansion connectors, desktop PC style.

Development Support

• In-circuit emulator (ICE) support with socketed microprocessor in PGA pack

• Logic analyzer headers for all CPU and PCI bus signals.

• Switches (push-button) for NMI, SMI, and RESET.

• LEDs for IDE, serial port, Ethernet activity, and Ethernet link speed.

• I/O port 80h and 680h hexadecimal displays.

• Am486 microprocessor JTAG support.

• Connector for AMD embedded systems Test Interface Port (TIP) board.

Form Factor

• Baby-AT motherboard form factor.

• Fits standard desktop-PC-style chassis.

BIOS and Software

The included diskette contains information about the included BIOS and anyadditional utility and demonstration software for the PCI CDP.

Am486® Microprocessor PCI Customer Development Platform User’s Manualxvi

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Customer Development Platform Documentation

The Am486® Microprocessor PCI Customer Development Platform User’s Manual provides information on the design and function of the development platform. The software shipped with the board is described in the README files and online BIOS manual included with your kit.

The included online documentation is in text or Adobe Acrobat (PDF) format. The latest Acrobat Reader is available from Adobe’s site on the World Wide Web (currently at www.adobe.com).

About This Manual

Chapter 1, “Quick Start” helps you quickly set up and start using the PCI CD

Chapter 2, “Board Functional Description” contains descriptions of the basic sections of the evaluation board: layout, microprocessor, core logic chipset, Ethcontroller, DRAM, boot ROM and Flash memory, PCI bus and ISA bus interfacsuper I/O, keyboard and mouse, drives, and interrupt switches.

Appendix A, “Default Settings” summarizes the jumper and configuration resispositions on the PCI CDP when it is shipped.

Appendix B, “Bill of Materials and Schematics” shows the bill of materials for tevaluation board, and the actual CAD schematics used to build the board.

Am486® Microprocessor PCI Customer Development Platform xvii

eb

Suggested Reference Material

The following AMD documentation may be of interest to the PCI CDP user. For information on ordering literature, see page iii.

• Enhanced Am486®DX Microprocessor Family Data Sheet, order #20736

• Am486®DX/DX2 Microprocessor Hardware Reference Manual, order #17965

• Am486® Microprocessor Software User’s Manual, order #18497

• Am79C972 PCnetTM-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support Data Sheet, order #21485

• E86 Family Products Development Tools CD, order #21058

• Flash Memory Products Data Book, order # 11796

• For current application notes and technical bulletins, see our World Wide Wpage at www.amd.com.

The following non-AMD documents are also recommended:

• Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via SoftwareDallas Semiconductor, www.dalsemi.com.

• DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data SheetDallas Semiconductor, www.dalsemi.com.

• FINALi 486 M1489/1487 PCI Chip Set Preliminary Data SheetAcer Laboratories Inc., see www.acerlabs.com for contact information. RelatedBIOS guidelines, errata, and application documents are also available.

• M5113: Enhanced Super I/O Controller Data SheetAcer Laboratories Inc., see www.acerlabs.com for contact information.

Am486® Microprocessor PCI Customer Development Platform User’s Manualxviii

e

Documentation Conventions

The Advanced Micro Devices Am486® Microprocessor PCI Customer Development Platform User’s Manual uses the conventions shown in Table 0-1 (unless otherwise noted). These same conventions are used in all the E86 family support product manuals.

Table 0-1. Notational Conventions

Symbol Usage

Boldface Indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated.

Italic Indicates a descriptive term to be replaced with a user-specified term.

Typewriter face Indicates computer text input or output in an example or listing.

[ ] Encloses an optional argument. To include the information described within the brackets, type only the arguments, not the brackets themselves.

{ } Encloses a required argument. To include the information described within the braces, type only the arguments, not the braces themselves.

.. Indicates an inclusive range.

... Indicates that a term can be repeated.

| Separates alternate choices in a list — only one of the choices can be entered.

:= Indicates that the terms on either side of the sign arequivalent.

Am486® Microprocessor PCI Customer Development Platform xix

Am486® Microprocessor PCI Customer Development Platform User’s Manualxx

Chapter 1

Quick Start

This chapter provides information that helps you quickly set up and start using the

Am486® microprocessor PCI customer development platform (CDP).

The PCI CDP is shipped with a BIOS that has been configured specifically for the chipset used on this platform. The BIOS contains the code that enables the PCI CDP to function as a standard AT-compatible PC, using AT-compatible displays, display adapters, and keyboards. Details on the BIOS can be found in the BIOS documentation shipped on diskette with your kit.

The PCI CDP can run AT-compatible operating system software. You can start the system with either a bootable diskette or an ATA (IDE) hard disk drive that already has the operating system installed.

Embedded BIOS software typically supports the configuration of onboard Flash memory as a resident flash disk (RFD) that can also be set up as a boot device. See the online BIOS manual included with your kit.

For information on how to:

• Set up the PCI CDP, see page 1-2.

• Boot the PCI CDP from a diskette, see page 1-6.

• Boot the PCI CDP from a hard disk drive, see page 1-7.

• Troubleshoot installation problems, see page 1-8.

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Setting Up the PCI CDPCAUTION: As with all computer equipment, the PCI CDP may be damaged by electrostatic discharge (ESD). Please take proper ESD precautions when handling any board.

Warning: Read before using this development platformBefore applying power, the following precautions should be taken to avoid damage or misuse of the board:

• Make sure power supply connectors (from a standard AT system power supare plugged onto the board correctly. The grounds (usually black wires) must meet at the center of the two power supply connectors on the board. See “PSupply Connectors (N2 and P2)” on page 2-33.

• See Figure 2-3 on page 2-5 for connector positions.

• Check the diskette that was shipped with your kit for README or errata documentation. Read all the information carefully before continuing.

For current application notes and technical bulletins, see the AMD World WiWeb page at www.amd.com and follow the link to Embedded Systems.

!

Am486® Microprocessor PCI Customer Development Platform User’s Manual1-2

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Installation Requirements

You need to provide the following items (in addition to the PCI CDP from the kit).

Required for all setups:

• A VGA-compatible monitor

• A PCI- or ISA-bus video card that supports VGA

• A cable to connect the monitor to the video card

• An AT-compatible keyboard

• A PS/2-style mouse (if needed for your operating system)

• A standard AT-style power supply

To boot from a floppy diskette:

• An AT-compatible 3.5-inch or 5.25-inch diskette drive

• A bootable DOS diskette

• A standard 34-wire AT diskette drive cable

To boot from a hard disk drive:

• An ATA-compatible hard disk drive

• AT-compatible operating system (preinstalled on the hard disk drive)

• A standard 40-pin ATA HDD cable

If you install both a floppy diskette drive and a hard disk drive, you can boot freither device. Only one boot disk image (floppy or hard disk) is required. Forexample, you can boot from the floppy and then install the operating system blank hard disk drive.

CAUTION: Use the configuration described here when you first start the PCI CDP. Before using other features, read the appropriate sections in Chapter 2, “Board Functional Description.”!


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Board Installation

Note: See Figure 2-2 on page 2-4 for a block diagram of the board. See Figure 2-3 on page 2-5 for a layout diagram of the board, including connector locations referenced in this section.

DANGER: Make sure the power supply and the VGA monitor are not plugged into an electrical outlet during the following steps.

1. Remove the board from the shipping carton. Visually inspect the board to verify that it was not damaged during shipment. The board contains several jumpers. The following steps assume all jumpers are in the factory default configuration (settings are listed in Appendix A, “Default Settings”).

2. If you are installing a diskette drive, perform the following steps:

a. Inspect the 34-wire, diskette-drive cable that you are providing. The rwire along one edge of the ribbon cable indicates wire 1. Most cables ha connector for the board at one end and two or more connectors alonlength. There may be two different drive connectors at each location taccommodate different drive types.

b. Connect one end of the diskette-drive cable to the 34-pin connector (connector J6 at location E20) on the PCI CDP (with wire 1 oriented towards the middle of the board). If there is a twist in one span of the caconnect the opposite end to the board.

c. Connect another connector on the diskette-drive cable to the diskette djust as you would for a standard PC installation. If there is a twist in thcable, the position you use determines whether the drive responds asB (typically drive A connects to the end of the cable, beyond the twist). Tconnector’s orientation should be indicated in the drive documentationmarked near the connector on the drive. Usually wire 1 is oriented towathe drive’s power cable connector.

d. Find one of the 4-wire power connectors from the PC power supply aattach it to the 4-pin connector on the diskette drive just as you woulda standard PC installation.

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3. If you are installing a hard disk drive, perform the following steps:

a. Inspect the 40-wire IDE cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1.

b. Connect one end of the 40-wire IDE cable to the hard drive just as you would for a standard PC installation. The connector’s orientation shouldindicated in the drive documentation, or marked near the connector ondrive. Usually wire 1 is oriented towards the drive’s power cable connec

c. Connect the other end of the 40-wire IDE cable to the first 40-pin conne(connector J5 at location L4) on the PCI CDP (with wire 1 oriented towathe edge of the board, near the power supply connector).

d. Find one of the 4-wire power connectors from the PC power supply aattach it to the 4-pin connector on the hard drive just as you would forstandard PC installation.

4. Make sure the CPU heat sink is securely attached to the microprocessorconnect the heat sink fan power wires to a spare disk drive power conneFan power supply connectors are not all the same. Check the voltage printed on the fan and connect its wires to the correct voltage pins on the appropriate power supply connector.

5. Insert a PCI- or ISA-bus VGA-compatible video card into an appropriate son the PCI CDP. The PCI slots are labeled SLT1 and SLT2. The ISA slotslabeled SL1 and SL2.

6. Connect the monitor cable from the monitor to the D-connector on the vidcard just as you would for a standard PC.

7. Connect the AT keyboard to the keyboard connector (connector J1 at location

8. Connect the PS/2 mouse (if used) to the mouse connector (connector J1location M1).

9. Connect the connectors (usually marked P8 and P9) from the standard PC supply into the board’s power connectors J2 (at location Q2) and J3 (at locaN2). P8 connects to J2 (the six pins closest to the corner of the board); Pconnects to the other six pins. Make sure the black ground wires from P8 and P9 meet in the middle of the board’s J2 and J3 connectors.

CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. !


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Starting from Diskette

Use the following steps to start the PCI CDP from a bootable diskette:

1. Make sure you have installed the PCI CDP correctly as described in “SettingUp the PCI CDP” on page 1-2.

CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP.

2. Plug the VGA monitor into an electrical outlet and turn it on.

3. Insert a bootable DOS diskette (not included) in the disk drive.

4. Apply power to the PCI CDP by connecting the PC power supply to an electoutlet. If the power supply is equipped with a switch, turn it on.

The power supply fan should start running, and the port 80h LEDs should to display power-on self-test (POST) status codes. Then the speaker shobeep and the monitor should start displaying startup information.

Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan.

5. The first time you start the system, the BIOS might display a message repoa CMOS error or some other BIOS configuration problem. Follow the instructions shown on the screen to enter the Setup utility. Once you are iSetup utility, you can set the system’s date, time, startup drive, and otheroptions.

For more information on the included BIOS, see the online BIOS manualincluded with your kit.

6. Save and exit the setup utility.

7. The system should now boot from the DOS diskette just like a standard Pyou encounter any problems, see “Installation Troubleshooting” on page

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Starting from an IDE Hard Drive

Use the following steps to start up the PCI CDP from an IDE hard drive on which you have preinstalled an operating system (while it was connected to another PC):

1. Make sure you have installed the PCI CDP correctly as described in “SettingUp the PCI CDP” on page 1-2.

CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP.

2. Plug the VGA monitor into an electrical outlet and turn it on.

3. If a diskette drive is installed, make sure it is empty.

4. Apply power to the PCI CDP by connecting the PC power supply to an electoutlet. If the power supply is equipped with a switch, turn it on.

The power supply fan and hard disk should start running, and the port 80h Lshould start to display power-on self-test (POST) status codes. Then the spshould beep and the monitor should start displaying startup information.

Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan.

5. The first time you start the system, the BIOS might display a message repoa CMOS error or some other BIOS configuration problem. Follow the instructions shown on the screen to enter the Setup utility. Once you are iSetup utility, you can set the system’s date, time, startup drive, and other op

6. In the BIOS setup utility, use the automatic configuration option to set upDrive C. Select either physical addressing or logical block addressing (LBas appropriate for your hard disk drive.

For more information on the included BIOS, see the online BIOS manualincluded with your kit.

7. Save and exit the setup utility.

8. The system should now boot using the operating system on the hard disyou encounter any problems, see “Installation Troubleshooting” on page

!


Installation Troubleshooting

Table 1-1. Installation Troubleshooting

Problem Solution

The Port 80h LED readout is blank after I turn on the power supply.

Check power supply connectors J2 and J3.

The Port 80h LED readout is stuck at 00. I see nothing on the VGA monitor and do not hear any beeps from the speaker. I do not hear the head synchronization on the diskette drive (if attached).

Ensure processor reset by pressing the Reset button, SW1 at location N5.

Check that the BIOS ROM and the microprocessor are correctly installed, and that jumpers JP32 and JP33 are both off.

The Port 80h LED readout displayed some power-on-self-test (POST) numbers, but then stopped at one number before the system finished starting.

Make sure all cables are connected properly, all adapters are seated firmly in their slots, and the CMOS battery is correctly installed.

See the online BIOS documentation included with your kit for a list of POST numbers and meanings.

I hear a beep on the speaker but see nothing on the VGA monitor.

Check that the monitor is plugged in and turned on.

Check that the monitor is correctly connected to the video card.

Check that the video card is correctly seated in the appropriate slot.

Check that the video card supports VGA.

I see the startup information on the monitor but the memory test stops at an incorrect memory size. (1 Mbyte equals 1024 Kbyte.)

Make sure the SIMMs that came with the kit are securely installed in the SIMM sockets.

I see the startup information on the monitor but it says there’s a battery problem or CMOS checksum error and the system doesn’t finish booting.

Follow the BIOS instructions to run the Setup utility to configure the CMOS RAM and save settings.


e

u

e

e

.

I configured the CMOS RAM and saved my settings, but settings are lost the next time I turn on the PCI CDP.

Make sure a fresh 3.0-V 20-mm coin cell is installed correctly (“+” side facing up) in the BT1 battery holder at location E12.

I don’t hear any sound from the diskette drive and the system does not boot from a diskette.

Check that the 34-wire cable to the diskette drive is properly connected at both the drive end and the boardend (board connector J6 at location E20). The red wireshould be oriented towards pin 1 on both the drive andthe board.

Check that the CMOS setup indicates that drive A is thcorrect size and capacity for your diskette drive.

I hear the diskette being accessed but get an error message “Non System disk” or “Drive A not found.”

Check that the diskette in the drive is bootable, just as yowould on a standard PC.

Make sure the diskette drive is connected properly to thlast connector on the cable.

In the BIOS setup utility, make sure the BIOS is configured to boot from diskette, and that the diskette sizand density is configured properly.

I get a “Missing Keyboard” error message on the monitor during boot-up.

Check that an AT-style keyboard is properly connected

The BIOS debugging monitor prompt is displayed.

Make sure the NMI switch is not pressed.

Check that the DRAM and any PCI or ISA-bus devicesare installed correctly and known to be functional.

Table 1-1. Installation Troubleshooting (Continued)

Problem Solution


or

y

I have installed a hard disk with a preinstalled operating system, but the PCI CDP won’t access the hard disk.

Check that the 40-wire IDE cable is properly connectedat both the drive end and the board end (board connectJ5 at location L4). Check that the CMOS setup is configured correctly for your drive.

Make sure the board will start from a bootable diskette indrive A. Then try to do a directory listing of drive C. If the directory listing of C works, the drive is functioning and there is a problem with the drive’s boot block or system image. (Note that some operating systems willdisplay an error if you list an empty directory. If this happens, try copying a file to the drive; then do a directorlisting again. If this fails, check the drive for boot block viruses.)

Make sure the drive functions properly on a different system.

There is a problem you cannotresolve.

Check that the board is set to its default settings (see Appendix A, “Default Settings”).

Contact the AMD Technical Support Hotline (see page iii).

Table 1-1. Installation Troubleshooting (Continued)

Problem Solution


Chapter 2

Board Functional Description

The Am486® microprocessor PCI customer development platform (CDP) provides a test and development platform for Am486 microprocessor-based designs. Read the following sections to learn more about the board:

• Feature and Layout Diagrams, page 2-2• Jumper Functions, page 2-6• Board Restrictions, page 2-7• Board Features, page 2-7

– Am486 Microprocessor (M14), page 2-8– Core Logic Chipset (M8, I13, D15), page 2-11– Onboard Ethernet Controller (F7), page 2-13– 4-Kbyte Serial EEPROM (C4), page 2-14– Development Support, page 2-15

- JTAG Ports (Q14 and D17), page 2-15- Logic Analyzer Headers, page 2-15- In-Circuit Emulator Compatibility (M14, Q15–Q16), page 2-17- Hexadecimal Display (H23, J23), page 2-17- Test Interface Port (TIP) (A16), page 2-18

– PCI Bus (I7), page 2-19– Level-2 Cache Memory (K19–N19 and N11), page 2-20– DRAM Main Memory (P7), page 2-20– Boot ROM (C16), page 2-21– ISA Flash Memory (F20), page 2-23– EIP Flash Memory (L21), page 2-25– Real-Time Clock (G17), page 2-27– ISA Bus Interface (A7), page 2-28– Super I/O (C19), page 2-28

- Serial Ports (E23 and C23), page 2-29- IrDA Interface (A19), page 2-29- Parallel Port (A22), page 2-30- Floppy Disk Drive (E20), page 2-30


ials,

s.

– IDE Hard Drive (L4 and M4), page 2-31– Keyboard (O1), page 2-31– Mouse (M1), page 2-31– CPU Voltage Adjustment (Q15–Q16), page 2-32– Power Supply Connectors (N2 and P2), page 2-33– Reset and Interrupt Switches and Headers, page 2-34– Resistor Options, page 2-35

See the appendices for information about default board settings, bill of materand schematics.

Feature and Layout DiagramsThe following figures summarize the features and layout of the PCI CDP.

• Figure 2-1 on page 2-3 provides an overview of the platform’s features.

• Figure 2-2 on page 2-4 is the block diagram for the platform.

• Figure 2-3 on page 2-5 shows the platform layout and component location


Figure 2-1. PCI CDP Overview (Same as Figure 0-1)

Am486®

MicroprocessorJTAG PortCPU Logic Analyzer HeadersIn-Circuit Emulator SupportZero-Insertion-Force SocketFan/Heat Sink Included

Level-2 Cache512 KbyteWrite-Back Policy

EIP Flash MemoryAddressed as fourth DRAM bank8-Mbyte Flash MemoryFaster than ISA Bus Flash MemoryCoexists with up to 48 Mbyte of DRAM

Ethernet ControllerAm79C972 Device10/100Base-T PortThree Connection Status LEDsExtra EEPROM for User Data

Boot ROM Socket8 Bits WideBIOS Included

PCI ExpansionTwo PCI Bus Connectors

ISA Flash Memory1 Mbyte, 16 Bits Wide

Hex DisplayI/O Port 80h, 8 Bits WideI/O Port 680h, 8 Bits Wide

Test Interface Port

ISA Bus

CPU Bus

PCI Bus

IDE InterfaceSupports up to Four DevicesTwo Connector Status LEDs

RTCDS1685 Real-Time ClockYear-2000 Compliant242 Bytes Nonvolatile RAM

M5042 Keyboard ControllerAT Keyboard ControllerPS/2 Mouse Controller

ALi M1489Cache, Memory, and DRAM Controller(Northbridge Chip)PCI Bus Logic Analyzer HeadersNMI, SMI, Reset Switches

Super I/OIrDA Module2 Serial Ports with Status LEDs1 Parallel PortFloppy Disk Interface

ALi M1487ISA Bridge(Southbridge Chip)PCI Bus Arbiter

ISA ExpansionTwo ISA Bus Connectors

DRAMThree 72-pin SIMM SocketsSupports 48 Mbytes of EDO or FPM DRAM48 Mbytes of 60-ns DRAM Installed


Figure 2-2. PCI CDP Block Diagram

MicroprocessorAm486®

(ZIF Socket)

ALi M1489Cache, Memory, and PCI Controller

ALi M1487ISA Bridge Controller

AMD Am79C972PCNet Fast+ Ethernet

PCI Expansion Connector

Super I/O Chip

Floppy Disk Connector

IDE Connector

AT Keyboard Connector

PS/2 Mouse Connector

EDO DRAM72-pin SIMM Socket 1

Serial Port1 Connector

Serial Port2 Connector

Parallel Port Connector

HEX LEDs for Debug

Boot ROM Socket (x8)

1-Mbyte FLASH Memory (x16)

Logic Analyzer Header(s): CPU Signals

Logic Analyzer Header(s): PCI Signals

ISA Expansion Connector

Memory Address

CPU Data

CPU Address

CPU Control

PCI Bus (33 MHz, 5 V)

ISA Bus

Cache Control



IrDA

CPU Jumpers

TIP Board Interface

SystemPower

SystemClocks

CPUPower

Pin Grid Array

JTA

G

SwitchesLEDs

NM

I

Res

et

PHY

Onboard512K L2 Cache

DRAM-to-Flash 8-Mbyte Flash MemoryFor Execute-In-Place

& Control

SM

I

E/n

etS

IO1

SIO

2

ISA Expansion Connector

IDE Connector

M5042KeyboardController

M5113A

DS1685Y2K RTC

PCI Expansion Connector

1-Kbyte Config SEEPROM

MACH®

CPU Interface

Interface

4-Kbyte User SEEPROM

Logic

IDE

0ID

E1


Figure 2-3. PCI CDP Layout

IDE

Har

d D

isk

Con

n.

11

12

13

14

15

16

17

18

19

20

1

2

3

4

5

6

7

8

9

10

21

22

23

24

B A D C F E H G J I LK N M P O Q

B A D C F E H G J I LK N M P O Q

11

12

13

14

15

16

17

18

19

20

1

2

3

4

5

6

7

8

9

10

21

22

23

24

Am486®

Microprocessor

EIP Flash Memory

ISA Flash

Boot ROM

TIP Conn.

CO

M 2

CO

M 1

Speaker

Battery

ISASlots

PCISlots

DRAMSIMMSlots

Mouse KBDEthernetConn.

Par

alle

l Por

t

M1489Northbridge

M1487Southbridge

Am79C972Ethernet

Controller

Power Conn.

M5042Kbd/

Mouse

DS1685RTC

M5113

SuperI/O

MACH®

Logic Chip

IDE

Har

d D

isk

Con

n.Pin

1

Pin A1

Flo

ppy

Con

n.

Pin

1

Pin

1


Jumper FunctionsTable 2-1 describes the configuration jumpers on the PCI CDP.

Table 2-1. Board Jumper Summary

Part Signal Description Location in Figure 2-3 on Page 2-5

See App. B Schematicson:

For More Info., See:

JP2 CPUVCC3 Used with JP3 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same.

Q15 Sheet 3 page 2-32

JP3 CPUVCC3 Used with JP2 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same.

Q16 Sheet 3 page 2-32

JP4 CPUV1, CPUV2, CPUV3

Selects the CPU voltage used when JP2 and JP3 are set to “ADJ.” The selectable voltages are 3.45 V, 3.3 V, and 2.5 V.

R15 Sheet 3 page 2-32

JP32 Boot ROM A17

Used to configure boot ROM address signal A17.

C14 Sheet 17 page 2-21

JP33 Boot ROM A18

Used to configure boot ROM address signal A18.

B14 Sheet 17 page 2-21


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, the s 5-

t for CI us .

ory

mory

rnal le al

rd nd

mber 2-3 e.

Board Restrictions• Using a PCI chipset with the Am486 microprocessor is a fast and effective

to design a working system, but the system’s features can be limited by thchipset’s capabilities.

• The chipset used in the PCI CDP supports 5-V PCI 2.0 devices only. Thredevices are supported: the onboard Ethernet controller and two PCI slots.

• Except for the adjustable CPU supply voltage and 3.3-V Ethernet controllerPCI CDP uses 5-V power throughout. (The Am486 microprocessor provideV-tolerant I/O.)

• The chipset does not directly support ROM or Flash memory devices excepthe boot ROM. It is possible to implement Flash memory on the DRAM, Por ISA bus, but the chipset only allows booting from the boot ROM. ISA-bFlash memory is limited to 1 Mbyte because of addressing considerations

• The PCI CDP implements two banks of execute-in-place (EIP) Flash memin place of one DRAM bank. Flash memory timing requirements limit the chipset’s DRAM interface to its Fast (not Fastest) speed when the Flash meis used. This is equivalent to using 70-ns fast-page-mode (FPM) DRAM.

• The chipset allows only three banks of DRAM to be attached without extebuffers. Buffering the DRAM adds one wait state and reduces the availabperformance. “DRAM Main Memory (P7)” on page 2-20 describes additionDRAM device and configuration limits.

• The ISA peripherals provided by the M1487 chip are configured for standaPC-AT compatibility, so there is not much flexibility in assigning interrupts aDMA channels.

• The PCI CDP does not implement OnNow or Advanced Configuration andPower Interface (ACPI) power management.

Board FeaturesThe remainder of this chapter describes the features of the PCI CDP. The nuin parentheses following each heading indicates the part’s location in Figureon page 2-5. In addition, other locations referenced can be found in the figur


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a 32-

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stem

Am486 Microprocessor (M14)

The PCI CDP includes an Am486 microprocessor in a 168-pin, pin-grid-array package (part U25). The microprocessor is zero-insertion-force (ZIF) socketed and a CPU fan heat sink is provided for cooling. For debugging and analysis, access is provided to the Am486 microprocessor’s JTAG debugging port and to all of tmicroprocessor signals, and support is provided for Intel-compatible in-circuemulators. See “Development Support” on page 2-15.

The Enhanced Am486DX Microprocessor Family boosts system performancincorporating a 16-Kbyte cache to the existing flexible clock control and enhanSystem Management mode (SMM) features of a 486 CPU. The Enhanced Am486DX Microprocessor Family has the following characteristics:

• Industry-standard write-back cache support

• Frequent instructions execute in one clock

• 105.6-million bytes/second burst bus at 33 MHz

• Flexible write-through and write-back address control

• Advanced 0.35-µ CMOS-process technology

• 3.3-V or 3.45-V core with 5-V tolerant I/O

• Dynamic data bus sizing for 8-, 16-, and 32-bit buses (the PCI CDP uses bit data bus)

• 32-bit address bus

• 32-bit registers

• Supports “soft reset” capability

• 16-Kbyte unified code and data cache

– Four-way set-associative

– Write-through or write-back policy (the PCI CDP uses write-back policy

• Floating-point unit

• Paged, virtual memory management

• Stop clock control for reduced power consumption

• Industry-standard two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating sy


• Static design with Auto Halt power-down support

• Wide range of chipsets supporting SMM available to allow product differentiation (the PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset)

• Support available through the AMD FusionE86 Program


Figure 2-4. Am486 Microprocessor Block Diagram

A31–A2BE3–BE0

ADS, W/R, D/C,M/IO, PCD, PWT, RDY, LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA,RESET, INTR, NMI, FERR, UP, IGNNE, SMI, SMIACT, SRESET

VOLDET

VCC, VSS

CLK

STPCLKCLKMUL

Central andProtectionTest Unit

ControlROM

InstructionDecode

Barrel Shifter

ALU

Register File

SegmentationUnit

DescriptorRegisters

Paging Unit

Limit andAttribute

PLA

Cache Unit

Prefetcher

AddressDrivers

Bus ControlRequest

Sequencer

Data BusTransceivers

Burst BusControl

Bus SizeControl

CacheControl

ParityGenerationand Control

24

32

24

2 32

32

128

DecodedInstructionPath

CodeStream

PCD, PWT

24

Displacement Bus

Bus Interface

D31–D0

BRDY, BLAST

BS16, BS8

KEN, FLUSH,AHOLD, CACHE, EADS, INV, WB/WT, HITM

PCHK,DP3–DP0

TDI, TCK,TDO, TMS

PowerPlane

Micro-instruction

ClockGenerator

WriteBuffers4x32

CopybackBuffers4x32

WritebackBuffers4x32

TranslationLookaside

Buffer

16-KbyteCache

32-ByteCode Queue2x16 Bytes

JTAG

ClockInterface

PhysicalAddress

FloatingPointUnit

FloatingPoint

RegisterFile

32-Bit Data Bus

32-Bit Linear Address

32-Bit Data Bus

PhysicalAddress


89

7)”

CI

e

nd

SELserts r

evice

Core Logic Chipset (M8, I13, D15)

The PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset. The chipset consists of two very-large-scale-integration (VLSI) devices that provide bus interface and peripheral functions used in the system, plus an M5042 keyboard and mouse controller. See “Keyboard (O1)” on page 2-31.

The M1489 Cache, Memory, and PCI Controller (often called a northbridge chip) interfaces the Am486 microprocessor to the memory and PCI bus. The M14(part U5 at location M8) performs the following functions:

• Controls DRAM accesses and refresh cycles. See “DRAM Main Memory (Pon page 2-20

• Provides a 33-MHz, PCI 2.0-compliant interface with 5-V signalling. See “PBus (I7)” on page 2-19

• Maintains Level-1 and Level-2 cache coherency for PCI-master-initiated memory cycles. See “Level-2 Cache Memory (K19–N19 and N11)” on pag2-20

• Provides an IDE controller for a hard disk drive. See “IDE Hard Drive (L4 aM4)” on page 2-31

The PCI CDP routes three PCI address signals via series resistors to the ID pins on the two PCI slots and the onboard Ethernet controller. The chipset asone of these signals to configure each device according to the device numbewritten to the chipset’s configuration address register. Table 2-2 relates each dto its device number and signal routing.

Table 2-2. PCI Configuration Addressing

PCI Device Device Number

PCI Address Signal

PCI ID Select Signal

See App. B schematics on:

Slot SLT1 Device 3 PAD19 PCIID1 Sheet 11

Slot SLT2 Device 4 PAD20 PCIID2 Sheet 11

Ethernet Controller

Device 5 PAD21 PCIID3 Sheet 11, Sheet 13


vices es

)”

ters. d the

y s pins M es in ut to

All PCI bus signals are routed to logic analyzer headers. See “DevelopmentSupport” on page 2-15.

The M1487 ISA Bridge Controller (often called a southbridge chip) interfaces the ISA bus to the PCI bus and provides standard, PC-compatible peripherals decommon to desktop computers. The M1487 (Part U21 at location I13) providthe following peripheral functions:

• Two 82C59 interrupt controllers

• One 82C54 programmable interval timer

• Two 82C37 DMA controllers

• A real-time clock (RTC) (optional on the CDP, see “Real-Time Clock (G17on page 2-27)

• External boot ROM decoding

The M1487’s integrated peripherals are configured for standard PC-AT compatibility, so there is not much flexibility in assigning interrupts and DMAchannels.

The M1487 also contains the PCI bus arbiter, which allows three additional masThe PCI CDP board uses one master request/grant interface for the onboarAm79C972 Ethernet controller. The other two master interfaces are routed toPCI expansion slots.

The M1489 and M1487 communicate with each other across their proprietarLinkBus. The LinkBus has no separate pins, but instead uses the CPU addresA2 to A17. The LinkBus handles the RTC, keyboard controller, and boot ROtransactions as well; this is why CPU address pins are routed to these devicthe schematics. The chipset asserts the Am486 microprocessor’s AHOLD inpthree-state its address pins when the LinkBus is in use.


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ess

any

e, as

he

m or t he

is ge

lities

Onboard Ethernet Controller (F7)

The PCI CDP includes an onboard, full-duplex 10/100BaseT Ethernet port based on the AMD Am79C972 PCnet™-FAST+ Ethernet Controller (part U51). A separate voltage regulator provides 3.3-V power for the Ethernet controller. The Ethernet port is part J10 at location E1 on the board. Three LEDs near the port indicate transmit and receive activity and link speed. The link LED lights if 100 Mbit/s operation is established.

The Ethernet controller’s interrupt output (INTA) is routed to the chipset’s PCINT2 signal. The initialization code dynamically assigns INT2 to an interrupt request (IRQ) in the chipset’s PCI INTx routing table mapping registers. Seechipset documentation for details on the mapping registers.

The Am79C972 PCnet-FAST+ device is a highly integrated 10/100 Mbps PCI Ethernet controller. It includes an IEEE 802.3-compliant Ethernet Media AccController (MAC) with Auto-Negotiation of 10 or 100 Mbps and half- or full-duplex operation, and a Media Independent Interface (MII) for connection to standard IEEE 802.3 compliant 10/100 Mbps physical layer (PHY) device.

The Am79C972 contains a high performance 32-bit PCI bus master interfacwell as large, flexible internal memory buffers, to provide high-speed data throughput and low CPU and system bus utilization. For PCI configuration, tEthernet controller is accessed as device number 5.

The Am79C972 can be configured by the PCI configuration space mechanisit can download its configuration from a 1-Kbyte serial EEPROM (part U54 alocation D6). The PCI CDP uses the serial EEPROM interface to configure tAm79C972 device. The EEPROM is preprogrammed with an Ethernet configuration suitable for the PCI CDP.

In addition to the Ethernet configuration EEPROM, a 4-Kbyte serial EEPROMprovided for user nonvolatile data. See “4-Kbyte Serial EEPROM (C4)” on pa2-14.

For customer designs, the PCnet-FAST+ controller is offered with AMD’s extensive suite of industry-proven PCnet software drivers, remote boot ROMfirmware (not supported by the PCI CDP), and a complete set of supporting utiand design tools. Follow the Networking link at www.amd.com for information about networking software, support, and tools.


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e

ed yte lt), sed

trieve

the ble

The PCnet-FAST+ device supports the industry’s Net PC specification. The PCnet-FAST+ device also complies with Microsoft’s PC97 and PC98 requirements bfully supporting the OnNow and ACPI power management initiatives; howevthe PCI CDP does not implement OnNow or ACPI. A customer design couldsupport these technologies by using an ATX-style power supply and motherbdesign.

4-Kbyte Serial EEPROM (C4)

An extra NM93C66M8 4-Kbyte serial EEPROM (part U81) is connected to thAm79C972 Ethernet controller’s serial EEPROM interface. This provides additional EEPROM space for storing user nonvolatile data.

The M1487 device’s CLKCTL signal (controlled via chipset register 40h) is usto multiplex the Ethernet controller’s EEPROM chip select between the 1-KbEEPROM and the 4-Kbyte EEPROM. When CLKCTL is asserted (the defauthe Ethernet controller’s 1-Kbyte configuration EEPROM (part U54) is accesnormally. When CLKCTL is deasserted, the Ethernet controller’s EEPROM interface registers can be used to access the 4-Kbyte EEPROM to store or reuser data. See Sheet 13 of the schematics in Appendix B.

Software for using the 4-Kbyte EEPROM is provided with the PCI CDP. Seereadme file on the diskette that came with your kit for information about availautilities.


) vides The

rt is

lyzer. atible n be the tics

Development Support

The PCI CDP includes the following facilities for development support:

• JTAG port

• CPU-bus and PCI-bus logic analyzer headers

• Port 80 and Port 680 hexadecimal displays

• TIP board interface

These features are described in the following paragraphs.

JTAG Ports (Q14 and D17)The Am486 microprocessor provides an IEEE Standard 1149.1-1990 (JTAGcompliant test access port and boundary-scan architecture. The JTAG port proa scan interface for testing the microprocessor in a production environment.microprocessor’s JTAG port is available on connector J35 at location Q14.

Do not attempt use the second JTAG port (part P48 at location D17). This po

used at AMD to program the Vantis™ MACH® programmable logic device. Reprogramming of the MACH device can cause improper system operation. The MACH device controls the ISA Flash memory space and the Port 80h and 680h hexadecimal displays. See “ISA Flash Memory (F20)” on page 2-23 and “Hexadecimal Display (H23, J23)” on page 2-17.

Logic Analyzer HeadersThe CPU interface signals are buffered and routed to headers for a logic anaThe signals on the CPU bus logic analyzer headers are arranged to be compwith the disassembler for the HP 16500 Logic Analyzer, but any analyzer caused. Table 2-3 lists the available headers, their locations in Figure 2-3, andAppendix B schematics sheet on which they appear. Sheet 4 of the schemaincludes usage notes.


Table 2-3. Analyzer Headers

Part Description Location in Figure 2-3 on Page 2-5


P36 POD 4, Microprocessor data (GD) signals

P24 Sheet 4

P38 POD 3, Microprocessor data (GD) signals

M24 Sheet 4

P39 POD 2, Microprocessor control signals, plus LA qualifier (see note on schematics Sheet 4)

L11 Sheet 5

P40 POD 6, Microprocessor address (GA) signals

I17 Sheet 5

P41 POD 1, Microprocessor control signals

K16 Sheet 5

P42 POD 5, Microprocessor address (GA) signals, including logic-derived GA0 and GA1 signals

I20 Sheet 5

P43 PCI Address and Data (PAD) signals F11 Sheet 12

P44 PCI Address and Data (PAD) signals H9 Sheet 12

P45 PCI control signals C12–D13 Sheet 12

P46 PCI control signals C9–D10 Sheet 12

P47 POD 7, Miscellaneous microprocessor control signals

K10 Sheet 4


listed

per

0h I/O d

In addition to the logic analyzer headers, separate three-pin headers are provided for each PCI device’s bus request and bus grant signals. These headers arein Table 2-4:

In-Circuit Emulator Compatibility (M14, Q15–Q16)The PCI CDP can be used with an in-circuit emulator that mates to the pin-grid-array (PGA) zero-insertion-force (ZIF) socket in place of the Am486 microprocessor. To support emulators that use an Intel microprocessor, the necessary CPU power-supply jumpers are provided so the board will work with Intel 486 DX2 and DX4 chips. See “CPU Voltage Adjustment (Q15–Q16)” onpage 2-32.

When connecting an in-circuit emulator, risers might be required to allow proplacement relative to the microprocessor socket and the ISA slots.

Hexadecimal Display (H23, J23)The PCI CDP includes 2-digit hexadecimal displays for port 80h and port 68debugging messages. To change the display value, perform an 8-bit write toport 80h or 680h, respectively. The value written is latched by the display ancannot be read back by software.

Table 2-4. PCI Bus Master Test Points

Part Signal Location in Figure 2-3 on Page 2-5


JP29 PREQJ0PGNTJ0GND

I6 Sheet 12


K5 Sheet 12


E7 Sheet 12


rrupt Q ssing

PC TIP

Test Interface Port (TIP) (A16)The PCI CDP includes a connector for the AMD Test Interface Port (TIP) board. The TIP board is used for testing and debugging AMD embedded product customer development platforms. It connects through a ribbon cable to the TIP connector on the platform.

The TIP board provides a collection of peripherals, such as LEDs, hexadecimal displays, an LCD display, two serial ports, a parallel port, an Ethernet controller, and Flash memory, that can be convenient in system development.

The PCI CDP’s TIP connector resides on the ISA bus and can use the ISA interequest (IRQ) signals if a TIP board is connected. Individual TIP connector IRsignals are listed in Table 2-5. See the TIP board documentation for I/O addreinformation.

NOTE: The TIP board’s IRQ usage can conflict with the PCI CDP’s onboard peripherals. Some TIP or CDP peripherals may not operate correctly when theboard is in use.

Table 2-5. TIP Interrupt Usage

TIP Function Interrupt

TIP Ethernet IRQ15

TIP parallel port IRQ12

TIP serial port 1 IRQ11

TIP test function IRQ14

TIP serial port 2 IRQ10


tion,

is 2-11.

(The et’s r

PCI Bus (I7)

The PCI CDP has two desktop-PC-style PCI expansion connectors (parts SLT1 and SLT2) to allow the installation of a wide array of off-the-shelf 5-V PCI devices. These include standard devices such as video, sound, SCSI, or PCMCIA adapters, or diagnostic devices such as PCI bus analyzers, extender cards, and other diagnostic hardware. The slots do not support 3.3-V PCI peripherals. The PCI bus is implemented via the chipset’s M1489 northbridge chip except for bus arbitrawhich is handled by the M1487.

For PCI bus configuration, connector SLT1 is addressed as Device 3 and SLT2addressed as Device 4. See Table 2-2, “PCI Configuration Addressing,” on page

The PCI bus connector’s interrupt signals are routed as shown in Table 2-6. Ethernet interrupt signal is also shown for reference.) The initialization codedynamically assigns PCI interrupts to an interrupt request (IRQ) in the chipsPCI INTx routing table mapping registers. See the chipset documentation fodetails on the mapping registers.

Table 2-6. PCI Bus Interrupt Routing

PCI Bus Interrupt PCI Slot 1 Signal PCI Slot 2 Signal Ethernet Signal

INT0 INTA INTD —

INT1 INTB INTA —

INT2 INTC INTB INTA

INT3 INTD INTC —


set’s

of

sing or

Ms

Level-2 Cache Memory (K19–N19 and N11)

The PCI CDP includes an onboard 512-Kbyte, single-bank, direct-mapped, unified Level-2 cache. This is the largest single-bank cache allowed by the chipset. The cache tag and data static RAM (SRAM) devices are soldered onto the PCI CDP board. A 10-ns tag SRAM device and 15-ns data SRAM devices are used to achieve 2-1-1-1 timing on reads and 2-2-2-2 on writes.

The tag SRAM is a single 32-K by 8-bit device, part U11, and the data SRAMs are 128-K by 8-bit devices, parts U7, U8, U9, and U10.

Chipset registers allow the level-2 cache to be disabled or enabled. The level-2 cache can be configured for either write-back or write-through operation.

NOTE: The benefit of level-2 cache varies, depending on the software being used.

DRAM Main Memory (P7)

The PCI CDP comes with three standard, 5-V, 72-pin single inline memory module (SIMM) sockets, populated with three 16-Mbyte, 60-ns, extended data out (EDO) SIMMs.

The included SIMMs provide the largest and fastest DRAM configuration allowed in this design. For customer designs, the SIMM configurations supported depend upon the chipset and the initialization or BIOS code used to configure the chipregisters. See the chipset documentation for information about detecting andconfiguring DRAM. The BIOS provided will automatically detect the amount DRAM installed.

The chipset used in this design supports 2-, 4-, 8-, 16-, or 32-Mbyte SIMMS u4- or 16-Mbit technology DRAM chips. Either fast page mode (FPM) or EDOSIMMs can be used, and the sockets can be filled with a combination of FPMEDO SIMMs. All installed SIMMs must be run at the same speed, however.

The chipset allows either 1, 2, or 3 DRAM banks. Single- and double-bank SIMcan be combined as shown in Table 2-7 on page 2-21.


87

oot y.

ns. ISA-

e (at

ess cted

Table 2-7. SIMM Socket Population Chart

NOTE: 32- or 36-bit-wide memory can be used. However, 36-bit EDO SIMMs are accessed as only 32 bits wide because the FINALi chipset does not support EDO SIMMs’ 32-bit data plus 4-bit error correction code (ECC) format. Onlytraditional byte-wide parity is supported.

Boot ROM (C16)

The PCI CDP provides a 0.5-inch wide 32-pin DIP socket (part U14) for an initialization or BIOS ROM device. The boot ROM is implemented on the M14chip’s LinkBus.

The boot ROM socket is populated with a BIOS that allows the PCI CDP to band run DOS, Windows, or a real-time operating system (RTOS) immediatel

The platform must always boot from the boot ROM because of chipset limitatioThe chipset does not allow booting from another source such as DRAM-bus, bus, or PCI-bus memory.

The boot ROM address space size defaults to 128 Kbytes, using ROM devicaddress bits A0–A16, but the board design provides jumpers JP32 and JP33locations C14 and B14) for configuring the ROM device’s A17 and A18 addrsignals. The jumpers allow these address bits to be left High, tied Low, or conneto their corresponding ISA bus signal. This provides flexibility in addressing various sized Flash memory or ROM devices. See Figure 2-5 on page 2-22

SIMM 0 SIMM 1 SIMM 2

Single Bank SIMM Single Bank SIMM Single Bank SIMM

Double Bank SIMM Single Bank SIMM —


h. If

ipset

FFh that

a top is mp, cution

de

adow

Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)

By default, jumpers JP32 and JP33 are not connected, so ROM device pins A17 and A18 are tied High to address the 128-Kbyte BIOS range, E0000h–FFFFFthese jumpers are changed to select ISA addressing for addresses C0000h–DFFFFh, software must enable ROM addressing for this space via chregister index 12h, bits 2–1, and index 44h, bits 7–6.

For software compatibility, the boot ROM image appears from E0000h to FFFin the Am486 microprocessor’s lower 1-Mbyte address space. (This assumesa 128-Kbyte boot ROM is used.) At reset, however, the microprocessor is inspecial state that causes it to fetch its first instruction from FFFFFFF0h, at theof its extended memory range. To provide the first instruction, the boot ROMaliased to begin at FFFE0000h. One of the first instructions is typically a far juwhich ends the special state and causes the microprocessor to continue exein the lower 1-Mbyte space.

Because boot ROM accesses are relatively slow, subsequent initialization cotypically copies the boot ROM contents into DRAM space and configures thechipset’s Shadow Region Register to direct all boot ROM accesses to this shimage of the boot ROM.

JP32JP33

Boot ROMROM Pin

ISA Signal(SA17 or SA18)

(A17 or A18)

5 V

ROM Jumper Locations Individual Jumper Schematic

1 2 31 2 3

(SA18) (SA17)

1 2 3


OM nge d. If

only

d. it A0 When serts

lash are the

pport ry rger 16 vely ory

ISA Flash Memory (F20)

The PCI CDP includes 1 Mbyte of 16-bit wide AMD Flash memory soldered onto the board and located logically on the ISA Bus. A Vantis MACH programmable logic device is used to control the interface between the ISA bus and the Flash device. This provides an example of how a small amount of ISA Flash memory might be implemented in customer designs.

The ISA Flash memory employs one Am29F800 top-sector boot block Flash memory chip (part U58). This device occupies ISA memory space from address F00000h to FFFFFFh. See Figure 2-6 on page 2-24. Software should access this space in 16-bit words on even addresses.

Software can enable this ISA memory space by setting bit 3 of the chipset’s RFunction Register, index 12h. This disables DRAM access in the 1-Mbyte rafrom F00000h to FFFFFFh, allowing access to the ISA memory space insteabit 3 of index 12h is clear, access to the ISA Flash memory space is allowedif 15 Mbytes or less of DRAM is installed.

The Flash device is configured in word mode, so only 16-bit access is alloweThe ISA address signals are routed so that ISA address bit A1 is routed to bon the Flash device, so it can only be addressed on even word boundaries. generating Flash command sequences, multiply the Flash address by two togenerate the correct ISA address. For example, writing address F00AAAh as555h (AAAh÷ 2) on the Flash device’s address pins.

The Am29F800 can be programmed using the JDEC single-power-supply Fstandard command set. See the Am29F800 documentation for details. Softwfor using Flash memory is provided with the PCI CDP. See the readme file ondiskette that came with your kit for information about available utilities.

ISA space is limited to 16 Mbytes, and because the chipset provides limited sufor mapping ISA memory windows over DRAM, only 1 Mbyte of Flash memois provided. However, in a customer design with a small amount of DRAM, a laISA Flash memory space can be situated between the top of DRAM and theMbyte ISA address limit. Note that access to memory on the ISA bus is relatislow when compared to DRAM or PCI bus transactions. See “EIP Flash Mem(L21)” on page 2-25 for another approach.


Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory

100000h

(15 Mbyte) EFFFFFh

000000h

(16 Mbyte) FFFFFFh

(1 Mbyte) 0FFFFFh

F00000h

ISA Flash Memory

(56 Mbyte) 37FFFFFh

DRAM

DRAM (48 Mbyte) 2FFFFFFh

1000000h

3000000h

EIP FlashBank 1

} Enabled ViaChipset Register12h, Bit 3

EIP FlashBank 0

(52 Mbyte) 33FFFFFh3400000h

EIP Location Depends on DRAM Size

Accessed as Fourth DRAM Bank (Bank 3)}

DRAM

128 Kbyte Boot ROM


00B 5, lash

he ).

’s ble t),

access al data sing F800 the tion

to the vel-2 is

EIP Flash Memory (L21)

The PCI CDP includes 8 Mbytes of Flash memory for execute-in-place (EIP) applications. The EIP Flash memory is implemented in the fourth bank (bank 3) of the DRAM controller’s address space. This memory consists of eight 29F8top-sector boot block Flash memory devices (parts U61, U62, U63, U64, U6U66, U67, and U68), soldered to the board and organized as two 32-bit wide Fmemory banks.

The EIP Flash memory is controlled by an AMD 22V10 PAL® device programmed to act as a simple DRAM-to-Flash interface that makes the Flash memory appear to the M1489 DRAM controller as a single bank of 32-bit-wide EDO DRAM.

The provided BIOS enables the EIP Flash memory and configures the other DRAM banks accordingly. To enable the EIP Flash memory, the BIOS programs the chipset’s DRAM Configuration Register 2 (index 11h, bits 4–7) so the fourth DRAM bank is accessed as 2-Mbyte by 8 (11 row, 10 column) DRAM chips. TDRAM-to-Flash interface uses CPU address bit A22 for Flash memory bankswitching (A22 is routed to DRAM address bit 8 in the selected configurationBecause of timing requirements, it is also necessary to program the chipsetDRAM Configuration and Timing Control registers (index 1Ah and 1Bh) to disahidden refresh, disable RAS-only refresh, select Fast access mode (not Fastesand select CAS before RAS refresh. This affects all four DRAM banks.

The EIP Flash memory can be accessed only by the CPU (no PCI bus-master to the EIP Flash is allowed), and all accesses are 32 bits wide. During normoperation, the EIP Flash memory can be read like other DRAM memory, but cannot be written directly. Instead, the Am29F800 devices are programmed uthe JDEC single-power-supply Flash standard command set. See the Am29documentation for details. Software for using Flash memory is provided withPCI CDP. See the readme file on the diskette that came with your kit for informaabout available utilities.

Software that writes to the EIP Flash memory must make sure that accessesFlash memory are not cached. This can be done by disabling Level-1 and Lememory caching, or by appropriate programming of the page tables if pagingenabled in the microprocessor.


e se

ddress RAM 0–2.

ank. bit A0 te (32-

ress. 8h

Software that writes to the EIP Flash memory must also avoid any back-to-back write cycles (including back-to-back non-burst cycles) to the EIP Flash memory space. For reliable writes, always read or write a different DRAM bank (0, 1 or 2) before and after writes to the EIP space. For example, read location 00000h, write a value to Flash memory, and then read location 00000h again. (Simply running the Flash programming software in the normal DRAM space does not ensure reliable Flash programming, even though caching is disabled.)

Reading the EIP Flash memory does not entail any of the timing restrictions that apply to writes. The microprocessor can read EIP Flash memory with any combination of single-beat or burst read cycles.

The EIP Flash memory itself is organized in two banks. The base address of each EIP bank depends on how much DRAM is installed in DRAM banks 0–2. Thboard is shipped with 48 Mbytes installed, so by default the EIP first bank baaddress is 3000000h (48 Mbytes + 1 byte), and the EIP second bank base ais 3400000. See Figure 2-6 on page 2-24. Software can query the chipset’s DConfiguration Registers (index 10h and 11h) to determine the size of banks See the chipset documentation for a description of these registers.

Each Flash device is configured in byte mode, with four devices in each EIP bThe CPU address signals are routed so that CPU address bit A2 is routed to on the Flash devices, so the EIP space can only be addressed on even 4-bybit double-word) boundaries. When writing to the devices’ control registers, multiply the byte-mode register offset by four to generate the correct CPU addFor example, if the bank base address is 3000000h, writing address 3002AAasserts AAAh (2AA8h÷ 4) on each Flash device’s address pins.


ed C is

uch

with t the OS is some TC

ister

rupt

gister

hile

by I14.

Real-Time Clock (G17)

The real-time clock (RTC) function in the chipset’s 1487 chip is initially disablon the PCI CDP. Instead, a separate DS1685 year-2000 (Y2K)-compliant RTenabled.

The DS1685 provides the features of widely-used, non-Y2K-compliant RTCs sas the DS1287. In addition, the DS1685 provides a byte for storing century information, plus other registers and features not found in older RTC chips.

Because of its extra features, the DS1685 RTC is not completely compatiblethe DS1287. The provided BIOS operates correctly with the DS1685 RTC, buextra RTC features can cause unexpected behavior if a customer-supplied BIused in PC-AT compatible systems. One example is that the DS1685 providesinterrupt sources that are not present in the DS1287 RTC. Customer-writteninitialization software can take the following steps to disable the extended Rinterrupts:

1. Set the DV0 bit in CMOS register A to enable access to the extended regbank in the DS1685.

2. Write a value of 60h to CMOS address 4Bh to disable the extended interaddresses.

3. Clear the Dv0 bit in CMOS register a to disable access to the extended rebank (so that legacy software behaves as expected).

4. Read CMOS register C to clear any pending interrupts that were triggered wthe extended interrupts were enabled.

For DS1685 RTC programming details, see the DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data Sheet, and Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via Software, available from Dallas Semiconductor, www.dalsemi.com.

If desired, the M1487’s internal RTC can be enabled instead of the DS1685 removing resistor part R58 from the back side of the board, beneath location(See Sheet 16 of the schematics in Appendix B.)


ed on “ISA

if this -21. sing

tput

as et for

ISA Bus Interface (A7)

The PCI CDP is populated with two standard ISA bus connectors (parts SL1 and SL2) for developers who need to use ISA devices in their development systems. The ISA bus interface is provided by the chipset’s M1497 southbridge.

ISA devices that use the F00000h to FFFFFFh address space cannot be usthe PCI CDP, because this area is used by the ISA Flash memory bank. SeeFlash Memory (F20)” on page 2-23.

ISA devices that use the C0000h to DFFFFh address space cannot be usedspace is enabled for boot ROM addressing. See “Boot ROM (C16)” on page 2Boot ROM addressing in this range might also cause conflicts with devices uthe D0000h to DFFFF address space.

Super I/O (C19)

The PCI CDP uses an M5113 Super I/O chip to provide standard PC input/oufunctions. The Super I/O chip provides:

• Two 16450/16550-compatible serial ports • IrDA 1.0 infrared interface• AT-compatible parallel port• 82077-compatible floppy disk interface

The BIOS supplied with the platform configures these peripherals to operatethey would on a standard PC. See the Acer Laboratories Inc. M5113 data shedetailed configuration information.


ese ble 2-

rDA RT

hip. 13 ort.

Serial Ports (E23 and C23)The platform’s Super I/O device includes two 16550-compatible serial ports. Thare routed to two 9-pin D-shell connectors, J8 and J9. See Figure 2-7 and Ta8. Light-emitting diodes (LEDs) are provided near each serial port to indicatetransmit and receive activity.

Figure 2-7. Serial Port Connector Pins (J8, J9)

Table 2-8. Serial Port Pin/Signal Table

IrDA Interface (A19) The Super I/O device is configured to support infrared data transfers via an ILED module, part U44. The serial data transmission rates include all of the UAbit rates (up to 115 Kbps).

The IrDA LED module is connected to dedicated pins on the M5113 Super I/O cThe IrDA interface shares one UART with serial port COM2. A control bit in the M51chip controls whether the UART communicates over the COM2 port or the IrDA pSee the M5113: Enhanced Super I/O Controller Data Sheet, available from Acer Laboratories Inc. See www.acerlabs.com for contact information.

Pin Signal

1 DCD

2 RXD

3 TXD

4 DTR

5 GND

6 DSR

7 RTS

8 CTS

9 RIN

1 5

96Notes:See Figure 2-3 on page 2-5 for connector locations.


e ppy oard

Parallel Port (A22) Figure 2-8 and Table 2-9 show the parallel port pinouts.

Figure 2-8. Parallel Port Socket (J4)

Table 2-9. Parallel Port Pin/Signal Table

Floppy Disk Drive (E20) The PCI CDP’s Super I/O chip provides a floppy disk controller to support thsystem’s floppy disk drive connector (part J6). Either a 5.25-inch or 3.5-inch flodisk drive can be installed with a standard 34-pin connector. For details, see “BInstallation” on page 1-4.

Pin Signal

1 STRB

2–9 PD0–PD7

10 ACK

11 BUSY

12 PE

13 SLCT

14 AFDT

15 ERROR

16 INIT

17 SLCTIN

18–25 GND

13 1

1425Notes:See Figure 2-3 on page 2-5 for connector locations.


.

es r J7 y

e is ter. If n the as an

1) 79

ven

IDE Hard Drive (L4 and M4)

The PCI CDP contains two standard 40-pin IDE connectors (parts J5 and J7). The M1498 chip provides the IDE hard drive controller. For details on how to connect a single IDE hard drive to the PCI CDP, see “Board Installation” on page 1-4

An LED is located next to each IDE connector to indicate IDE activity. IDE devicon connector J5 can generate interrupts on IRQ14, and devices on connectocan generate interrupts on IRQ15. This interrupt mapping can be changed breprogramming the chipset configuration registers.

Each connector supports one master and one slave device. If only one devicattached to an IDE connector, that device must be configured as an IDE masa two-position cable is used to attach two devices to a single IDE connector oboard, one of the devices must be configured as an IDE master and the otherIDE slave. See each IDE device’s documentation for configuration details.

Keyboard (O1)

The PCI CDP provides a standard AT-compatible keyboard connector (part Jimplemented via the chipset’s M5402 mouse/keyboard controller chip (part Uat location D15).

Mouse (M1)

A port is provided for a PS/2-style mouse (connector J11). This device is driby the M5402 mouse/keyboard controller chip.


and

.

CPU Voltage Adjustment (Q15–Q16)

The CPU power supply voltage can be adjusted by moving jumper JP4 or both jumpers JP2 and JP3 on the PCI CDP. Selectable voltages are 2.5 V, 3.3 V, 3.45 V, or 5 V. Figure 2-9 shows the default configuration of the CPU voltage jumpers (set for 3.45 V).

To select either 3.3-V or 2.5-V CPU voltage, leave JP2 and JP3 set to “ADJ”move jumper JP4 to the desired voltage.

To select 5-V operation, move both jumpers JP2 and JP3 to their “5 V” position

Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16)

CAUTION: Jumpers JP2 and JP3 must both be placed in the same position. Positioning JP2 and JP3 differently can damage the PCI CDP.

ADJ

5 V

3.45 V

2.5 V

ADJ

5 V

JP3JP2

JP4

3.3 V

!


rectly

Power Supply Connectors (N2 and P2)

The PCI CDP accepts standard PC-style motherboard power connectors to supply power to the CPU and all onboard components. To ensure proper functionality of the power module, the board’s PC power supply sockets must be inserted coronto the board.

CAUTION: It is important that the ground wires of one connector are adjacent to the ground wires of the other.See Figure 2-10.

Figure 2-10. Ground Wire Connections

!GND GND

-12

+12

+5+5

-5

Edge of Board

IDE Connector Power Supply Conn.

PS2 Power Conn

PW

G

Back of


Reset and Interrupt Switches and Headers

Three push-button switches are provided so the user can generate RESET, SMI, and NMI events. In addition, a two-pin header is provided for the RESET signal so that an external pushbutton switch can be attached. These switches and headers are routed to the appropriate chipset signals as listed in Table 2-10.

Table 2-10. Switch Summary

Embedded BIOS software typically enters its debugging monitor when an NMI event is generated. In addition to pressing the NMI switch, an NMI event can be caused by a PCI-bus parity error, a DRAM parity error, or an ISA-bus IOCHCK error.



SW1,JP34

PWG Used to reset the system. N5, K23 Sheet 17

SW2 NMI Used to generate an NMI event.

K6 Sheet 17

SW3 EXTSMI Used to generate an SMI event.

H11 Sheet 17


Resistor Options

The PCI CDP includes a number of resistor populate/depopulate options, which are listed in Table 2-11. Many are used only as manufacturing options, but some may be useful for exploring design options or better emulating a target design.

Table 2-11. Resistor Options



R11 CLKMUL When R11 is populated and R148 is removed, the clock multiplier for an Am486DX2-66 microprocessor is selected.

M17 Sheet 2

R58 ENRTC When populated (the default), the M1487 chip’s internal RTC is disabled and the DS1685 Y2K-compliant RTC is enabled.

I14 (back side)

Sheet 16

R59 CMPSTJ When removed (the default), the 1X CPU-to-PCI bus frequency multiplier is selected. (1X is the only multiplier supported in this design.)

I14 (back side)

Sheet 16

R70 TURBO When R70 is removed and R71 is populated (the default), the M1487’s TURBO signal is High (asserted). This input must be enabled by software to have any effect.

I14 (back side)

Sheet 17

R71 TURBO When R71 is populated and R70 is removed (the default), the M1487’s TURBO signal is asserted. This input must be enabled by software to have any effect.

I14 (back side)

Sheet 17

R93 CLKPU2 When R93 is populated and R176 is removed, the system clock speed is 25 MHz.

J3 (back side)

Sheet 18


R145 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled.

D15 (back side)

Sheet 25

R146 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled.

D15 (back side)

Sheet 25

R148 CLKMUL When R148 is populated and R11 is removed (the default) the clock multiplier for an Am486DX4-100 or Am486DX5-133 microprocessor is selected.

M17 Sheet 2

R170 IBCSTJ When populated (the default), the M1487’s internal keyboard controller is disabled. (The M1487 internal keyboard controller function is discontinued. The M5042 is provided instead.)

I14 (back side)

Sheet 16

R176 CLKPU2 When R176 is populated and R93 is removed (the default), the system clock speed is 33 MHz.

J3 Sheet 18

Table 2-11. Resistor Options (Continued)




Appendix A

Default Settings

This chapter lists the default settings of the Am486 microprocessor PCI customer development platform when it is shipped.

Table A-1. Default Jumper Settings

Part Signal Location in Figure 2-3 on Page 2-5

Default Position Position Marking

JP2 CPUVCC3 Q15 Pins 2–3 “ADJ”

JP3 CPUVCC3 Q16 Pins 2–3 “ADJ”

JP4 CPUV1, CPUV2,CPUV3

R15 Pins 1–2 “3.45 V”

JP32 Boot ROM A17

C14 No connection (No marking)

JP33 Boot ROM A18

B14 No connection (No marking)

Am486® Microprocessor PCI Customer Development Platform A-1

Am486® Microprocessor PCI Customer Development Platform User’s ManualA-2

Appendix B

Bill of Materials and Schematics

The bill of materials for the Am486 microprocessor PCI customer development platform (CDP) begins on page B-2.

The actual schematics used to build the PCI CDP begin on page B-10.

Am486® Microprocessor PCI Customer Development Platform B-1

Board Bill of Materials (BOM)

Item Qty. Reference Part Package Description

1 119 C1, BC1, BC2, C3, BC3, C4, BC4, C5, BC5, C6, BC6, C7, BC7, C8, BC8, BC9, BC10, BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19, BC20, BC21, BC22, BC23, BC24, BC25, BC26, BC27, BC28, BC29, BC30, BC31, BC32, BC33, BC34, BC35, C36, BC36, C37, BC37, C38, BC38, C39, BC39, BC40, BC41, BC42, BC43, BC44, BC45, BC46, C47, BC47, C48, C50, C52, C65, C67, C69, C70, C71, C72, C73, C74, C75, C76, C77, C79, C80, C81, C82, C88, C89, C90, C91, C92, C93, C94, C95, C100, C105, C111, C112, C114, C115, C122, C123, C124, C125, C126, C127, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C156, C157, C160, C166, C167, C168, C169, C170, C171, C172, C173, C174

0.1 µF 805 RC0805, X7R, ±10%, 50 V

2 1 BT1 3 V Coin cell (socket) KEYSTONE 103 or 106

3 14 C9, C10, C11, C12, C13, C34, C35, C83, C96, C97, C102, C103, C104, C109

0.01 µF 805 RC0805, X7R, ±10%, 50 V

4 6 C14, C28, C58, C64, C158, C159

47 pF 805 RC0805, NPO, ±5%, 50 V

5 33 C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C29, C30, C31, C32, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153

180 pF 805 RC0805, NPO, ±10%, 50 V

Notes:

An asterisk (*) indicates parts that are not populated.

Am486® Microprocessor PCI Customer Development Platform User’s ManualB-2

6 10 C33, C41, C42, C43, C46, C56, C57, C60, C66, C154

15 pF 805 RC0805, NPO, ±5%, 50 V

7 1 C40 1000 pF 805 RC0805, 1/8 W, ±5%, 50 V

8 2 C44, C45 39 pF 805 RC0805, NPO, ±5%, 50 V

9 4 C53, C54, C155, C161 10 pF 805 RC0805, NPO, ±5%, 50 V

10 1 C55 22 pF 805 RC0805, NPO, ±5%, 50 V

11 1 C68 6.8 µF C-CASE TANTALUM, C-CASE, 16 V, ±20%

12 2 C86, C78 2.2 µF B-CASE TANTALUM, B-CASE, 20 V, ±20%

13 23 TC2, TC3, TC9, TC11, TC12, TC13, TC14, TC15, TC16, TC17, TC18, TC19, TC22, TC23, TC24, TC25, C84, C87, C106, C107, C108, C110, C113

10 µF C-CASE TANTALUM, C-CASE, 16 V, ±20%

14 1 C85 1 µF A-CASE TANTALUM, A-CASE, 16 V, ±20%

15 2 C98, C99 33 pF 805 RC0805, NPO, ±5%, 50 V

16 1 C101 0.001 µF, 2 KV (MIN.)

TH SPRAGUE 30GAD10

17 4 C162, C163, C164, C165 0.015 µF 805 RC0805, X7R, ±10%, 50 V

18 6 D1, D5, D6, D7, D8, D9 MMBD4148 (SOT23) SOT-23 VISHAY MMBD4148

19 1 D10 LED (SOT23) SURSOT-23

LUMEX SSL-LX15IC-RP

20 4 D11, D12, D13, D14 LED (SOT23) SURSOT-23

LUMEX SSL-LX15GC-RP

21 2 D15, D17 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LSGC


Notes:



22 2 D16, D18 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LEC

23 2 F1, F2 FUSE, 0.5A 1206 BUSSMAN 3216FF-500mA

24 1 HS1 HEATSINK (TO-220) THERMALLOY ML32

25 7 JP2, JP3, JP29, JP30, JP31, JP32, JP33

HEADER 3X1 TH-1X3 1X3 HEADER; 0.025” SQ. POST AMP 87224-3

26 1 JP4 HEADER 3X2 TH-2X3 1X3 HEADER; 0.025” SQ. POST AMP 103186-3

27 1 JP34 HEADER 2X1 TH-1X2 1X2 HEADER; 0.025” SQ. POST AMP 87224-2

28 1 J1 KYBD CONN TH AMP 212044-1

29 2 J2, J3 PWR-CN6 TH MOLEX 15-48-0106

30 1 J4 Parallel Port DB25 AMP 745967-7

31 2 J7, J5 CNN-40C TH-2X20-SHRD

2X20 HEADER; SHRD AMP 103308-8

32 1 J6 CNN-34C TH-2X17-SHRD


33 2 J8, J9 SERIAL PORT DB9 AMP 745410-1

34 1 J10 AMP RJ45A TH AMP 555153-1

35 1 J11 MOUSE_CON TH AMP 750329-2

36 1 LS1 SPEAKER ISL PROD. INTL. ISL-8032VT

37 9 L1, L2, L3, L4, L5, L6, L7, L8, L9

FB RC1206 MURATA ERIE BLM32A07

38 10 MT1, MT2, MT3, MT4, MT5, MT6, MT7, MT8, MT9, MT10

Mounting Hole

39 1 P31 COND60 AMPMOD50, 1X30, R-ANG

AMP 104069-7

40 2 P35, P48 HEADER2X5; SHRD TH-1X5-SHRD



Notes:



41 11 P36, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47

HP CONN TH-1X10-SHRD

3M:2520-6003UB or AMP 103308-5

42 1 Q1 MMBT3906 (SOT23) SOT-23 VISHAY MMBT3906

43 2 Q4, Q2 MMBT3904 (SOT23) SOT-23 VISHAY MMBT3904

44 1 Q5 TIP127 TO-220 MOTOROLA TIP127

45 9 RN1, RN2, RN3, RN4, RN8, RN9, RN10, RN11, RN12

33-8B CTS 743 08-3 330 J TR

46 7 RN5, RN6, RN7, RN13, RN14, RN15, RN16

22-8B CTS 743 08-3 220 J TR

47 12 RP1, RP2, RP5, RP6, RP7, RP12, RP14, RP16, RP17, RP18, RP19, RP20

10 K-10P SIP10 CTS 770 10 1 103 SP

48 2 RP4, RP3 1 K-10P SIP10 CTS 770 10 1 102 SP

49 6 RP8, RP9, RP10, RP11, RP15, RP21

4.7 K-10P SIP10 CTS 770 10 1 472 SP

50 1 RP13 330-8P SIP8 CTS 770 8 1 331 SP

51 19 R3, R4, R5, R13, R19, R49, R50, R52, R61, R64, R68, R76, R77, R91, R104, R131, R141, R142, R175

10 K 805 RC0805, 1/8 W, ±5%, 50 V

52 17 R6, R20, R21, R34, R58, R78, R85, R103, R105, R118, R130, R134, R170, R173, R174, R177, R178

1 K 805 RC0805, 1/8 W, ±5%, 50 V

53 5 R7, R8, R27, R81, R124 33 805 RC0805, 1/8 W, ±5%, 50 V

54 1 R11 *10 K 805 RC0805, 1/8 W, ±5%, 50 V

55 6 R14, R15, R16, R17, R18, R14722 805 RC0805, 1/8 W, ±5%, 50 V

56 11 R22, R31, R35, R36, R38, R41, R42, R54, R99, R100, R101

10 805 RC0805, 1/8 W, ±5%, 50 V

57 1 R23 27.4 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V


Notes:



58 1 R25 25.5 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

59 1 R26 15.8 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

60 10 R28, R94, R97, R135, R136, R137, R138, R156, R158, R160

330 805 RC0805, 1/8 W, ±5%, 50 V

61 1 R29 15.0 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

62 4 R30, R65, R139, R140 100 805 RC0805, 1/8 W, ±5%, 50 V

63 15 R33, R47, R57, R119, R120, R121, R122, R123, R127, R148, R163, R165, R167, R169, R176

0 805 RC0805, 1/8 W, ±5%, 50 V

64 9 R39, R44, R45, R75, R90, R92, R106, R171, R172

4.7 K 805 RC0805, 1/8 W, ±5%, 50 V

65 1 R48 51 K 805 RC0805, 1/8 W, ±5%, 50 V

66 1 R59 *1 K 805 RC0805, 1/8 W, ±5%, 50 V

67 5 R62, R63, R149, R150, R151 270 805 RC0805, 1/8 W, ±5%, 50 V

68 2 R70, R146 *2.2 K 805 RC0805, 1/8 W, ±5%, 50 V

69 9 R71, R80, R95, R96, R98, R145, R157, R159, R161

470 805 RC0805, 1/8 W, ±5%, 50 V

70 1 R79 10M 805 RC0805, 1/8 W, ±5%, 50 V

71 1 R93 *4.7 K 805 RC0805, 1/8 W, ±5%, 50 V

72 1 R102 47 805 RC0805, 1/8 W, ±5%, 50 V

73 1 R107 100, 1% 805 RC0805, 1/8 W, ±1%, 50 V

74 2 R108, R109 49.9, 1% 805 RC0805, 1/8 W, ±1%, 50 V


Notes:



75 4 R110, R111, R112, R113 75, 1% 805 RC0805, 1/8 W, ±1%, 50 V

76 3 R114, R115, R117 1.00 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

77 1 R116 22 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V

78 4 R152, R153, R154, R155 1.5 K 805 RC0805, 1/8 W, ±5%, 50 V

79 4 R162, R164, R166, R168 *0 805 RC0805, 1/8 W, ±5%, 50 V

80 3 SIMM1, SIMM2, SIMM0 SIMM72 AMP 822030-3

81 2 SLT1, SLT2 PCI Slot AMP 145154-4

82 2 SL1, SL2 ISA AT Connector AMP 645169-3

83 3 SW1, SW2, SW3 PBNO C&K KT11P2SM

84 4 TC1, TC4, TC7, TC10 47 µF D-CASE TANTALUM, D-CASE, 16 V, ±20%

85 4 TC5, TC6, TC20, TC21 10 µF D-CASE TANTALUM, D-CASE, 25 V, ±20%

86 1 TC8 100 µF E-CASE TANTALUM, E-CASE, 16 V, ±20%

87 1 T1 PE68515 PULSE ENGR. PE-68515

88 1 U1 74F245 SOL20 SIGNETICS 74F245D

89 1 U5 M1489 PQFP208 ALi M1489

90 1 U6 LP2951 SO8 NATIONAL LP2951CM

91 4 U7, U8, U9, U10 128 Kx8-15 SOJ32(0.3”/0.4”)

128 Kx8, 15 ns, Corner Vcc/GND Pins, SOJ32

92 1 U11 32 Kx8-15 SOJ28(.3”) 32 Kx8, 15 ns, Corner Vcc/GND Pins, 0.3”SOJ28

93 1 U14 Am29F010-90 DIP32(0.6”)(SOCKET)

AMD Am29F010-90PC

94 1 U15 74F04 SO14 SIGNETICS 74F04D


Notes:



95 1 U17 IMI SC464 SSOP28 INTL. MICROCKTS. INC. IMISC464AYB

96 1 U21 M1487 PQFP160 ALi M1487

97 1 U22 DS1685-5 DIP24(0.650”)

DALLAS SEMI. DS1685-5

98 2 U24, U82 74F08 SO14 SIGNETICS 74F08D

99 1 U25 Am486 Microprocessor, PGA

PGA169 AMD (AMP SOCKET1 916504-2)

100 11 U26, U28, U30, U31, U32, U36, U38, U40, U47, U49, U70

74ABT16244 SSOP48 SIGNETICS 74ABT16244ADL

101 1 U42 74ABT244 SOL20 SIGNETICS 74ABT244D

102 1 U43 M5113A PQFP100 ALi M5113A

103 1 U44 TFDS6000 SMT TEMIC TFDS6000D

104 2 U46, U45 RS232-5V SSOP28 LINEAR TECH LTC1349CG

105 1 U51 Am79C972 (PQR160)

PQR160 AMD Am79C972KC

106 1 U52 LXT970QC MQFP64 LEVEL ONE LXT970QC

107 1 U53 MC33269DT-3.3 DPAK MOTOROLA MC33269DT-3.3

108 1 U54 NM93C46N DIP8 NATIONAL NM93C46N

109 1 U55 MACH221 PQFP-100 AMD MACH221SP-7

110 9 U56, U61, U62, U63, U64, U65, U66, U67, U68

29F800-55 TSOP48 TSOP48 AMD AM29F800BT-55EC

111 2 U60, U80 PALCE22V10_PLCC (5ns)

PLCC28 AMD PALCE22V10H-5JC

112 1 U69 74ABT373 SOL20 SIGNETICS 74ABT373AD

113 1 U71 74ABT16245 SSOP48 SIGNETICS 74ABT16245BDL

114 4 U72, U73, U74, U75 Hex Display TH TI TIL311


Notes:





117 1 U79 M5042 PLCC44 ALi M5042

118 1 U81 NM93C66M8 SO8 NATIONAL NM93C66M8


120 1 U84 74ABT125 SO14 Signetics 74ABT125D

121 1 Y1 24 MHz_SMD ECLIPTEK ECSMA-24.00MTR

122 1 Y2 14.318 MHz_SMD ECLIPTEK ECSMAT-14.318MTR

123 2 Y4, Y6 32.768 KHz_SMD ECLIPTEK ECPSM29T-32.768KTR

124 1 Y5 25 MHz_SMD ECLIPTEK ECSMA-25.000MTR

127 1 XU14 DIP32(0.6”) SOCKET

SAMTEC ICA-632-SGG

128 1 XBT1 3.3 V LITHIUM COINCELL

TOSHIBA CR2032

129 1 U25-HS FANSINK FOR CPU THERMALLOY 2321B-TCM-42S-PF17

130 5 XXX JUMPERS (0.1”) FOR 0.025” SQ. POSTS


Notes:



SchematicsThe schematics that follow are the actual CAD schematics used to build the PCI CDP. These schematics are useful for understanding and modifying the PCI CDP. Because the development platform is based on a particular chipset and incorporates many different possible design options, actual Am486 microprocessor-based designs might be considerably different.


1

1

5

5

A A

B B

C C

D D

E E

Table of Contents

Page 1: COVER.SCHPage 2: CPU.SCH

Page 6: M1489.SCHPage 7: L2_CACHE.SCHPage 8: SIMM_SKTS.SCHPage 9: EIP_MEM1.SCH

Page 11: PCI_CONN.SCHPage 12: PCI_VIS.SCHPage 13: ENET1.SCHPage 14: ENET2.SCHPage 15: IDE.SCHPage 16: M1487.SCHPage 17: ROM_MISC.SCHPage 18: CLOCK.SCHPage 19: ISA_CONN.SCH

Page 4: CPU_VIS1.SCHPage 3: CPU_POWER.SCH

Page 20: SUPER_I/O.SCHPage 21: SERIAL_PARALLEL.SCHPage 22: ISA_MEM1.SCH

Page 24: RTC_TIP.SCHPage 23: ISA_MEM2.SCH

Page 10: EIP_MEM2.SCH

Page 25: KEYBOARD.SCHPage 26: CPU_PINOUT.SCH

Original designRev 1.0:

Rev 1.1:

Rev 1.2:

Minor modifications a

Added External 8042 SRemoved Support for MRemoved Keyboard InteChanged design name t

Rev 1.3: Added Extra Bypass CaSwapped Around Some SRenamed MCLK1 net to Added 0-ohm resistor Added Pin to HS1 for Fixed Error in 3.3V R

Rearranged Clock NetsChanged Some Componen(50ohm to 49.9ohm, 1%5% on SH19)

Rev 1.4:

Page 5: CPU_VIS2.SCH

Note: Unless otherwise stated th

Note: Unless otherwise stated th

ROM device

z clock nets

Am486 Microprocess

Note: Unless otherwise noted all

SH11:

SH16:

SH9:

SH15:

Changed SIP resistor Changed 330ohm SIP Resi

Added a 4K serial EEP’972 E/net device loadsCLKCNTL signal from M14

Broke CPU Logic AnalyzeAdded PAL to gnerate CBuffered BE[0..3], RDY

Swapped R107 and R109; Fixed wiring error on c

Added 5 more 0.1uF byp

SH4 & 5:

Fixed wiring error on cFixed wiring error in Removed unused inverterChanged net on NMI pin Changed R58 to be a pop

Rev 2.0:

SH14:

Added diagram to correcSH3:

SH13:

Added configuration infRemoved circuit to geneM1487 to assert NMI to

Added better explanatio

single Flash ROMions

ond when Am486

Am4PCIDev

MICROPROCESSORUSTOMER DEVELOPMENT PLATFORM

2.1

dvanced Micro Devices, Inc. (800) 222-9323

E. Ben White Blvd., TX 78741roprietary/All Rights Reserved

1 26ber 04, 1998

COVER.SCHNumber Rev

Sheet of

2

2

3

3

4

4

fter Design Review

tyle Keyboard Controller (SH24)1487 Internal KBC (SH15)rface From Clock Page (SH17)o Am486PCI C.D.P.

pacitors (SH5 & SH14 & SH15 & SH17)ignals Within Resistor Networks (SH6 & SH20)M_CLK1 (SH24)to make pin 10 & 11 pullup work (SH17)NetLister (SH3)egulator Circuit (SH12)

to Facilitate Routing (SH17)ts to Standard Values on SH 13 and 40pF to 39pF,

e capacitors are a 0805 package and 10% Tol.

e resistors are a 0805 package and 5% Tol.

Added jumpers to allow mulitple BIOS images in a single FlashRemoved 1 diode from VBAT generation circuitAdded new NMI generation circuit and spare ’F14 gatesAdded jumper for external RESET# pushbutton

Fixed wiring error on crystalRemoved MCLK1 net (16MHz) and rewired MCLK2 to drive all 33MHRemoved CLKCNTL signal from DOZE# pin of U17

Removed unneeded 0-ohm resistors from Super I/O chipFixed wiring error on crystalAdded ’ABT125 buffer to drive serial port LEDs

MACH device outputs changed for new ISA Flash support

Changed ISA Flash to 1MByte (512Kx16)

Removed unneeded logic from RTC interfaceAdded inverter to generate proper CS# for RTC chipFixed wiring error on crystalGrounded U22-pin 22Removed 1 unused OR gate for use on SH17

Switched mouse connector to verticle typeChanged ’F06 symbol to show o/c

SH17:

SH18:

SH20:

SH22:

SH23:

SH24:

SH25:

or Development System With PCI Expansion and On-Board Am79C972 100MB/s Ethernet Controller

logic operates off a 5V power supply

packs to 10-pin (SH2, SH3, SH11, SH15, SH16, SH17, SH19, SH20 & SH21)stor Pack to 8-pin (SH19)

ROM for user parameters and mux. circuit to daisy chain it off the 1K device. its configuration from 1K SEEPROM.87 used to select 1K or 4K SEEPROM.

r Headers into 2 pagesPU A0 and A1 and also generate a Logic Analyzer Qualify signal#, BRDY#, and ADS# through the new PAL

R109 is 49.9ohm, 1%rystal

ass capacitors for new chips (’F14, ’ABT125, 22V10, ’F08, ’C66)

rystalgeneration of low-active reset signal RSTDRV# (used on SH24)to 1487NMI for use in new circuitulated component

t Power Connector Footprint

ormation for PCI slotsrate PCI PERR# to causeAm486 microprocessor

n of EIP Flash memory operation

Rev 2.0 (continued):

Modified ROM jumpers to allow mulitple BIOS images in adevice and support 256K or 512K BIOS for non-PC applicat

Added XBUSCSJ signal to Mach device so it does not respfetches the reset vector at FFFF FFF0

SH17:

SH22:

Rev 2.1: Updated revision level and prototype warning on all sheets

SH14 &15 &20: Connected pins 1 and 2 on all LEDs for greaterpurchasing/manufacturing flexibility

86 Microprocessor Customerelopment Platform

Am486PCI C

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

1

1

5

5

A A

B B

C C

D D

E E

CLKMUL pin to GND for AMD DX2-66 AMD DX5-133; use 10K pullup for DX4-100

CPU.SCH

Am486 MICROPROCESSORPCI CUSTOMER DEVELOPMENT PLATFORM

OR, PULLUPS, AND JTAG INTERFACE

2.1

(C) Advanced Micro Devices, Inc. (800) 222-9323

5204 E. Ben White Blvd.Austin, TX 78741AMD Proprietary/All Rights Reserved

2 26riday, December 04, 1998

Document Number Rev

Sheet of

GA[2..31]

DP[0..3]

GA29GA30

GA26

GA31

GA24

GA27

GA25

GA28

MIOJDCJWRJ

ADSJ

GA[2..31]

PCDFERRJ

LOCKJ

HITMJ

BEJ[0..3]

WB-WT#

GD[0..31]

DP[0..3]

N

BLAST#

PULLHI1

HDLAPWT

BREQ

PLOCK#

VCC

C401000pF

R9110K

2

2

3

3

4

4

Enhanced Am486Microprocessor(SOCKET1-PGA169)

TieandAMD

JTAG Connector

2

9

1

10

Top View

JTAG Connector

Am486 MICROPROCESS

F

Title

Size

Date:

GD7

GD12

DP2

DP0

GD[0..31]

GD1

K2VCC

GD10

GD21

GD23GD24

GD29

GD2

GD25

GD16

GD30

DP1

GD3GD4

GD8

GD14

GD19

GD13

GD6

GD26

GD31

GD5

GD11

GD17

GD22

DP3

GD0

GD9

GD15

GD20

GD18

GD27GD28

GA10

GA16

GA21

GA24

GA29

GA13

GA3

GA11

GA25

GA30

GA22

GA4

GA8

GA14

GA19

GA28

GA26

GA31

GA5

GA17

GA9

GA15

GA23

GA20

GA7

GA18

GA27

GA2

GA12

GA6

BEJ3

BEJ1BEJ2

BEJ0

BEJ[0..3]

CLKMUL

TCK

TDITDO

TMS

PULLHI1

P24T5

SMIACKJ

SMIJPCHKJ

INTR

EADSJ

A20MJ

KENOJ

RDYOJBRDYOJ

IGNNEJ

BOFFJ

CPUVCC3

ZRSTDRV

AHOLD

BS8JBS16J

FLUSHJ

K2VCC

CPUCLK

MI

STPCLKJ

HITMJCPURST

PCD_CACH

INV

VCC

VCC

VCC

P35

HEADER2X5; SHRD

1 23 45 67 89 10

R11*10K

R1310K

R1480

RP1

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP8

4.7K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

U25

Am486-PGA

37501632625817346849155157566980

10965795

24

26

28

38

39

60

63

72

75

81

83

90

93

99

102

105

117

138

141

143

144

145

146

149

111104112110134169151133116988848

156

3 14

33

44

10

12

13

29

31

74

25438

42404123642

191

183654856791537335615266979684

10378

107108113

47

7 9 11

20

21

22

59

64

71

76

77

82

89

94

95

100

101

106

118

120

139

158

160

161

162

163

164

166

119115114136153154137124155125123126122140121127142157128159147165129148131167130168150132

70868792

13527304546152

55

CLKRESETINTRNMIHOLDBOFF#AHOLDEADS#KEN#FLUSH#IGNNE#BS16#BS8#A20M#RDY#BRDY#

DP0DP1DP2DP3

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

CV

CC

INC

(DX

4V

CC

5)

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

CV

CC

VC

C

M/IO#D/C#W/R#

LOCK#PLOCK#

ADS#BLAST#

BREQHLDAPWTPCD

FERR#

VO

LD

ET

(DX

2N

C)

TC

KT

DI

TD

O

SR

ES

ET

INV

(DX

2IN

C)

HIT

M#(D

X2IN

C)

INC

CA

CH

E#(D

X2IN

C)

TM

S

ST

PC

LK

#

D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

INC

(DX

2N

C)

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2

BE3#BE2#BE1#BE0#

PCHK#SMI#

WB/WT#(DX2INC)UP#

SMIACT#CLKMUL(DX2INC)

SKT1_NC

1

1

5

5

A A

B B

C C

D D

E E

CPU_POWER.SCH


15.0K)

1-2: 5V CPU2-3: OTHERS

J3

16

Power C

2345

= Connect

PLY, CPU BYPASS CAPACITORS

2.1



3 26ber 04, 1998

Number Rev

Sheet of

DP1DP2DP3DP0

DP[0..3]

3

RDYOJ

BS8J

BRDYOJ

MIOJ

K2VCC

PWG

C3

BOFFJ

FLUSHJBS16J

DP[0..3]

IGNNEJ

CPUVCC3

VCC

-12

C111uF

R26

15.8K, 1%

1/8W

1%

J2

PWR-CN6

123456

C340.01uF

R310K

C5

0.1uF

J3

PWR-CN6

123456

C8

0.1uF

JP2

HEADER 3X1

123

TC747uF

R510

+ TC8100uF

+ TC147uF

JP3

HEADER 3X1

123

36

1uF

C130.01uF

7

1uF

C90.01uF

C3

0.1uF

C121uF

TC510uF

C100.01uF

+ TC1047uF

C1

0.0

C164

0.015uF

C163

0.015uF

C162

0.015uF

RP2

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

2

2

3

3

4

4

3-4: 3.3V1-2: 3.45V

Am486PCI C

5-6: 2.5VV(out)= 1.235(1+ R/

Overlap To Make An Oval

J2

onnector(s)

16 2345

or Polarizing Key

POWER CONNECTOR, CPU PULLUPS, CPU POWER SUP

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

BASE

CPUV3

COLLECTORU6VIN

K2VCC

U6FB

CPUV2

U6O/P

CPUV1

CPUVCC

CPUVCC3

CPUVC

VCC

V -5VVCC

+12V-5V

VCC

VCC

-12V

+12V

VCC

VCC

0.0

+

TC9

10uF

R2327.4K, 1%1/8W

1%

+ TC1910uF

+ TC2010uF

R30

100

+

TC1810uF

U6

LP2951

1234 5

678O/P

SENSDGND ERR

TAPFB

VIN

R2733

+

+ TC2110uF

R25

25.5K, 1%

1/8W

1%

C350.01uF

+ TC447uF

K

C390.1uF

R28330

C

0.

+TC610uF

C37

0.1uF

C

0.

R2915.0K, 1%1/8W1%

0.0

+ C4

0.1uF

C6

0.1uF

+

TC310uF

R410K

R6110K

JP4

HEADER 3X2

1 23 45 6

Q5TIP127

3

1

2E

B

C

MT2

MountingHole

1

MT3

MountingHole

1

MT4

MountingHole

1

MT1

MountingHole

1

MT8

MountingHole

1

MT7

MountingHole

1

MT6

MountingHole

1

MT5

MountingHole

1

MT10

MountingHole

1

MT9

MountingHole

1

C166

0.1uF

C167

0.1uF

C168

0.1uF

C169

0.1uF

65

15uF

THERMALLOY ML32

HS1

HEATSINK (TO-220)

1 1

1

1

5

5

A A

B B

C C

D D

E E

CPU_VIS1.SCH

HP Conn.

1 2

19 20

Top View Am486 MICROPROCESSORPCI CUSTOMER DEVELOPMENT PLATFORM

POD 7

T NEEDED BY HP DISASSEMBLER

NALYZER HEADERS FOR CPU SIGNALS

2.1




Document Number Rev

Sheet of

GDGD[0..31]

P47

HP CONN3M:2520-6003UB

2468101214161820

CLK2CLK1 D15D14 D13D12 D11D10 D9D8 D7D6 D5D4 D3D2 D1D0 GND

+5V

2

2

3

3

4

4

POD 3

POD 4

SIGNALS NO

Using Logic Analyzer Headers:

Clock the analyzer off the clock signal on P41 (POD1)

Qualify the clock using the LA_QUAL signal on P39 (POD2)This qualification signal is asserted (1) when ADS#, RDY# or BRDY# isasserted on the Am486 Microprocessor bus.Thus cycles where valid address or data information is not transferredcan be filtered out when neededSignals are arranged on the LA Headers to work with the HP Disassembler for the 16500 analyzer

BUFFERS AND LOGIC A

F

Title

Size

Date:

VGD30VGD28VGD26VGD24VGD22VGD20VGD18VGD16


GD25

GD18

GD3

GD23

GD26

GD29

GD9

GD6

GD24

GD21

GD1

GD31

GD7

GD13

GD11

GD4

GD12

GD5

GD27

GD22

GD15

GD10

GD20

GD14

GD2

GD30

GD0

GD8

GD19

GD17GD16

GD28



VGD[0..31]

VGD31VGD30VGD29VGD28VGD27VGD26VGD25VGD24VGD23VGD22VGD21VGD20VGD19VGD18VGD17VGD16

VGD15VGD14VGD13VGD12VGD11VGD10VGD9VGD8VGD7VGD6VGD5VGD4VGD3VGD2VGD1

[0..31]

VSRESETVHITMJ

VPCHKJVSMIJVWB-WT#VSMIACKJVFERRJVAHOLDVNMIVIGNNEJ

VPLOCK#

VGD0

VCACHE#VSTPCLKJ

VINV

FERRJ

WB-WT#SMIACKJ

SMIJPCHKJ

IGNNEJ

AHOLDNMI

STPCLKJ

HITMJCPURSTPCD_CACH

INVPLOCK#

VCC

VCC

VCC

3579

1113151719

1

P36


23 45 67 89 10

11 1213 1415 1617 1819 20

1 CLK2CLK1 D15D14 D13D12 D11D10 D9D8 D7D6 D5D4 D3D2 D1D0 GND

+5V

P38


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

U26

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC

1A11A21A31A42A12A22A32A43A13A23A33A44A14A24A34A4

GNDGNDGNDGND

1Y11Y21Y31Y42Y12Y22Y32Y43Y13Y23Y33Y44Y14Y24Y34Y4

GNDGNDGNDGND

U28

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

U47

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

1

1

5

5

A A

B B

C C

D D

E E

CPU_VIS2.SCH


POD 1

PLACE THEVENIN TERMINATORNEAR HP LOGIC ANALYZERCONNECTOR

POD 2

19

1

HP Conn.

20

Top View

2

TO AID LOGIC ANALYZER USE

2.1



5 26ber 04, 1998

Number Rev

Sheet of

VINTR

VBRDYOJ

VPCD

VHLDA

VBEJ1VBEJ3VDCJ

VHOLD

VBS8J

VADSJ

VEADSJ

VFLUSHJ

VBOFFJ

GA[2..31]

BEJ

BEJ[0..3]

BEBEJBEJ

VCPUCLK1

GA[2..31]

BEJ[0..3]

ADSJBRDYOJRDYOJ

C

P41


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

NN0-6003UB

2468101214161820

CLK2D15D13D11D9D7D5D3D1

GND

R157470

R156330

2

2

3

3

4

4

Am486PCI C

PLACE THEVENINTERMINATOR NEAR’ABT16244BUFFER

POD 5

POD 6

5nsecLACNTL.JED

BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS, AND PAL

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

VWRJVBRDYOJVRDYOJVADSJ

VLOCKJ

VBLAST#

VCPUCLK1

VWRJ

VPWT

VCPUCLK

VKENOJ

VZRSTDRV

VBS16J

VCPUCLK

VBEJ2

VRDYOJ

VBREQVA20MJ

VMIOJ

GA24

GA22

GA8

GA30

GA27

GA17

GA15

GA10

GA28

GA20

GA23

GA31

GA26

GA4

GA7

GA9

GA25

GA16

GA13

GA11

GA5

GA19

GA12

GA29

GA3

GA6

GA18

GA21

GA2

GA14

VBEJ0

VBRDYOJVADSJVRDYOJ

VGA7

VGA22

VGA4

VGA30

VGA13VGA13

VGA4

VGA24

VGA26

VGA11

VGA3VGA7

VGA15

VGA10

VGA23

VGA12

VGA31

VGA25VGA28

VGA5

VGA29

VGA18

VGA27

VGA10

VGA22

VGA19VGA21

VGA17

VGA15

VGA27

VGA9

VGA16

VGA23

VGA14

VGA21

VGA6

VGA25

VGA14

VGA16

VGA20

VGA11

VGA28

VGA2

VGA24

VGA6

VGA8

VGA18

VGA9

VGA20

VGA19

VGA26

VGA5

VGA30

VGA8

VGA12

VGA2

VGA31

VGA3

VGA[2..31]

VGA17

VGA29

VGA0VGA1

VGA1VGA0

0J123

VBEJ0VBEJ1VBEJ2VBEJ3

LA_QUAL

LA_QUAL

VWRJVBRDYOJVRDYOJVADSJ

BLAST#

BS8JPCD

BS16J

BREQ

DCJ

WRJ

EADSJ

A20MJ

ZRSTDRV

MIOJ

PWT

BOFFJ

INTR

CPUCLK3

LOCKJ

FLUSHJ

HDLA

KENOJ

VGA[2..31]

VCC

VCC

VCC

VCC

VCC

VCR95470

U31

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

R94330

U49

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

P39

HP CO3M:252

3579

1113151719

1

CLK1D14D12D10D8D6D4D2D0

+5V

P40


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

P42


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

U32

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

U80

PALCE22V10_PLCC (5ns)

2

345679

10111213

2726252423212019181716

CLK/I0

I1I2I3I4I5I6I7I8I9I10

I/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0I11

U30

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

1

1

5

5

A A

B B

C C

D D

E E

M1489.SCH

PARITY


FINALi M1489 INTERFACE

2.1




Document Number Rev

Sheet of

GA[2..31]

PD1

PD3

PD0

PD2

TAG[0..7]

PAD[0..31]

MDP0MDP1MDP2MDP3

GA[2..31]

R163 0R165 0

R167 0R169 0

2F

2

2

3

3

4

4

FOR IDE MASTER: DO

NOT POPULATE

F

Title

Size

Date:

PAD[0..31]

TAG[0..7]

GD[0..31]

MA[0..11]

GA2 PAD0GA3 PAD1GA4 PAD2GA5 PAD3GA6 PAD4GA7 PAD5GA8 PAD6GA9 PAD7GA10 PAD8GA11 PAD9GA12 PAD10GA13 PAD11GA14 PAD12GA15 PAD13GA16 PAD14GA17 PAD15GA18 PAD16GA19 PAD17GA20 PAD18GA21 PAD19GA22 PAD20GA23 PAD21GA24 PAD22GA25 PAD23GA26 PAD24GA31 PAD25

PAD26PAD27PAD28PAD29PAD30PAD31

TAG0TAG1TAG2TAG3TAG4TAG5TAG6TAG7

GD

0G

D1

GD

2G

D3

GD

4G

D5

GD

6G

D7

GD

8G

D9

GD

10

GD

11

GD

12

GD

13

GD

14

GD

15

GD

16

GD

17

GD

18

GD

19

GD

20

GD

21

GD

22

GD

23

GD

24

GD

25

GD

26

GD

27

GD

28

GD

29

GD

30

GD

31

MA

0M

A1

MA

2M

A3

MA

4M

A5

MA

6M

A7

MA

8M

A9

MA

10

MA

11

HD

D15

HD

D8

HD

D4

HD

D2

HDD[0..15]

HD

D13

HD

D6

HD

D10

HD

D14

HD

D11

HD

D7

HD

D1

HD

D12

HD

D9

HD

D0

HD

D5

HD

D3

HDRQ1HDACK1HDRQ0HDACK0

CASJ0CASJ1CASJ2CASJ3RASJ0RASJ1RASJ2RASJ3

MA[0..11]

WEJ

TAGWEJ

CWEJ0

COEJ0

FRAMEJC_BEJ3C_BEJ2C_BEJ1C_BEJ0TRDYJIRDYJSTOPJPARDEVSELJ

PERRJ

A3IIA3I

PD0PD1PD2PD3

ADSJMIOJDCJWRJRDYOJBRDYOJ

KENOJEADSJ

BEJ0BEJ1BEJ2BEJ3

PCD_CACHLOCKJ

BOFFJ

HITMJAHOLD

GD[0..31]

HDD[0..15]

HDIOWJHDIORJHDA0HDA1HDA2

HDIO16JHDCSJ0HDCSJ1HDCSJ2HDCSJ3

PCICLK

SMIACKJIBCSTJCMPSTJCMPGNTJ

RSTDRV

HDIORDY

CPUCLK1

CLEAROKJ

HDRQ1HDACK1HDRQ0

HDACK0

VCC

C380.1uF

+TC11

10uFU5

M1489

15715817317217117016716516316216416916616116015917417517617717817918018318418147464845

1861871881893940

18519019142414443

131127129192155152154153

5 6 7 8 9 10

12

11

13

14

15

16

17

18

20

19

21

23

24

25

26

27

29

28

30

31

32

33

35

36

37

38

58

57

56

55

54

51

50

49

62

61

60

59

66

65

64

63

71

70

69

68

1991974138206207123205204203202198195193196200194201151102150103149105148106146107145108143109142110115136116135117134118126124121125119133120132122

208

168

156

128

104

90

72

53

34

182

144

130

78

52

22

111

147

141

137

123

112

140

113

114

139

75

76

73

74

81

82

79

80

77

83

84

85

86

88

91

93

95

97

99

101

100

98

96

94

92

89

87

67

GA2GA3GA4GA5GA6GA7GA8GA9GA10GA11GA12GA13GA14GA15GA16GA17GA18GA19GA20GA21GA22GA23GA24GA25GA26GA31BEJ0BEJ1BEJ2BEJ3ADSJMIOJDCJWRJRDYOJBRDYJLOCKJPCDHITMJAHOLDBOFFJKENOJEADSJRSTDRVPCICLKCPUCLK1SMIACKJIBCSTJCMPSTJCMPGNTJCLEAROKJ

GD

0G

D1

GD

2G

D3

GD

4G

D5

GD

6G

D7

GD

8G

D9

GD

10

GD

11

GD

12

GD

13

GD

14

GD

15

GD

16

GD

17

GD

18

GD

19

GD

20

GD

21

GD

22

GD

23

GD

24

GD

25

GD

26

GD

27

GD

28

GD

29

GD

30

GD

31

MA

0M

A1

MA

2M

A3

MA

4M

A5

MA

6M

A7

MA

8M

A9

MA

10

MA

11

CA

SJ0

CA

SJ1

CA

SJ2

CA

SJ3

RA

SJ0

RA

SJ1

RA

SJ2

RA

SJ3

CA3CA2

TAGWEJPERRJ

TAG7TAG6TAG5TAG4TAG3TAG2TAG1TAG0

CCSJ3CCSJ2CCSJ1CCSJ0CWEJ1CWEJ0COEJ1COEJ0PAD31PAD30PAD29PAD28PAD27PAD26PAD25PAD24PAD23PAD22PAD21PAD20PAD19PAD18PAD17PAD16PAD15PAD14PAD13PAD12PAD11PAD10PAD9PAD8PAD7PAD6PAD5PAD4PAD3PAD2PAD1PAD0

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DV

CC

VC

CV

CC

VC

CV

CC

VC

CF

RA

ME

JC

/BE

J3C

/BE

J2C

/BE

J1C

/BE

J0T

RD

YJ

IRD

YJ

ST

OP

JP

AR

DE

VS

ELJ

HD

CS

J3H

DC

SJ2

HD

CS

J1H

DC

SJ0

HD

IO16J

HD

IOR

DY

HD

A2

HD

A1

HD

A0

HD

IOR

JH

DIO

WJ

HD

D15

HD

D14

HD

D13

HD

D12

HD

D11

HD

D10

HD

D9

HD

D8

HD

D7

HD

D6

HD

D5

HD

D4

HD

D3

HD

D2

HD

D1

HD

D0

WE

J

R851K

R162 *0R164 *0

R166 *0R168 *0

C1710.1uF

C170.1u

1

1

5

5

A A

B B

C C

D D

E E

L2_CACHE.SCH


TERMINATION AND WE* FANOUT

2.1



7 26ber 04, 1998

Number Rev

Sheet of

MA[0..11]

TAG[0..7]

COEJ0CWEJ0

GA[2..19]

GD28

GD25

A3I

GD[0..31]

GD29

GA[4..18]

GD26

A3II

GD30GD31

GD27

GD24

AMA[0..11]

MWEJ0MWEJ1

GD[0..31]

COEJ0CWEJ0

CSJ0

CSJ2CSJ3

GA[2..19]

TAG[0..7]

WRJ

BEJ3

BEJ2

BEJ1

BEJ0

MWEJ2

TAGW

A3I

A3II

GA[4..18]

CSJ1

VCC

3333

33

-15

16

1314151718192021

222924

32

30

GND

DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8

CE1#WE#OE#

VCC

CE2

2

2

3

3

4

4

Am486PCI C

L2 CACHE TAG AND DATA SRAMS AND BYTE CONTROL; DRAM SERIES

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

A

AMA0AMA2AMA4

TAG0

AMA6

TAG1TAG2TAG3TAG4

AMA1

TAG5

AMA3

TAG6

AMA5

TAG7

AMA7

AMA8AMA9AMA10AMA11

MA1

MA0

MA7MA5

MA9

MA3

MA10

MA6

MA2MA4

MA11

MA8

MA[0..11]

ZMWEJ1ZMWEJ0

U1PD

ZMWEJ2

GA16

GA13

GA13

GA11

GA8GA7

GA14

GA12

GA9

GA18

GA6GA5 GA5

GA8

GD9

GA12

GA9

GA11GD7

GA14

GA18

GA16

GA11

GA4

GA14

GA18

GA6

GA17

GD13

GD10

GA18GA17

GA11

GD0

GA10

GD8

GA15

GA14

GA12

GA5

GD12

GA17

GA16

GA11

GA8GA7

GD6GA10GA9

GA17

GD17

GD11GA6

GA7

GD5

GD19

GD16GA5

GA13

GD22GD14

GA15

GA6

GA16

GD1

GA10

GA4

GD15

GA15

GA12 GA12

GA16

GA8

GA7

GA4

GD23

GD18

GA18

GD21GD20

GA15

GA5

GA7

GD3

GA4

GA15

GA9

GA17

GA13 GA13

GA8

GA10GA10

GA4

GA14

GA9

GA6

GD4

GD2

MRASJ0MRASJ1MRASJ2MRASJ3

MCASJ2MCASJ3

MCASJ0MCASJ1

CSJ1

CSJ2

CSJ3

CSJ0

WEJ

MA[0..11]

RASJ1RASJ2RASJ3

CASJ0CASJ1CASJ2CASJ3

EJ

RASJ0

VCCVCCVCC

VCCVCC

VCC

VCC VCC

VCC

VCC

U24A

74F08

31

2

U24B

74F08

64

5

U24C

74F08

89

10

U24D

74F08

1112

13

U1

74F245

2 183 174 165 156 147 138 129 11

191

A1 B1A2 B2A3 B3A4 B4A5 B5A6 B6A7 B7A8 B8

GDIR

R1910K

R96470

R8R7

RN4

33-8B

1357

2468

RN1

33-8B

1357

2468

RN3

33-8B

1357

2468

RN9

33-8B

1357

2468

R124

U11

32Kx8-15

109876543

252421232

261

2027

22

28

14

1112131516171819

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14

CE#WE#

OE#

VCC

GND


U10

128Kx8-15

16

1314151718192021

222924

32

30

12111098765

272623254

283

3121

GND


CE1#WE#OE#

VCC

CE2

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16NC

U7

128Kx8

12111098765

272623254

283

3121


U8

128Kx8-15

16

1314151718192021

222924

32

30

12111098765

272623254

283

3121

GND


CE1#WE#OE#

VCC

CE2


U9

128Kx8-15

16

1314151718192021

222924

32

30

12111098765

272623254

283

3121

GND


CE1#WE#OE#

VCC

CE2


RN2

33-8B

1357

2468

1

1

5

5

A A

B B

C C

D D

E E

SIMM_SKTS.SCH


K

USINGLATE

DRAM 72-PIN SIMM SOCKETS

2.1




Document Number Rev

Sheet of

MCASJ[0

AMA[0..11]

MDP2

GD26GD27

GD21

GD8

GD16

GD25

GD17

GD0GD1

GD3

GD5

MDP3

GD6

GD11

GD15

GD2

GD22

GD10

GD28

MDP1

GD4

GD29

GD12

GD14

GD30

GD7

MDP0

GD20

GD31

GD13

GD19

GD9

GD24

GD18

GD23

MCASJ[

MDP[0..3]

GD[0..31]AMA[0..11]

MDP[0..3]

GD[0..31]

AMA[0..11]

MCASJ[0..3]

MCASJ[0..3]

AMA[0..11]

64626058565452502725232197536563615755535149262422208642

38353736

2

2

3

3

4

4

SIMM0 SIMM1 SIMM2

SINGLE BANK SINGLE BANK SINGLE BAN

SINGLE BANKDOUBLE BANK

SIMM SOCKET POPULATION CHART

SIMMS CAN BE SINGLE BANK OR DOUBLE BANK, 1Mbit, 4Mbit, or 16Mbit DRAM CHIPS. POPUSIMM SOCKETS AS SHOWN IN THIS CHART.

F

Title

Size

Date:

GD31GD30GD29GD28GD27GD26GD25GD24GD23GD22GD21GD20GD19GD18GD17GD16GD15GD14GD13GD12GD11GD10GD9GD8GD7GD6GD5GD4GD3GD2GD1GD0

MCASJ3MCASJ2 MDP3MCASJ1 MDP2MCASJ0 MDP1

MDP0

AMA10AMA11

GD[0..31]

..3]

MDP[0..3]

GD31GD30GD29GD28GD27GD26GD25GD24GD23GD22GD21GD20GD19GD18GD17GD16GD15GD14GD13GD12GD11GD10GD9GD8GD7GD6GD5GD4GD3GD2GD1GD0

MCASJ3MCASJ2 MDP3MCASJ1 MDP2MCASJ0 MDP1

MDP0

MCASJ0

MCASJ2MCASJ3

MCASJ1

AMA11AMA10

AMA1

AMA10

AMA0

AMA2AMA3AMA4

AMA8AMA9

AMA5AMA6AMA7

AMA11

GD[0..31]

0..3]

MDP[0..3]

MCASJ[0..3]

AMA[0..11]

AMA2

AMA5

AMA9

AMA0

AMA4

AMA7

AMA3

AMA8

AMA6

AMA1

AMA3

AMA9

AMA5AMA4

AMA2AMA1

AMA8

AMA0

AMA6AMA7

MDP[0..3]

GD[0..31]

MDP[0..3]

GD[0..31]

MWEJ1

MRASJ2

MRASJ1

MWEJ0

MRASJ1

MRASJ0

MCASJ[0..3]

MRASJ0

AMA[0..11]

MWEJ2

MRASJ2

VCCVCC

VCC

SIMM1

SIMM72

64626058565452502725232197536563615755535149262422208642

38353736

66484611

696867

344544

414340

10

30

59

1 39

72

70

33

42

47

71291932312818171615141312

IO34IO33IO32IO31IO30IO29IO28IO27IO25IO24IO23IO22IO21IO20IO19IO18IO16IO15IO14IO13IO12IO11IO10IO9IO7IO6IO5IO4IO3IO2IO1IO0

IO35IO26IO17IO8

NC4NC3NC2NC1

PRD2PRD1PRD0

RAS2RAS1RAS0

CAS2CAS1CAS0

VC

CV

CC

VC

C

GN

DG

ND

GN

D

PRD3

RAS3

CAS3

WE

A12A11A10A9A8A7A6A5A4A3A2A1A0

SIMM2

SIMM72

66484611

696867

344544

414340

10

30

59

1 39

72

70

33

42

47

71291932312818171615141312


IO35IO26IO17IO8

NC4NC3NC2NC1

PRD2PRD1PRD0

RAS2RAS1RAS0

CAS2CAS1CAS0

VC

CV

CC

VC

C

GN

DG

ND

GN

D

PRD3

RAS3

CAS3

WE


SIMM0

SIMM72

64626058565452502725232197536563615755535149262422208642

38353736

66484611

696867

344544

414340

10

30

59

1 39

72

70

33

42

47

71291932312818171615141312


IO35IO26IO17IO8

NC4NC3NC2NC1

PRD2PRD1PRD0

RAS2RAS1RAS0

CAS2CAS1CAS0

VC

CV

CC

VC

C

GN

DG

ND

GN

D

PRD3

RAS3

CAS3

WE


1

1

5

5

A A

B B

C C

D D

E E

EIP_MEM1.SCH


Makes 2 banks of Controller. ProgBank Select when

ips

ips

(22)=0

(22)=1

lect

PLACE THENEAR 22V1

Supports burst R

Access as 32-bit

Set M1489 Memor

Supports single-

Compatible with

Limitations and O

Flash chip A0 pneeded to accesEIP Flash Arrayat 48MB or 3000

Uses 29F800T, 55

Accessable from

Uses fourth DRAM

IP FLASH MEMORY CONTROLLER

2.1



9 26ber 04, 1998

Number Rev

Sheet of

VCPUCLK1

VCC

R158330

R159470

2

2

3

3

4

4

Am486PCI C

EIPCNTL.JED REV. 0.9

1Mx32 Flash ROM appear as 1 bank of 2Mx32 DRAM (70ns, FPM) to M1489 Memoryram M1489 for 2Mx8 (11/10) DRAM chips. MA8 (CPU A22) used as Flash ROMRAS3# asserted by M1489 Memory Controller.

PAL

4 ea. 1Mx8Flash ROM Ch

4 ea. 1Mx8Flash ROM Ch

Bank1 Cntl.

Bank2 Cntl.

VA(2:21)

VA(22)

Am486MICROPROCESSOR

A(2:22)

’ABT244

A

A

CPU Address Bit A(22) Used As Flash Bank Se

VENIN TERMINATOR0 PAL

ead Cycles or single-beat Read Cycles

s wide always

y Controller to "Fast" for proper operation, even if installed DRAM is 60ns and can run at the "Fastest" setting

beat Write Cycles only; no back-to-back Write Cycles

CAS-before-RAS Refresh Cycles only

peration of the EIP Interface:

in tied to Am486 Microprocessor A2 pin, so multiply desired Flash chip address by 4h to find Am486 Microprocessor address s the desired memory cell (ex: Flash Chip AAAh accessed by Am486 Microprocessor at 2AA8h) start address moves, depending on how much DRAM is installed (ex: 48MByte DRAM puts EIP start address 000h for first bank of Flash ROMs and 3400000h start address for second bank of Flash ROMs

ns devices in "Byte" mode

Am486 Microprocessor only; not accessable from PCI Bus Masters

bank of M1489 Memory Controller

E

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

REFCIP

WRCIP

MRASJ3MCASJ3MCASJ2

VWRJ

MCASJ1MCASJ0

EIPCE1#EIPCE2#

EIPOE1#EIPOE2#

EIPWE2#

AMA8

EIPWE1#

VGA22RSTDRV

U60

PALCE22V10_PLCC (5ns)

2

345679

10111213

2726252423212019181716

CLK/I0

I1I2I3I4I5I6I7I8I9I10

I/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0I11

1

1

5

5

A A

B B

C C

D D

E E

EIP_MEM2.SCH


EIP FLASH MEMORY ARRAY

2.1




Document Number Rev

Sheet of

RSTDRV#

GD26GD27

GD30

GD24

GD31

GD28GD29

GD25

VGA2

RSTDRV#

GD25

GD29GD28

GD31

GD26

GD30

GD27

GD24

VGA2

VGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVG

VGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVGVG

VGA[2..31]

GD[0..31]

GD[0..31]

VGA[2..31]

RSTDRV#

EIPCE1#EIPOE1#EIPWE1#

EIPOE2#EIPWE2#

EIPCE2#

VCC

VCC

U64

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND

DQ0A0A1A2A3A4A5A6A7A8A9A10

DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C129

0.1uF

C128

0.1uF

U68

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C136

0.1uF

C137

0.1uF

2

2

3

3

4

4

F

Title

Size

Date:

GD0GD1GD2GD3GD4GD5GD6GD7

EIPOE1#EIPCE1#

RSTDRV#

EIPWE1#

GD14

GD9

GD15

GD8

GD13GD12GD11GD10

VGA2VGA2 VGA2

GD18GD19

GD22

GD16

GD23

GD20GD21

GD17

EIPOE1#EIPCE1#

RSTDRV#

EIPWE1#EIPOE1#EIPCE1#

RSTDRV#

EIPWE1#

GD0GD1GD2GD3GD4GD5GD6GD7

EIPWE2#EIPOE2#EIPCE2#

RSTDRV#

GD10GD11

GD14

GD8

GD15

GD12GD13

GD9

VGA2VGA2 VGA2

GD17

GD21GD20

GD23

GD16

GD22

GD19GD18


RSTDRV#


RSTDRV#

A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21

VGA3VGA4VGA5VGA6VGA7VGA8VGA9VGA10VGA11VGA12VGA13VGA14VGA15VGA16VGA17VGA18VGA19VGA20VGA21



A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21




VCC VCC VCC

VCC VCC VCC

U61

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

U63

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C122

0.1uF

C123

0.1uF

C125

0.1uF

C124

0.1uF

U62

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C127

0.1uF

C126

0.1uF

U67

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C131

0.1uF

C130

0.1uF

C133

0.1uF

C132

0.1uF

U66

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C134

0.1uF

C135

0.1uF

U65

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

1

1

5

5

A A

B B

C C

D D

E E

PCI_CONN.SCH


TORS; PCI IDSEL GENERATION

lot1 Slot2 Ethernet

NTA#

NTB#

NTC#

NTC#

INTD#

INTA#

INTB#

INTC#

INTA#

2.1



11 26ber 04, 1998

Number Rev

Sheet of

PAD1

PAD7PAD8

PAD10PAD12

PAD14

PAD17

PAD19PAD21

PAD23

PAD25PAD27

PAD29PAD31

SERRJ

PERRJPLOCKJ

DEVSELJ

IRDYJ

C_BEJ1

C_BEJ2

C_BEJ3

PREQJ0

SERRJ

STOPJ

PAR

C_BEJ0

FRAMEJTRDYJ

DEVSELJ

PLOCKJ

INT1JINT3J

PCICLK1

PAD5PAD3

-12V

C4215pF

RP10

4.7K-10P

23456789

10

O2O3O4O5O6O7O8O9

C

O10

2

2

3

3

4

4

Am486PCI C

IDSEL = AD19Device #3


PCI PULLUPS AND SLOT CONNEC

PCIBus INT S

INT0#

INT1#

INT2#

INT3#

I

I

I

I

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

PAD0PAD2

PAD4PAD6

PAD9

PAD11PAD13

PAD15

PAD16PAD18

PAD20PAD22

PAD24

PAD26PAD28

PAD30

C_BEJ0

PAR

STOPJ

TRDYJ

FRAMEJ

PGNTJ1

PCIID2

PCIRSTJ

INT1JINT3J

PAD19

PAD20PAD21

FRAMEJ

TRDYJ

STOPJ

INT0J

PAD6

PCIRSTJ

PAD0

PAD26

INT2J

PCIID1

PAD16

PGNTJ0

PAD30

PAD18

PAR

PAD4

PAD2

PAD22

PAD13

PAD20

PAD9

PAD28

PAD11

PAD24

PAD15

C_BEJ0

PREQJ1

PREQJ2

PREQJ0PGNTJ1

PGNTJ2

PGNTJ0

C_BEJ1C_BEJ2

C_BEJ3IRDYJ

INT0JINT2JINT1JINT3J

PCIID1

PCIID2PCIID3

PAD8

PAD31

PAD17C_BEJ2

IRDYJ

INT2J

PAD27

PAD14

PAD5PAD3

PAD1

PAD19

PAD10

INT0J

PCICLK2

PAD21

DEVSELJ

PAD29

PERRJ

C_BEJ1

PAD7

PREQJ1

C_BEJ3

SERRJ

PAD12

PAD23

PLOCKJ

PAD25

VCC

VCCVCCVCC

+12V-12V+12V

VCC

RN8

33-8B

1357

2468

SLT1

PCI Slot

1234567891011121314151617181920

2221

232425262728293031

626364656667686970717273747576777879

8180

82838485868788899091

61

9293949596979899

100101102103104105106107108109

110111112113114

323334353637383940414243444546474849

505152

115116117118119120

5354555657585960

TRST#+12VTMSTDI+5V

INTA#INTC#

+5VRSRVD

+5V(I/O)RSRVD

GNDGND

RSRVDRST#

+5V(I/O)GNT#GND

RSVRDAD30

AD28+3.3V

AD26GND

AD24IDSEL+3.3VAD22AD20GND

AD18

TCKGNDTDO+5V+5VINTB#INTD#PRSNT1#RSRVDPRSNT2#GNDGNDRSRVDGNDCLKGNDREQ#+5V(I/O)

AD29AD31

GNDAD27AD25+3.3VC/BE3#AD23GNDAD21AD19+3.3V

-12V

AD17C/BE2#GNDIRDY#+3.3VDEVSEL#GNDLOCK#PERR#+3.3VSERR#+3.3VC/BE1#AD14GNDAD12AD10GND

AD8AD7+3.3VAD5AD3

AD16+3.3V

FRAME#GND

TRDY#GND

STOP#+3.3V

SDONESBO#GNDPAR

AD15+3.3VAD13AD11GNDAD9

C/BE0#+3.3V

AD6

GNDAD1+5V(I/O)ACK64#+5V+5V

AD4GNDAD2AD0

+5V(I/O)REQ64#

+5V+5V

SLT2

PCI Slot

1234567891011121314151617181920

2221

232425262728293031

626364656667686970717273747576777879

8180

82838485868788899091

61

9293949596979899

100101102103104105106107108109

110111112113114

323334353637383940414243444546474849

505152

115116117118119120

5354555657585960

TRST#+12VTMSTDI+5V

INTA#INTC#

+5VRSRVD

+5V(I/O)RSRVD

GNDGND

RSRVDRST#

+5V(I/O)GNT#GND

RSVRDAD30

AD28+3.3V

AD26GND

AD24IDSEL+3.3VAD22AD20GND

AD18

TCKGNDTDO+5V+5VINTB#INTD#PRSNT1#RSRVDPRSNT2#GNDGNDRSRVDGNDCLKGNDREQ#+5V(I/O)

AD29AD31

GNDAD27AD25+3.3VC/BE3#AD23GNDAD21AD19+3.3V

-12V

AD17C/BE2#GNDIRDY#+3.3VDEVSEL#GNDLOCK#PERR#+3.3VSERR#+3.3VC/BE1#AD14GNDAD12AD10GND

AD8AD7+3.3VAD5AD3

AD16+3.3V

FRAME#GND

TRDY#GND

STOP#+3.3V

SDONESBO#GNDPAR

AD15+3.3VAD13AD11GNDAD9

C/BE0#+3.3V

AD6

GNDAD1+5V(I/O)ACK64#+5V+5V

AD4GNDAD2AD0

+5V(I/O)REQ64#

+5V+5V

1RP11

4.7K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP9

4.7K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

1

1

5

5

A A

B B

C C

D D

E E

HP Conn.

1 2

19 20

Top View

PCI_VIS.SCH

PLACE NEAR PCI0 CONN

PLACE NEAR PCI1 CONN

PLACE NEAR Am79C972 CHIP

PLACE TERMIN’ABT16


IC ANALYZER HEADERS FOR PCI BUS

2.1




Document Number Rev

Sheet of

VPAD31

VPAD11

VPAD3

VPAD29VPAD27VPAD25VPAD23

VPAD1

VPAD21

VPAD15

VPAD9

VPAD19VPAD17

VPAD13

VPAD7VPAD5

VFRAMEJVDEVSELJ

VC_BEJ1VC_BEJ3

VINT1J

VPLOCKJVPERRJ

VINT3J

VPCIRSTJ

VSTOPJ

PGNTJ1

PGNTJ0

PCICLK

PREQJ1

PREQJ0

PREQJ2PGNTJ2

2468101214161820

2468101214161820

2

2

3

3

4

4

ECTOR

ECTOR

E/NET

THEVENINATOR NEAR244 BUFFER

PLACE THEVENINTERMINATOR NEARHP LOGIC ANALYZERCONNECTOR

BUFFERS AND LOG

F

Title

Size

Date:

PAD18

PAD6

PAD23

PAD16

PAD5PAD4

PAD30

PAD3PAD2PAD1

PAD19

PAD31

PAD21

PAD0

PAD17

PAD9

PAD29

PAD10

PAD28

PAD8

PAD13

PAD24

PAD22

PAD11

PAD15

PAD25

PAD14

PAD26PAD27

PAD20

PAD12

PAD7

VPAD19

VPAD11

VPAD9

VPAD2

VPAD17

VPAD12

VPAD12

VPAD30VPAD28

VPAD25

VPAD26

VPAD6

VPAD0

VPAD24

VPAD8

VPAD0

VPAD22

VPAD7

VPAD10

VPAD5VPAD4

VPAD27

VPAD6

VPAD14

VPAD1

VPAD20

VPAD3

VPAD10

VPAD18

VPAD15

VPAD13

VPAD4

VPAD18

VPAD14

VPAD16

VPAD29VPAD30VPAD31

VPAD2

VPAD23

VPAD8

VPAD24

VPAD28

VPAD22VPAD21VPAD20

VPAD16

VPAD26

VFRAMEJVIRDYJVTRDYJVDEVSELJVPCICLKVINT0JVINT1JVINT2JVINT3JVPCIRSTJVSTOPJVPAR

VPLOCKJVPERRJVSERRJ

VC_BEJ1VC_BEJ0

VC_BEJ2VC_BEJ3

VIRDYJVTRDYJ

VC_BEJ0VC_BEJ2

VINT2J

VSERRJVPARVINT0J

VPAD[0..31]

VPCICLK

STOPJPCIRSTJ

TRDYJ

INT3J

C_BEJ3

INT1J

FRAMEJ

PAR

PAD[0..31]

C_BEJ1

IRDYJ

INT2J

INT0J

DEVSELJ

PERRJ

C_BEJ2

C_BEJ0

SERRJ

PLOCKJ

VCC

VCC

VCC

VCC

VCC

U42

74ABT244

2468

11131517

119

181614129753

1A11A21A31A42A12A22A32A4

1G2G

1Y11Y21Y31Y42Y12Y22Y32Y4

R97330

R98470

P46


3579

1113151719


+5V

P43


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

P44


23 45 67 89 10

11 1213 1415 1617 1819 20


+5V

P45


3579

1113151719


+5V

JP29

HEADER 3X1

123

JP30

HEADER 3X1

123

JP31

HEADER 3X1

123

U36

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

U38

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

U40

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

R160330

R161470

1

1

5

5

A A

B B

C C

D D

E E

ENET1.SCH


PLACE INPUT AND OUTPUT FILTER CAPS

AS CLOSE AS POSSIBLE TO REGULATOR

Spare "AND" Gates

nfig. For User NV Data

LLER, AND SERIAL EEPROMS

2.1



13 26ber 04, 1998

Number Rev

Sheet of

PADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPADPAD

EECS_1K

EECS_4K

EECS_4K

PAR

STOPJ

PGNTJ2

INT2J

FRAMEJ

PCIRSTJ

C_BEJ

PCICLK3

SERRJ

PREQJ2

C_BEJ

PERRJ

DEVSELJ

C_BEJ

PAD[0..31]

C_BEJ

PCIID3

IRDYJTRDYJ

VCC

VCC VCC

C85

1uF

U53

MC33269DT

3

1

VIN

GND_ADJ

6

U82C

74F08

9

108

U82D

74F08

12

1311

U81

NM93C66M8

12 6

8

5

3 4

7

CSSK ORG

VCC

GND

DI DO

NC

3

2

2

3

3

4

4

Am486PCI C


Set CSR116 bit 0 to "1" for proper PHY_RST operation

Defaults to "1"

For ’972 E/net Co

ETHERNET CONTROLLER, BYPASS CAPACITORS AND POWER SUPPLY FOR ETHERNET CONTRO

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

012345678910111213141516171819202122232425262728293031

EEDO

EN

ET

PG

EECS

ENETEBCLK

CLKCTR#

EECS

EESKEEDI

EECS_1K

21

3

0

PHY_RSTMDIOMDCERXD3ERXD2ERXD1ERXD0RX_DVRX_CLK_RXCLK

TX_EN_TXEN

ETXD0_TXDAT

TX_CLK_TXCLKTX_ER

ETXD3

ETXD1

COL_CLSNCRS_RXEN

CLKCTR

RX_ER_RXDAT

ETXD2

VCC3

VCC3

VCC3

VCC3

VCC

VCC3

VCC3VCC3

VCC3

VCC3

C88

0.1uF

+ C862.2uF

+ C8710uF

C90

0.1uF

C91

0.1uF

C92

0.1uF

C93

0.1uF

C94

0.1uF

C95

0.1uF

C89

0.1uF

C96

0.01uF

C97

0.01uF

C79

0.1uF

+ C782.2uF

C81

0.1uF

C82

0.1uF

C83

0.01uF

C80

0.1uF

R1051K

R1031K

R10410K

R1064.7K

+ C8410uF

U54

NM93C46N

12 6

8

5

3 4

7

CSSK ORG

VCC

GND

DI DO

NC

-3.3

4VOUT

U82B

74F08

4

5

U83A

74F14

1 2

U82A

74F08

1

2

U51

Am79C972 (PQR160)

5554525049474644414039373634333114121097642

159158156154153152151148

423015

160

11718202223252628

142143

144

146145

134

135

139

137

16

32

56

72

90

110

130

150

3 11

19

27

35

43

51

62

74

84

95

106

117

127

138

149

157

141

133

132

131

13

21

29

38

45

53

147

155

65

77

88

101

113

124

136

8 24

48

64

100

140

5

122123125120121126128

119118116115114112111109108107105104103

102999897

9694

7170696867666361

9392918987868583

7375767879808182

57

5958

60

129

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C_BE0#C_BE1#C_BE2#C_BE3#

IDSELFRAME#IRDY#TRDY#DEVSEL#STOP#PERR#SERR#PARINTA#PCIRST#

PCICLK

PCIREQ#PCIGNT#

TC

KT

MS

TD

IT

DO

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

VS

SB

PG

RW

UW

UM

I#P

ME

#

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

D_P

CI

VD

DB

VD

DB

VD

DB

VD

DB

VD

DB

VD

DB

VD

DB

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

D_P

CI

TBC_INTBC_EN

LED2#/SRDCLK/MIIRXFRTGEEEDO/LED3#/SRD/MIIRXFRTGD

EEDI/LED0#EESK/LED1#/SFBD

EECS

PHY_RSTMDIOMDC

RXD3RXD2RXD1RXD0

RX_DVRX_CLK/RXCLKRX_ER/RXDAT

TX_ERTX_CLK/TXCLK

TX_EN/TXEN

TXD0/TXDATTXD1TXD2TXD3

COL/CLSNCRS/RXEN

EBUA_EBA7EBUA_EBA6EBUA_EBA5EBUA_EBA4EBUA_EBA3EBUA_EBA2EBUA_EBA1EBUA_EBA0

EBD0EBD1EBD2EBD3EBD4EBD5EBD6EBD7

EBDA8EBDA9

EBDA10EBDA11EBDA12EBDA13EBDA14EBDA15

EROMCS#

AS_EBOE#EBWE#

EBCLK

EAR#

1

1

5

5

A A

B B

C C

D D

E E

ENET2.SCH


ECLI

123

45

67

8

119

1012

EDGE OF BOARD

PINS: 1-8NP MOUNTING HOLES: 9, 10SHIELD MOUNTING HOLES:11, 12

RJ45 PINOUT, COMPONENT SIDE VIEW

, ETHERNET CONNECTOR, AND LEDS

2.1




Document Number Rev

Sheet of

MFV0

R1

17

NE

T

ENET_ R1

T_RX+T_RX-T

T_TX+T_TX-

ENET_ R2

CAP

PHY_R

VCC

VCC

2

R1151.00K, 1%

R1141.00K, 1%

R1171.00K, 1%

R11175, 1%

1105, 1%

R11375, 1% 555153-1

J10

AMP RJ45A

12345678

1112

12345678

GND1GND2

R11275, 1%

C101

0.001uF, 2KV (MIN.)

2

+ C10710uF

2

2

3

3

4

4

1 2

34PTEK ECSMA-25.00MTR

ECLIPTEK ECSMA-25.00MTR

LINK SPEED TX DATA RX DATALUMEX SOT23 LED

1 2

3

Red Green Green

ETHERNET PHY CHIP

F

Title

Size

Date:

PHY _XI

ENEENERXC

TXCT

ENEENE

PHY_ XO

ENET _

ENET_RD-

ENET_RD+

RD

_C

T

ENET_TD+

ENET_TD-

ENET_TREF

ENET _RES

AVCC

AGND

RBIAS

AAVCC

AAGND

LEDS# LEDT# LEDR#

LEDS#

LEDT#LEDR#

RL

ED

S#

RL

ED

T#

RL

ED

R#

ST

TX_CLK_TXCLK

COL_CLSN

ETXD2ETXD1

ETXD3

TX_ER

ETXD0_TXDAT

TX_EN_TXEN

RX_ER_RXDATRX_CLK_RXCLK

RX_DV

ERXD0ERXD1ERXD2ERXD3

MDC

MDIOCRS_RXEN

VCC3

VCC

VCC

L5

FB

1

T1

PE68515

123

765

141516 10

1112

RD+RD-RD_CT

RX+RX-

RX_CT

TD_CTTD+TD- TX-

TX+TX_CT

R7

C98

33pF

C99

33pF

+ C11010uF

C1110.1uF

C1120.1uF

R107100, 1%

R10849.9, 1%

R10949.9, 1%

C1000.1uF

C1050.1uF

L4

FB

1

+ C10610uF

C1030.01uF

C1020.01uF

R11622K, 1% C104

0.01uF

L7

FB

1 2

L6

FB

1 2

+ C10810uF

C1090.01uF

U52

LXT970QC

12

11

9

19

24

37

53

22

26

31

43

52

10

56

5960616263

575864515554

5049484746

1442

45

1315345678

33143416

3839404142

323536

2827

1718

25

21

20

30

29

23

XI

XO

VCCD

VCCT

VCCA

VCCR

VCCIO

GNDT

GNDA

GNDR

GN

DD

GN

DIO

TE

ST

TX_ER

TXD0TXD1TXD2TXD3TXD4

TX_CLKTX_ENCOLRX_DVRX_ERRX_CLK

RXD0RXD1RXD2RXD3RXD4

CRSMDIOFDS/MDINTMDC

FDEMDDISTRSTEMF4MF3MF2MF1MF0CFG1CFG0PWRDWNRESET#

LEDS#LEDC#LEDL#LEDT#LEDR#

NC1NC2NC3

FIBINFIBIP

FIBOPFIBON

RBIAS

TPOP

TREF

TPIN

TPIP

TPON

Y5

25MHz_SMD

12 3

4

R149270

R150270

R151270

D10

LED (SOT23)

312

D11

LED (SOT23)

312

D12

LED (SOT23)

312

1

1

5

5

A A

B B

C C

D D

E E

IDE.SCH


Byass Ca

Distribute Tantalum capacitors ar

ND BOARD BYPASS CAPACITORS

2.1



15 26ber 04, 1998

Number Rev

Sheet of

..15]

1032021

6J

J

J

DY

HDD[0..15]

VCC

VCC

VCC

VCC

VCC

BC15

0.1uF

BC16

0.1uF

BC17

0.1uF

BC18

0.1uF

BC19

0.1uF

R21

1KR20

1KR90

4.7k

BC3

0.1uF

BC4

0.1uF

BC5

0.1uF

BC6

0.1uF

BC7

0.1uF

+ TC1210uF

+ TC210uF

+ TC2410uF

BC29

0.1uF

BC30

0.1uF

BC31

0.1uF

BC32

0.1uF

BC33

0.1uF

RP7

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

2

2

3

3

4

4

HD ACTIVE LED

HD ACTIVE LED

IDE HARD DISK 1

IDE HARD DISK 2

Am486PCI C

LUMEX LED (SOT23)

2

13 CATH

Top View

pacitors For The Board

Place one bypass capacitor near each chip Vcc pin, except:’ABT chips get one on each side near end Vcc pinsQFP chips get one on each side by central Vcc pin

ound the board

IDE INTERFACE A

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

HDD[0

HDD7 HDD8HDD6 HDD9HDD5 HDD10HDD4 HDD11HDD3 HDD12HDD2 HDD15HDD13 HDD14HDD1 HDD0



HDCSJHDCSJHDCSJHDCSJ

HDAHDAHDA

HDIO1

HDIOR

HDIOW

HDIOR

J5LE

DJ7

LE

D

J7LEDR

J5LEDR

HDIO16J

HDA2HDCSJ1

HDIO16J

HDA2HDCSJ3

HDIORJHDIOWJ

HDA1HDA0

HDCSJ0

SYSRSTJ

HDIORJHDIOWJ

HDA1HDA0

HDCSJ2

HDIORDY

HDIORDY

IRQ14

IRQ15

HDRQ0

HDACK0

HDRQ1

HDACK1

SYSRSTJ

VCC

VCC

VCC

VCC

BC21

0.1uF

BC22

0.1uF

BC23

0.1uF

BC24

0.1uF

BC25

0.1uF

BC26

0.1uF

BC27

0.1uF

BC28

0.1uF

BC20

0.1uF

J7

CNN-40C

13579111315171921232527293133353739

2468

10121416182022242628303234363840

J5

CNN-40C

13579111315171921232527293133353739

2468

10121416182022242628303234363840

R62

270

R63

270

BC2

0.1uF

BC8

0.1uF

BC9

0.1uF

BC10

0.1uF

BC11

0.1uF

BC12

0.1uF

BC13

0.1uF

BC1

0.1uF

BC14

0.1uF

+ TC2510uF

BC35

0.1uF

BC36

0.1uF

BC37

0.1uF

BC38

0.1uF

BC39

0.1uF

BC40

0.1uF

BC41

0.1uF

BC42

0.1uF

BC34

0.1uF

BC43

0.1uF

BC44

0.1uF

BC45

0.1uF

RP6

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP5

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

BC46

0.1uF

BC47

0.1uF

D13LED (SOT23)

312

D14LED (SOT23)

312

1

1

5

5

A A

B B

C C

D D

E E

M1487.SCH

ON: DISAOFF: ENA

OFF: 1X ON: 2X C


ECLIPTEKECPSM29T-32.

D

*=Do Not P

FINALi M1487 INTERFACE

2.1




Document Number Rev

Sheet of

SD[0..15]

SA[0..19]

LA[17..23]

7890123

RRDRV#

LA[17..23]

SD[0..15]

SA[0..19]

PCIRSTJ

ZRSTDRV

RSTDRV#

SYSRSTJ

VCC

VCC

U1

74F04

2

U1

74F04

4

U1

74F04

8

C5310pF

R7910M

R59

*1K

R58

1K

74F

6R147

22

Y4

32.768KH

34

R170

1K

C174

0.1uF

RP12

10K-10

1 OOOOOOOO

C

O1

2

2

3

3

4

4

BLE INTERNAL RTCBLE INTERNAL RTC

CPU-TO-PCI BUS FREQUENCYPU-TO-PCI BUS FREQUENCY

768KTR

1 2

34ECLIPTEK ECPSM29T-32.768KTR

(COMPONENT SIDE VIEW)

ISABLES INTERNAL KBC

opulate

F

Title

Size

Date:

GA[2..17]

SD0SD1SD2SD3SD4SD5SD6SD7SD8SD9SD10SD11SD12SD13SD14SD15

SA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12

OSCI SA13OSCO SA14

SA15SA16SA17SA18SA19

LA1LA1LA1LA2LA2LA2LA2

GA

2G

A3

GA

4G

A5

GA

6G

A7

GA

8G

A9

GA

10

GA

11

GA

12

GA

13

GA

14

GA

15

GA

16

GA

17

SYSRST

JRESET

DRQ1DRQ2DRQ3

DRQ6DRQ7

IOCHKJTCMASTERJZIOWJZIORJ

ZAENZSBHEJZREFSHJ

N0WSJIOCHRDYJZSMEMWJZSMEMRJZMWJZMRJMEM16JIO16J

ENRTC

CMPSTJ ZBALE

CMPSTJ

CLEAROKJXBUSCSJ

CMPGNTJ

DRQ5

DRQ0

IRQ15IRQ14IRQ12IRQ11IRQ10

IRQ9

IRQ8J

IRQ7IRQ6IRQ5IRQ4IRQ3IRQ1

DACK1DACK2DACK3

DACK6DACK7

CPURST

M1487NMISMIJ

PCICLK

OSCATCLKPWGPREQJ0PREQJ1PREQJ2PGNTJ0PGNTJ1PGNTJ2FRAMEJIRDYJINT0JINT1JINT2JINT3J

RTCAS

SPEAKTURBOEXTSMI

ENRTC

VBAT

CMPGNTJCMPSTJIBCSTJ

GA[2..17]

CLKCTR

STPCLKJ

DACK5

DACK0

CLEAROKJ

A20MJ

CPUCLK2

FERRJINTR

IGNNEJ

XBUSCSJ

ENRTC

IBCSTJ

5A

1

5B

3

5D

9

C5410pF

+

TC17

10uFU21

M1487

612063222316171819214681497013505354

515547485759565873781415656474757271

44

43

45

42

39

38

24

25

26

27

29

31

33

34

32

28

30

35

36

37

110

111

67

79

66

76

139

2 68

69

77

82

95

129

158

159

140

1151161171181411421431451538914614714814915015115215415515615747122123124125126127121119130131132133134135136137

160

138

128

98

62

41

10

144

120

80

60

40

1109

107

105

85

91

87

103

108

106

104

84

94

86

102

100

101

99

97

96

83

88

89

90

92

93

11

3

52

56

112113114

12

CPUCLKCPURSTSYSRSTA20MJINTRFERRJIGNNEJNMISMIJSTPCLKJPCICLKSYSRSTJOSCATCLKPWGPREQJ0PREQJ1PREQJ2

PGNTJ1PGNTJ2FARMEJIRDYJINT0JINT1JINT2JINT3JXBUSCSJRTCASOSC1OSC2SPEAKERTURBOEXTSMISPLEDCLKCTRENRTC

CLE

AR

OK

JC

MP

GN

TJ

CM

PS

TJ

IBC

ST

JH

A2

HA

3H

A4

HA

5H

A6

HA

7H

A8

HA

9H

A10

HA

11

HA

12

HA

13

HA

14

HA

15

HA

16

HA

17

IOC

S16J

ME

MC

S16J

ME

MR

JM

EM

WJ

SM

EM

RJ

SM

EM

WJ

IOC

HR

DY

OW

AIT

JB

ALE

IOR

JIO

WJ

MA

ST

ER

JT

CIO

CH

CK

JR

EF

RE

SH

JS

BH

EJ

AE

N

LA20LA19LA18LA17SA19SA18SA17SA16SA15SA14SA13SA12SA11SA10SA9SA8SA7SA6SA5SA4SA3SA2SA1SA0


GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DV

CC

VC

CV

CC

VC

CV

CC

VC

CD

RE

Q7

DR

EQ

6D

RE

Q5

DR

EQ

3D

RE

Q2

DR

EQ

1D

RE

Q0

DA

CK

J7D

AC

KJ6

DA

CK

J5D

AC

KJ3

DA

CK

J2D

AC

KJ1

DA

CK

J0IR

Q15

IRQ

14

IRQ

12

IRQ

11

IRQ

10

IRQ

9IR

Q7

IRQ

6IR

Q5

IRQ

4IR

Q3

IRQ

1IR

Q8J

PGNTJ0

KBCLKKBDATA

LA23LA22LA21

VBAT

U15C

04

5

z_SMD

12

C50

0.1uF

C173

0.1uF

P

2345678910

234567890

1

1

5

5

A A

B B

C C

D D

E E

ROM_MISC.SCH


12

Battery Socket

C&K SW

2

4

Reset, SM

TURBO SWITCH FUNCTION

(TO Am486 CPU)

FINALi only supports(128Kx8 worth of adddesktop PC applicati

rnal RESET# pushbutton

SMI, AND NMI PUSHBUTTONS

2.1



17 26ber 04, 1998

Number Rev

Sheet of

SA[0..19]

SA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SASASASASASASA

BT1P

Q2RR

Q2R

QQ

1RQ

I

EN

MEMWJ

WJ

LE

EMRJJ

BHEJSTDRV

SA[0..19]

XBUSCSJMRDJSMEMWJ

TURBO

PWG

NMI

VCC

VCC

VCC

R70*2.2K

R71

470

R4851K

R5010K

R4910K

BT1

3V Coincell (socket)KEYSTONE 103 or 106

12

D1

MMBD4148

1

Q2MMBT3904 (S

12

3

Q1MMBT3906 (SOT23

1

2 3

U77A

74F32

1

23

+ TC1610uF

R6410K

D5SOT23)

13

2

2

3

3

4

4

Am486PCI C

ITCH

I Switches

1

3

Press Switch To Assert SMI

ROM DataTransferred onFINALi LinkBus

3

21MMBD4148 (SOT23)MMBT3904 (SOT23)MMBT3906 (SOT23)

Press Switch To Assert NMI

Press Switch To Assert RESET

(FROM M1487)

SPARE ’F14 GATES

Jumpers to allow multiple 128K BIOSimages in the same Flash ROM chipand/or non-PC applications that can usemore than 128Kx8 BIOS ROM

1MBit Flash ROM chipress space) for legacy,ons

Jumper for exte

BIOS ROM, ISA SIGNAL SERIES TERMINATION; BATTERY AND SPEAKER CIRCUITS; RESET,

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

10111213141516

CSPEAK CRSPEAK

RRSPEAK RCSPEAK

GA2GA3GA4GA5GA6GA7GA8GA9

GA[2..9]

Q1R

RREXTSMI

SW2NET EXTNMI# EXTNM

RRPWG

ROM_A17ROM_A18

SA18

SA17

ZA

ZS

ZIO

ZREFSHJ

BA

SMIOR

MRDJZMWJ

ZSZR

ATCLK

GA[2..9]

VBAT

ZBALE

ZSMEMRJZIORJ

AEN

SMEMWJ

IOWJ

MWTJ

REFRESHJZMRJ

SBHEJRSTDRV

SPEAK

ATCLKO

EXTSMI

M1487NMI

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

C5522pF

C52

0.1uF

R47

0

R7610K

R7710K

R6810K

R81

33

R80

470

RN11

33-8B

1357

2468

RN10

33-8B

1357

2468

RN12

33-8BCTS 743 08-3 330 J TR

1357

2468

+ TC1310uF

LS1

SPEAKER

R5210K

R140100

SW3PBNO

1 3

+ TC2310uF

(SOT23)

3

D9MMBD4148 (SOT23)

13

D6MMBD4148 (SOT23)

13

Q4MMBT3904 (SOT23)

12

3

OT23)

)

R341K

R139100

SW2PBNO

1 3

+ TC2210uF

D8MMBD4148 (SOT23)

13

U83B

74F14

3 4

R65100

SW1PBNO

1 3

MMBD4148 (

RP1810K-10P

23456789

1

10

O2

O3

O4

O5

O6

O7

O8

O9

C

O10

U83C

74F14

5 6

U83D

74F14

9 8

U83F

74F14

13 12

U83E

74F14

11 10

JP34

HEADER 2X1

12

U14

Am29F010-90

2224

1

31

30

32

16

12111098765

272623254

282932

1314151718192021

CEOE

A18

WR

A17

VCC

GND

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7 R177

1KJP32

HEADER 3X1

123

R1781K

JP33

HEADER 3X1

123

1

1

5

5

A A

B B

C C

D D

E E

CLOCK.SCH

INSTALL PULLUPRESISTOR AND REMOVE0-OHM RESISTOR FOR25MHz CPU AND PCI BUS

ULTIPLE LOADS AND AREE END OF THE NET


1

4ECLIPTEK ECS

(COMPONE

CLOCK GENERATOR

2.1




Document Number Rev

Sheet of

OSC

OSC1

PCICLK1PCICLK2

CPUCLK2CPUCLK1

CPUCLK3

PCICLK3PCICLK

CPUCLK

6

pF

C57

15pF

C66

15pF

R1760

2

2

3

3

4

4

PLACE SERIES TERMINATORS ASCLOSE TO U17 AS POSSIBLE

PCICLK AND CPUCLK3 HAVE MTHEVENIN TERMINATED AT TH

2

3MAT-14.318MTRNT SIDE VIEW)

F

Title

Size

Date:

CLKAVDD2

CLKAVDD1

CLKPU1

CLKPU2

CLKAVSS

CLKLF1

B1OUT1

B1OUT2

B1OUT3

B1OUT4

B2OUT1

B2OUT2

B2OUT3

RROSC1RROSCROSCC

B2OUT4

CLKOSCOUT

CL

KO

SC

INMCLK2

VCC

VCC

VCCVCC

VCC

U15E

74F04

11 10

C480.1uF

C470.1uF C41

15pF

C43

15pF

C46

15pF

C33

15pF

C5

15

C6015pF

+TC1510uF

+TC14

10uF

R42

10

R924.7KR93

*4.7K

R31 10R33 0

R22 10R35 10

R57 0

R36 10R38 10

R54

10

R394.7K

R41

10

R99 10

U17

IMI SC464

1

2

18

111017

15

28

327

2425

14

12

13

16

26194

5689

20212223

7

OSCin

OSCout

ST#

S0S1S2

DOZE#

14.318

B1inB2in

MCLK1MCLK2

AVDD

AVSS

LF1

VDD2

VSS3VSS2VSS1

B1out1B1out2B1out3B1out4

B2out1B2out2B2out3B2out4

VDD1

C650.1uF

Y2

14.318MHz_SMD

12 3

4

C154

15pF

C155

10pF

C161

10pF

L3

FB

C1700.1uF

1

1

5

5

A A

B B

C C

D D

E E

ISA_CONN.SCH


BUS CONNECTORS AND PULLUPS

2.1



19 26ber 04, 1998

Number Rev

Sheet of



D15

D9

D14

D12

D8

D13

D8

D10

D15D14

D12

D9

D13

D10

D11

D11

SD[0..15]

SA2

SA0

SA3

SA1

SA13

SA10

SA6

SA9

SA14

SA11

SA16SA17

SA4

SA15

SA12

SA7SA8

SA19SA18

SA5

IOCHKJ

AENIOCHRDYJ

SBHEJ

MWTJMRDJ

IRQ9

DRQ2

SMEMWJSMEMRJ

IOWJIORJ

DRQ3

DRQ1REFRESHJ


BALE

RSTDRV

N0WSJ

DACK3

DACK1

DACK2TC

OSC1

ATCLKO

DACK7

DACK6

DACK5

DACK0

IO16JMEM16J

MASTERJ

DRQ7

DRQ6

DRQ5

DRQ0


-12V -+12V

2

2

3

3

4

4

Am486PCI C

ISA

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

LA[17..23]

S

S

SD0SD1 S

SD4

S

S

SD[0..15]

SSD2

S

SD3

S

SD5

SD7

SS

S

SD6

S

SD3

S

SD4

SD7

SD2

S

S

SD6

S

SD5

SD1SD0

SA13SA14

SA7SA8

SA16

SA4

SA6

SA3

SA15

SA11

SA5

SA9

SA2

SA10

SA18

SA0

SA19

SA1

SA12

SA17


SD8

SD12

SD4

SD1SD2

SD7

SD10SD11

SD0

SD15

SD9

SD13

SD5

SD3

SD14

SD6

SA14

SA10

SA5

SA16

SA12

SA18

SA15

SA4

SA19

SA13

SA9

SA17

SA2

SA6

SA8

SA11

SA0SA1

SA7

SA3

SA

[0..1

9]

IRQ3

IRQ6

IRQ4IRQ5

IOCHKJ

IOCHRDYJAEN

MRDJMWTJ

SBHEJ

BALE

OSC1

SMEMWJ

DRQ3

IRQ6

DACK3

DRQ2

IORJ

IRQ7

IRQ3

N0WSJ

TC

IRQ9

IOWJ

REFRESHJ

IRQ4

RSTDRV

DACK2

SMEMRJ

DRQ1

IRQ5

DACK1

MASTERJ

DACK7

DACK6

DACK5

DACK0

IO16JMEM16J

DRQ6

DRQ5

DRQ0


DRQ7

IRQ15IRQ14

IRQ9

IRQ7IRQ8J

IRQ12

IRQ10IRQ11

SD[0..15]

LA[17..23]

MASTERJREFRESHJ

N0WSJ

MEM16J

ATCLKO

SA[0..19]

IO16J

-5V VCC+12V -12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC5V

C6447pF

C5847pF

R75

4.7K

R781K

SL1

ISA AT Connector

AMP 645169-3

50515253545556575859606162636465666768697071727374757677787980

12345678910111213141516171819202122232425262728293031

323334353637383940414243444546474849

818283848586878889909192939495969798

GNDRESDRV+5VIRQ9-5VDREQ2-12V-0WS+12VGND-SMEMW-SMEMR-IOW-IOR-DACK3DREQ3-DACK1DREQ1-REFSHSYSCLKIRQ7IRQ6IRQ5IRQ4IRQ3-DACK2TCALE+5V14.3MHZGND

-IOCHCKD7D6D5D4D3D2D1D0

IOCHRDYAENA19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

-SBHELA23LA22LA21LA20LA19LA18LA17

-MEMR-MEMW

SD8SD9

SD10SD11SD12SD13SD14SD15

-MEMCS16-IOCS16IRQ10IRQ11IRQ12IRQ15IRQ14-DACK0DREQ0-DACK5DREQ5-DACK6DREQ6-DACK7DREQ7+5V-MASTERGND

SL2

ISA AT Connector

AMP 645169-3

50515253545556575859606162636465666768697071727374757677787980

12345678910111213141516171819202122232425262728293031

323334353637383940414243444546474849

818283848586878889909192939495969798

GNDRESDRV+5VIRQ9-5VDREQ2-12V-0WS+12VGND-SMEMW-SMEMR-IOW-IOR-DACK3DREQ3-DACK1DREQ1-REFSHSYSCLKIRQ7IRQ6IRQ5IRQ4IRQ3-DACK2TCALE+5V14.3MHZGND

-IOCHCKD7D6D5D4D3D2D1D0

IOCHRDYAENA19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

-SBHELA23LA22LA21LA20LA19LA18LA17

-MEMR-MEMW

SD8SD9

SD10SD11SD12SD13SD14SD15

-MEMCS16-IOCS16IRQ10IRQ11IRQ12IRQ15IRQ14-DACK0DREQ0-DACK5DREQ5-DACK6DREQ6-DACK7DREQ7+5V-MASTERGND

D7MMBD4148 (SOT23)

13

RP15

4.7K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP13

330-8P

2345678

1O2O3O4O5O6O7O8

C

RP1910K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP1610K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP1710K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP14

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP21

4.7K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

RP20

10K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

1

1

5

5

A A

B B

C C

D D

E E

SUPER_I/O.SCH

S


9

7

TFDS6000

1

6

3

8

2

COMPONENT SIDE VI

5

ACE, SERIAL PORT ACTIVITY LEDS

2.1




Document Number Rev

Sheet of

IR1L

TXD1_LED

RXD1_LED

TXD2_LED

RXD2_LED

RR

TX

D2

RR

RX

D2

RR

TX

D1

RR

RX

D1

DR1J

RPM

INDEXJ

FDIR

HDSEL

WRTPRTJ

WGATEJ

STEPJ

DR0J

MTR0J

DSKCHG

RDATAJ

TRK0J

WDATAJ

MTR1J

IRQ11

IRQ9

IRQ10

VCC

VCC

VCC

VCC

J6

CNN-34CFLOPY-CON

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 34

R10010

R0

R1521.5K

R1531.5K

R1541.5K

R1551.5K

RP41K-10P

2 3 4 5 6 7 8 9

1

10

O2

O3

O4

O5

O6

O7

O8

O9

C

O10

A125

3

B125

6

C125

8

D125

11

U44TFDS6000

1

5

910

8

GN

VCC

SD

LEDC

NC

GP1GP2

LEDA

RXDTXD

D15

LED (2mA, SOT23)

321

D16

LED (2mA, SOT23)

321

D17

LED (2mA, SOT23)

321

D18

LED (2mA, SOT23)

321

2

2

3

3

4

4

uperI/O IrDA Port

4

10

EW

1 2

34ECLIPTEK ECSMA-25.00MTR KINGBRIGHT SOT23 LED

12

3

(COMPONENT SIDE VIEW) (COMPONENT SIDE VIEW)

SUPER I/O CHIP, IrDA INTERFACE, FLOPPY DISK INTERF

F

Title

Size

Date:

PP[0..7]

SD[0..7]

PP3

PP0PP1

SD1

SD3

PP2

PWG

SD2

SD7

PP4

SD6

SD0

PP5

PP7

SD4

PP6

SD5

SA3

SA1

SA7SA8

SA0

SA6

SA4SA5

SA9

SA2

SA[0..10]

SA10

EDA

VCCIR1

IR1SD

IRRX

IRRXIRTX

IRTX

SIO_IRQINIIRQ9

IIRQ11

SIO_NCSJ

SIO

OS

C2

SIO

OS

C1

IIRQ10 TXD1

RXD1

TXD2

RXD2

PP[0..7]

SD[0..7]

IOCHRDYJ

IRQ7

RTS2J

DR1J

RPM

FDIR

IRQ4

MTR1J

TXD2

IRQ6

DR0J

DTR1JRTS1J

WGATEJHDSEL

MTR0J

STEPJ

IRQ3

DRQ2

IRQ5

TXD1

DTR2J

WDATAJ

CTS1J

IORJ

DSKCHG

RXD1

DACK2

TRK0J

RI2JDCD2J

PWG

DSR2J

RSTDRV

CTS2J

RDATAJ

IOWJ

WRTPRTJ

TC

RI1J

AEN

INDEXJ

DCD1JDSR1J

PINITJ

PSTROBJPAUTOFDJ

PPEPACKJ

PSLCTINJPERRORJ

PBUSY

PSLCT

DRQ1

SA[0..10]

RXD2

DRQ3DACK3

DACK1

VCC

C4439pF

C4539pF

C670.1uF

C690.1uF

+C686.8uF

R10110

R10247

U43

M5113A

27293031323334414243

464445

36

35

57

1819

61

62

60

59

75

73

74

76

77

4849505153545556

52

3837

4039

98

97

96

99

899193

94

28 23

24

2526

22

58

21

20

15

72

6 47

67

95

100

71

70

69

68

66

65

64

63

7882808584

8892908786

798183

12

345

78910111213141617

SA0SA1SA2SA3SA4SA5SA6SA7SA8SA9

AENIOR#IOW#

DACK2#

TC

MR

IDE_OE#/IRQ10NCSJ

BU

SY

AC

K#

PE

SLC

TE

RR

OR

#S

LC

TIN

#IN

IT#

AU

TO

FD

#S

TR

OB

#

SD0SD1SD2SD3SD4SD5SD6SD7

DRQ2

IRQ4IRQ3

IRQ6IRQ7

DRQ3

SA10

DACK3#

PDIR/IRQIN

TxD2/FDC_ENRTS2#/UR2_ADD0DTR2#/UR2_ADD1

IRQ5/ADRx#/PP_MODE1

DACK1# DRQ1/UR1_ADD1

IDE_CS0#/IRQ9/UR1_ADD0

IRTX/CFG_PORTIRRX/FDC_ADD

IDE_CS1#/IRQ11

PWRGD

OS

C2

OS

C1

VC

CV

CC

GN

DG

ND

GN

DG

ND

IOCHRDY

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

RxD1CTS1#DSR1#DCD1#RI1#/IDE_EN

RxD2CTS2#DSR2#DCD2#RI2#/IDE_ADD

TxD1/PP_ADD0RTS1#/PP_ADD1

DTR1#/PP_MODE0

DENSELMOT0

DRV1DRV0MOT1

DIR#STEP#

WDATA#WGATE#HDSEL#INDEX#TRK0#

WP#RDATA#

DSKCHG#

R1181K

R130

1K

127

Y1

24MHz_SMD

12 3

4

U8474ABT

2

1

U8474ABT

5

4

U8474ABT

9

10

U8474ABT

12

13

4

3

6

27

D

1

1

5

5

A A

B B

C C

D D

E E

SERIAL_PARALLEL.SCH


(Component Side View)

Connector

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Parallel

1

83

94

Serial Connector(Component Side View)

6

72

5

1

D PARALLEL PORT INTERFACES

2.1



21 26ber 04, 1998

Number Rev

Sheet of

PP2

PP6

PP[0..7]

PP5PP4

PP7

PP1PP0

PP3

PPAUTOFDJPPP0

PPP1PPERRORJ

PPINTJPPP2PPSLCTINJPPP3

PPP4

PPP5

PPP6

PPP7

PPACKJ

PPBUSY

PPPE

PPSLCT

PPSTROBJ

RTS1JTXD1

DTR1J

RXD1DSR1J

CTS1J

DCD1J

RI1J

TXD2RTS2J

DTR2JRI2J

DCD2JDSR2J

CTS2J

RXD2

PSTROBJ

PAUTOFDJ

PINITJ

PSLCTINJ

PERRORJ

PACKJ

PBUSY

PPE

PSLCT

PP[0..7]

J8

SERIAL PORTAMP 745410-1

594837261

J4

Parallel PortAMP 745967-7

13251224112310229

218

207

196

185

174

163

152

141

J9

SERIAL PORTAMP 745410-1

594837261

2

2

3

3

4

4

Am486PCI C

SERIAL AN

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

RXD1PDSR1P#

TXD1P

DCD1P#

RTS1P#

SIO1C2MSIO1VP

SIO1C1P

SIO1C1M

SIO1C2P

SIO1VM

SIO2C2P

RIN2P#

SIO2C1MSIO2VP

SIO2C2M

RTS2P#

SIO2VM

DCD2P#

TXD2P

DSR2P#

DTR2P#

RXD2P

SIO2C1P

CTS2P#

RIN1P#DTR1P#CTS1P#

RRTS2P#RTXD2P#RCTS2P#RDTR2P#RRIN2P#

RRXD2P#RDSR2P#RDCD2P#

RRTS1P#RTXD1P#RCTS1P#RDTR1P#RRIN1P#

RRXD1P#RDSR1P#RDCD1P#

VCC

VCC

VCC

VCC

VCC

C72

0.1uF

C70

0.1uF

C71

0.1uF

C74

0.1uF

C75

0.1uF

C76

0.1uF

C77

0.1uF

R61K

R14 22

R17 22

R15 22

R16 22

R18 22

RN5

22-8B

1357

2468

RN6

22-8B

1357

2468

RN7

22-8B

1357

2468

U46

RS232-5V LTC1349CG

2122202319242518

9810

116512

133

4

27

261 282 17

7

RO3RO2RO4DI2DI3RO1DI1RO5

RI3RI2RI4

DO3RI1

DO1RI5

ON/OFFC1+

C1-

C2+

C2-V+ V-VCC GND

DO2

C73

0.1uF

C19

180pF

C23

180pF

C15

180pF

C17

180pF

C30

180pF

C31

180pF

C22

180pF

C20

180pF

C29

180pF

RN13

22-8B

1357

2468

RN14

22-8B

1357

2468

U45

RS232-5V LTC1349CG

2122202319242518

9810

116512

133

4

27

261 282 17

7

RO3RO2RO4DI2DI3RO1DI1RO5

RI3RI2RI4

DO3RI1

DO1RI5

ON/OFFC1+

C1-

C2+

C2-V+ V-VCC GND

DO2

C25

180pF

C27

180pF

C32

180pF

C16

180pF

C18

180pF

C21

180pF

C24

180pF

C26

180pF

C145

180pF

C144

180pF

C143

180pF

C142

180pF

C141

180pF

C140

180pF

C139

180pF

C138

180pF

RN15

22-8B

1357

2468

RN16

22-8B

1357

2468

C151

180pF

C146

180pF

C147

180pF

C150

180pF

C152

180pF

C153

180pF

C148

180pF

C149

180pF

RP3

1K-10P

23456789

1

10

O2O3O4O5O6O7O8O9

C

O10

1

1

5

5

A A

B B

C C

D D

E E

ISA_MEM1.SCH


81

49 5032

1

82

29

100

MACH221SP

2

30

31

99

ISA BUS MEMORY AND HEX DISPLAYS

1

2.1




Document Number Rev

Sheet of

ATCLKO

ATCLKO

BALE

EN245#DIR245

P80CS#P680CS#

IORJRSTDRV

SA0

XBUSCSJ IOCHRDYJ

N0WSJMEM16J

LA[17..23] ISAA[1..23]

BALE

SA[0..16]

SD[0..15]

ROMCE#ROMOE#ROMWE#

VCC

-7Y

565859606162697071727375828485868788

131826546368764

5724273133485055577477818398100

1415394264658992

I/O30I/O31I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47

I0/CLK0I1/CLK1

I2I3

I4/CLK2I5/CLK3

I6I7

N/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/CN/C

VCCVCCVCCVCCVCCVCCVCCVCC

2

2

3

3

4

4

2

9

1

10

Top View

JTAG Connector

53

78

79

51

80

52

PORT 80

PORT 680

INTERFACE FOR

ISACNTL.JRev. 1.6

F

Title

Size

Date:

MACH_TCK

LOW

MACH_TMSMACH_TDIMACH_TDO

LA18LA17

LA23LA22LA21LA20LA19

SA15SA16

SA7SA6

SA9

SA2

SA11SA10

SA4SA3

SA12

SA8

SA14

SA5

SA13

SA1


ISAD0ISAD1ISAD2ISAD3ISAD4ISAD5ISAD6ISAD7ISAD8ISAD9ISAD10ISAD11ISAD12ISAD13ISAD14ISAD15

EN245#

DIR245

ISAD4 ISAD0ISAD5 ISAD1ISAD6 ISAD2ISAD7 ISAD3

P80CS#

P80HDP80LD

ISAD6ISAD3

P680CS#

P680LD

ISAD4ISAD1ISAD2

ISAD5ISAD0

ISAD7

P680HD

ISAA19

ISAA7

ISAA13

ISAA18

ISAA17ISAA11

ISAA6

ISAA4

ISAA4

ISAA16

ISAA2

ISAA8

ISAA22

ISAA18

ISAA5

ISAA16ISAA15ISAA14

ISAA9

ISAA3

ISAA19

ISAA12

ISAA1

ISAA1

ISAA13ISAA5

ISAA22

ISAA21

ISAA7

ISAA15ISAA23

ISAA20

ISAA10

ISAA6

ISAA10

ISAA20

ISAA21

ISAA17

ISAA23

ISAA9

ISAA3ISAA2

ISAA11

ISAA12

ISAA14

ISAA8

SA0

AENMRDJMWTJ

SMEMWJSMEMRJ

IOWJ

REFRESHJ

BALEATCLKO

IORJ

ISAD[0..15]

RSTDRV

XBUSCSJ

VCC

VCC

VCC

VCC VCC

VCC VCC

P48

HEADER2X5; SHRD

23 45 67 89 10

1

R134 1K

U70

74ABT16244

148

718

2524

3142

47464443414038373635333230292726

214

1015

23568911121314161719202223

28343945

1OE#2OE#

VCCVCC

3OE#4OE#

VCCVCC


GNDGNDGNDGND


GNDGNDGNDGND

U69

74ABT373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OE#E

Q0Q1Q2Q3Q4Q5Q6Q7

U71

74ABT16245

47 23568911121314161719202223

4443414038373635333230292726

46

3142

718

4825

124

28343945

214

1015

1A1 1B11B21B31B41B51B61B71B82B12B22B32B42B52B62B72B8

1A31A41A51A61A71A82A12A22A32A42A52A62A72A8

1A2

VCCVCC

VCCVCC

1G#2G#

1DIR2DIR

GNDGNDGNDGND

GNDGNDGNDGND

U72

Hex DisplayTI - TIL311

14

7

32

1312

1

584

10

6911

VCC

GND

DADBDCDD

LED

STRBBLNKLDCRDC

NCNCNC

U73


14

7

32

1312

1

584

10

6911

VCC

GND

DADBDCDD

LED

STRBBLNKLDCRDC

NCNCNC

R135330 R136

330

R137330

U75


14

7

32

1312

1

584

10

6911

VCC

GND

DADBDCDD

LED

STRBBLNKLDCRDC

NCNCNC

R138330

U74


14

7

32

1312

1

584

10

6911

VCC

GND

DADBDCDD

LED

STRBBLNKLDCRDC

NCNCNC

U55

MACH221SP

939495969799689

101112192021222325323435363738434445464749

3285378

12

1617293040415152666779809091

I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29

TDITCKTMSTDO

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

1

1

5

5

A A

B B

C C

D D

E E

ISA_MEM2.SCH


ISA BUS FLASH MEMORY

2.1



23 26ber 04, 1998

Number Rev

Sheet of

2

2

3

3

4

4

Am486PCI C

1MByte ISA Flash Memory

Configured as 512Kx16bit (29F800T device in "word" mode)

Access at even ISA Memory addresses between 15MB and 16MB-1

Use CSR 12h bit 3 to access 0f00000-0ffffffh as ISA Memory (instead of DRAM, if installed)

Flash chip A0 pin tied to ISA Address Bit 1; mulitply desired Flash chip address by 2h to find correct ISA address for access

(ex: Flash chip address 555h is accessed at ISA address AAAh)

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

RSTDRV#WORD

ISAA17

ISAA15

ISAA8

ISAA4

ISAA14

ISAA9

ISAA13

ISAA11

ISAA18

ISAA12

ISAA6ISAA7

ISAA2

ISAA19

ISAA3

ISAA5

ISAA1

ISAA16

ISAA10

ROMCE#ROMOE#ROMWE#

ISAD1ISAD0

ISAD7ISAD6

ISAD2ISAD3ISAD4ISAD5

ISAD12

ISAD15

ISAD9ISAD10

ISAD8

ISAD14

ISAD11

ISAD13

RSTDRV#

ISAA[1..21]

ISAD[0..15]

ROMCE#ROMOE#ROMWE#

VCC

VCC

R131

10K

U56

29F800-55 TSOP48

15

12

2628

44

11

37

4627

292524232221201918876

424038

543

35

21

481716

30323436

33

39414345

47

31

RY/BY#

RESET#

CE#OE#

DQ7

WE#

VCC

GNDGND


DQ6DQ5DQ4

A11A12A13

DQ3

A14A15A16A17A18

DQ8DQ9

DQ10DQ11

DQ2

DQ12DQ13DQ14

DQ15/A-1

BYTE#

DQ1

C115

0.1uF

C114

0.1uF

1

1

5

5

A A

B B

C C

D D

E E

RTC_TIP.SCH


TIP TE

12.5pF

Set CS Bit in CR 4B for12.5pF Xtal

1 2

34ECLIPTEK ECPSM29T-32.768KTR

(COMPONENT SIDE VIEW)

D TEST INTERFACE PORT CONNECTOR

2.1




Document Number Rev

Sheet of

RTCX1

RTCX2

RTCPWR#

SA[0..19

VBAT

IRQ8J

SD[0..15

VCC

VCC

1

20

1923

2

3

24

1216

22

WR#

BAT

IRQ#QW

X1

X2

VCC

GNDGND

AUX

U77D

74F32

12

1311

Y6

32.768KHz_SMD

123

4

R14110K

2

2

3

3

4

4

T.I.P.CONNECTOR

ETHERNET IRQ

PARALLEL PORT IRQ

SERIAL PORT1 IRQ

SERIAL PORT0 IRQST IRQ

(RTCSJ)

OPTIONAL Y2K COMPLIANT RTC

Set RAMCLR Bit in CR 4B to enable RAM_Clear Function

21

6059

RTC Address/DataTransferred onFINALi LinkBus

EDGE OF BOARD

PLASTIC SHROUDNOTCH ON TOP

T.I.P. CONNECTOR

Top View

OPTIONAL Y2K RTC AN

F

Title

Size

Date:

ENETIRQPARIRQ

SA14 SA15SA13

SA9SA8

SA10SA12

SA16SA18

SA5

SA1SA2 SA3SA4SA6

SA0

SA7

SA11

SA17SA19

SWIRQ SERIRQ1SERIRQ0

GA2GA3GA4GA5GA6GA7GA8GA9

RTCWR#

RTCRD#

RTCKS#

SD7SD6

SD0SD3

SD4SD2

SD1

SD5

RTCCS#

]

RSTDRVPWG

IOWJ

IOCHRDYJ

AEN IRQ12

IRQ15

IRQ11

IRQ10IRQ14

IORJ

GA[2..9]

PWG

ENRTC

ZIOWJ

RTCAS

ZIORJ

RSTDRV#

]

VCC

VCC

+C11310uF16VC-CASE

R1210

R1230

R1190

R1200

R1220

U22

DS1685-5

456789

1011

13141517

1821

AD0AD1AD2AD3AD4AD5AD6AD7

P

V

S

VB

CS#ALEWR#RD#

KS#RCLR#

U77C

74F32

9

108

U77B

74F32

4

56

R14210K

P31

COND60

12345678910

1112131415161718192021222324252627282930313233343536373839404143454749

4244464850

5153555759

5254565860

U15F

74F04

13 12

1

1

5

5

A A

B B

C C

D D

E E

KEYBOARD.SCH


KEYBOARD INHIBIT FUNCTION

41

3

5-PinDin

25

EDGE OF BOARD

CONNECTOR

4

1

5

KEYBOARD

3

2

(COMPONENT SIDE)

6

7

(PINS 6 AND7 GROUND THEMETAL SHELL)

YBOARD AND MOUSE INTERFACE

2.1



25 26ber 04, 1998

Number Rev

Sheet of

MVCC

ATCLK

BINHIBIT

IORJ

IOWJXBUSCSJ

KCLK1

SA2

KBVCC

RSTDRV#

KDATA1

XBUSCSJ

GA[2..9]

RSTDRV#

ATCLK

SA2

IOWJ

IORJ

VCC

VCC

VCC

C1600.1uF

R145

470

R146*2.2K

C1

0.1uF

F1

FUSE--0.5A

AMP 212044-1

J1

KYBD CONN

12345

67

F2

FUSE--0.5A

J11

MOUSE_CONAMP 750329-2

123456

78

123456

GNDGND

2

2

3

3

4

4

Am486PCI C

5

4

CONNECTOR

3

MOUSE

12

6

(COMPONENT SIDE)

EDGE OF BOARD

5

2

6-PinMini-Din

31

46

7

8

PC KE

(C) A

5204 AustinAMD P

Friday, Decem

Title

Size Document

Date:

MDATA1

M_CLK1MMCLK

MMDATA

GA6

K

GA2

GA[2..9]

KB

SS

#

IRQ1

GA7

KCLKKDATA

KBINHIBIT

GA3GA4GA5

GA8

KKCLK

IRQ12

KKDATA

GA9

MCLKMDATA

KKDATAMMDATA

KKCLKMMCLK

IRQ12IRQ1

VCC

VCC

VCC

VCC

VCC

R1714.7K

R1724.7K

L8FB

L9FB

C15947pF

C15847pF

R1741K

R1731K

C2847pF

R444.7KR45

4.7K

C1447pF

L2 FB

U79

M5042

2

3

5

6

43

97

810

12

15161718192021

28

3031323335363738

2425262739404142

11

44

22

29

1

4

14

13

2334

T0

NC2

RESET#

SS#

T1

RD#CS#

EAA0

NC3

D1D2D3D4D5D6D7

PROG

P10P11P12P13P14P15P16P17

P20P21P22P23P24P25P26P27

WR#

VC

CG

ND

VC

C

NC1

OSC

D0

SYNC

NC4NC5

L1 FB

R17510K

C1560.1uF

C1570.1uF

U78D

74F06

9 8

U78C

74F06

5 6

U78A

74F06

1 2

U78B

74F06

3 4

U78E

74F06

11 10

U78F

74F06

13 12

1

1

5

5

A A

B B

C C

D D

E E

CPU_PINOUT.SCH

(2)-D22

(3)-TCK

(4)-D23

(5)-DP3

(6)-D24

(7)-GND

(8)-D29

(9)-GND

(10)-INV

(11)-GND

(12)-HITM#

SOCKET1Am486 MICROPROCESSOR(PIN #)-PIN DESIGNAT(PIN SIDE VIEW)

(1)-D20

(13)-INC

(14)-TDI

(15)-IGNEE#

(16)-INTR

(17)-AHOLD

(18)-D19

(19)-D21

(20)-GND

(21)-GND

(22)-GND

(23)-D25

(24)-VCC

(25)-D31

(26)-VCC

(27)-SMI#

(28)-VCC

(29)-CACH

(30)-WB/W

(31)-TMS

(32)-NMI

(33)-TDO

(34)-EADS

A

(120)-GND

(121)-A17

(122)-A19

(123)-A21

(124)-A24

(125)-A22

(126)-A20

(127)-A16

(128)-A13

(129)-A9

(130)-A5

(119)-A31

(131)-A7

(132)-A2

(133)-BREQ

(134)-PLOCK#

(135)-PCHK#

(137)-A25

(138)-VCC

(139)-GND

(140)-A18

(141)-VCC

(142)-A15

(143)-VCC

(144)-VCC

(145)-VCC

(146)-VCC

(147)-A11

(136)-A28

(148)-A8

(149)-VCC

(150)-A3

(151)-BLAST#

(152)-CLKMUL

(154)-A26

(155)-A23

(156)-VOLDET

(157)-A14

(158)-GND

(159)-A12

(160)-GND

(161)-GND

(162)-GND

(163)-GND

(164)-GND

(153)-A27

(165)-A10

(166)-GND

(167)-A6

(168)-A4

(169)-ADS#


2.1




Document Number Rev

Sheet of

2

2

3

3

4

4

ION

E#

T#

#

(35)-D11

(36)-D18

(37)-CLK

(38)-VCC

(39)-VCC

(40)-D27

(41)-D26

(42)-D28

(43)-D30

(44)-SRESET

(45)-UP#

(46)-SMIACT#

(47)-INC

(48)-FERR#

(49)-FLUSH#

(50)-RESET

(51)-BS16#

(52)-D9

(58)-BOFF#

(55)-SKT1_NC

(53)-D13

(54)-D17

(57)-BS8#

(56)-A20M#

(60)-VCC

(59)-GND

(64)-GND

(61)-D10

(63)-VCC

(62)-HOLD

(70)-BE3#

(68)-KEN#

(67)-D15

(66)-D8

(69)-RDY#

(65)-DP1 (71)-GND

(72)-VCC

(76)-GND

(74)-STPCLK#

(75)-VCC

(73)-D12

(77)-GND

(78)-D3

(82)-GND

(80)-BRDY#

(81)-VCC

(79)-DP2

(83)-INC

(84)-D5

(88)-PCD

(86)-BE2#

(87)-BE1#

(85)-D16

(89)-GND

(90)-VCC

(94)-GND

(92)-BE0#

(93)-VCC

(91)-D14

(95)-GND

(96)-D6

(100)-GND

(98)-PWT

(99)-VCC

(97)-D7

(101)-GND

(102)-VCC

(106)-GND

(104)-D/C#

(105)-VCC

(103)-D4

(107)-D2

(108)-D1

(112)-W/R#

(110)-LOCK#

(111)-M/IO#

(109)-DP0

(113)-D0

(114)-A29

(118)-GND

(116)-HLD

(117)-VCC

(115)-A30

Am486 MICROPROCESSORPIN SIDE VIEW

SOCKET 1

COMPONENT SIDE VIEW

1

17

153

169 17

1

169

153

SOLDER SIDE VIEW

F

Title

Size

Date:

Index

Numerics

25-MHz system clock, 2-3533-MHz system clock, 2-36

A

A17, boot address, 2-6, 2-21, A-1A18, boot address, 2-6, 2-21, A-1Am486 microprocessor

block diagram, 2-10overview, 2-8

Am486 microprocessor PCI customerdevelopment platform

analyzer headers, 2-15block diagram, 2-4damage, avoiding, 1-2default settings, A-1documentation, xviifeatures overview, xiiiinstallation requirements, 1-3installing, 1-4jumper summary, 2-6, A-1layout diagram, 2-5overview diagram, xi, 2-3purpose, xirestrictions, 2-7troubleshooting, 1-8

Am486DX2-66 microprocessor, 2-35Am486DX4-100 microprocessor, 2-36Am486DX5-133 microprocessor, 2-36analyzer headers, 2-15

B

bill of materials, B-2BOM

See bill of materials.boot ROM

limitations, 2-7socket, 2-21

C

cable, diskette drive, 1-4cache memory

and EIP Flash memory, 2-25Level-2 cache, 2-20

chipsetdescription, 2-11limitations, 2-7

CLKCTL signal, 2-14CLKMUL signal, 2-35, 2-36CLKPU2 signal, 2-35, 2-36clock multiplier, 2-35, 2-36CMOS, problems, 1-8CMPSTJ signal, 2-35CodeKit software, iiiconfiguration, PCI, 2-11conventions, notational, xixcore logic chipset, 2-11CPU power, adjusting, 2-32CPUV1 signal, 2-6, A-1CPUV2 signal, 2-6, A-1

Am486® Microprocessor PCI Customer Development Platform Index-1

Ind

CPUV3 signal, 2-6, A-1CPUVCC3, 2-6, A-1

D

debuggingmonitor, 2-34support, 2-15

defaults for jumpers and switches, A-1development support, 2-15diskette

connecting drive, 1-4starting from, 1-6

DMA controller, 2-12documentation

conventions, xixdescription of, xviimanual contents, xviireference material, xviiisupport, iii

DRAMlimit without buffering, 2-7speed limit with EIP, 2-7using, 2-20

driveSee IDE hard drive or floppy disk drive.

DS1685 real-time clock, 2-27

E

EEPROM, serial, 2-13, 2-14ENRTC signal, 2-35errors, 1-8Ethernet controller, 2-13execute-in-place (EIP) Flash memory, 2-25EXTSMI signal, 2-34

F

fan heat sink, 1-5, 1-6Flash memory

in DRAM space, 2-25ISA, 2-23limitations, 2-7

floppydisk drive, 2-30starting from, 1-6

frequency multiplier, 2-35

G

GND connectors, 2-33ground wire, 2-33

H

hard drive, IDESee IDE hard drive.

headers, analyzer, 2-15heat sink, CPU, 1-5, 1-6hexadecimal display, 2-17

I

IBCSTJ signal, 2-36IDE hard drive

connection for, 2-31starting from, 1-7

IDSEL signal, 2-11in-circuit emulator compatibility, 2-17infrared support

See IrDA interface.

Am486® Microprocessor PCI Customer Development Platform User’s Manualex-2

installingcustomer development platform, 1-4requirements, 1-3troubleshooting, 1-8

interrupt controller, chipset function, 2-12interrupt signals

DMA channel limitations, 2-7PCI, 2-19TIP interface, 2-18

IrDA interfaceSuper I/O, 2-29

ISA bus, 2-28

J

J1 connector, 1-5J2 connector, 1-5J3 connector, 1-5J4 connector, 2-30J5 connector, 1-5, 2-31J6 connector, 1-4, 2-30J7 connector, 2-31J8 connector, 2-29J9 connector, 2-29JP2 jumper, 2-6, A-1JP29 test header, 2-17JP3 jumper, 2-6, A-1JP30 test header, 2-17JP31 test header, 2-17JP32 jumper, 2-6, 2-21, 2-22, A-1JP33 jumper, 2-6, 2-21, 2-22, A-1JP34 connector, 2-34JP4 jumper, 2-6, A-1JTAG port, 2-15jumpers

defaults, A-1summary, 2-6, A-1

K

KBINHIBIT signal, 2-36keyboard

connecting, 1-5connector, 2-31controller enable, 2-36error, 1-9

L

LEDs, problems with, 1-8Level-2 cache memory, 2-20limitations, 2-7LinkBus, 2-12literature support, iiilocations, part, 2-5logic analyzer headers, 2-15

M

M1487 southbridge chip, 2-12M1489 northbridge chip, 2-11MACH device, 2-15memory

boot ROM, 2-21cache, 2-20DRAM, 2-20EIP Flash memory, 2-25Flash memory, 2-23map, 2-24problems, 1-8serial EEPROM, 2-13, 2-14

monitor, debugging, 2-34mouse, 2-31


Ind

N

NMI signal, 2-34nonvolatile data, 2-14northbridge chip, 2-11

P

P36 analyzer header, 2-16P38 analyzer header, 2-16P39 analyzer header, 2-16P40 analyzer header, 2-16P41 analyzer header, 2-16P42 analyzer header, 2-16P43 analyzer header, 2-16P44 analyzer header, 2-16P45 analyzer header, 2-16P46 analyzer header, 2-16P47 analyzer header, 2-16parallel port, 2-30part locations, 2-5PCI bus

arbiter, 2-12configuration addressing, 2-11description, 2-19interrupt signals, 2-19limitations, 2-7

peripheralsneeded to use board, 1-3

PGNTJ0 signal, 2-17PGNTJ1 signal, 2-17PGNTJ2 signal, 2-17pin-grid-array (PGA) socket, 2-17port 680h display, 2-17port 80h display, 1-6, 1-7, 2-17ports

See serial ports or parallel port.POST (Power-On Self-Test codes), 1-6, 1-7power management

not implemented, 2-7, 2-14

power supplyconnecting, 1-5using, 2-33

PREQJ0 signal, 2-17PREQJ1 signal, 2-17PREQJ2 signal, 2-17programmable interval timer, 2-12PWG signal, 2-34

R

R11 resistor, 2-35R145 resistor, 2-36R146 resistor, 2-36R148 resistor, 2-36R170 resistor, 2-36R176 resistor, 2-36R58 resistor, 2-35R59 resistor, 2-35R70 resistor, 2-35R71 resistor, 2-35R93 resistor, 2-35real-time clock (RTC), 2-27RESET signal, 2-34resistor options, 2-35ROM

boot, 2-21EIP Flash memory, 2-25ISA Flash memory, 2-23

S

schematics, B-10serial EEPROM, 2-13, 2-14serial ports

connector, 2-29Super I/O, 2-29

SL1 ISA slot, 1-5, 2-28SL2 ISA slot, 1-5, 2-28SLT1 PCI slot, 1-5SLT2 PCI slot, 1-5


SMI signal, 2-34southbridge chip, 2-12super I/O

IrDA interface, 2-29overview, 2-28serial ports, 2-29

support, iiiSW1 switch, 2-34SW2 switch, 2-34SW3 switch, 2-34switch summary, 2-34system clock speed, 2-35, 2-36

T

technical support, iiitest interface port (TIP), 2-18test points, PCI, 2-17third-party support, iiitimer, chipset function, 2-12TIP board, 2-18TURBO signal, 2-35

U

U25 ZIF socket, 2-8U44 IrDA module, 2-29U54 serial EEPROM, 2-13U81 serial EEPROM, 2-14

V

VGAcable, connecting, 1-5card, connecting, 1-5monitor problems, 1-8

voltage limitations, 2-7

W

WWW support, iii

Y

year-2000 (Y2K), 2-27

Z

zero-insertion-force (ZIF) socket, 2-17


Ind


Am486 Microprocessor PCI Customer Development …Am486® Microprocessor PCI Customer Development...

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