ALTERA Cyclone IV Development & Education Board (DE2-115)...21 ~ 25 04 ~ 06 SCHEMATIC ALTERA Cyclone...
27
5 5 4 4 3 3 2 2 1 1 D D C C B B A A 03 DISPLAY 07 ~ 08 SDRAM , SRAM , FLASH , SD CARD WM8731 Cyclone IV EP4CE115 BANK1..BANK8 , POWER , CONFIG 10 POWER 19 01 TOP 01 ~ 03 15 ~ 16 09 ~ 14 PAGE 21 ~ 25 04 ~ 06 SCHEMATIC ALTERA Cyclone IV Development & Education Board (DE2-115) 17 ~ 18 CONTENT Cover Page, Placement,TOP 05 ETHERNET CLOCK, IrDA, PS2 , RS232 , BUTTON , SWITCH , HSMC, EEPROM 09 FPGA LCD , LED , 7SEGMENT 08 USB DEVICE 20 02 MEMORY 88E1111 07 AUDIO ADV7123, ADV7180 06 VIDEO 04 IN/OUT ISP1362 POWER 1.2V, 1.8V, 2.5V, 3.3V, 5V 26 ~ 27 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27 Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27 Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27 Friday, September 24, 2010
Transcript of ALTERA Cyclone IV Development & Education Board (DE2-115)...21 ~ 25 04 ~ 06 SCHEMATIC ALTERA Cyclone...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03 DISPLAY 07 ~ 08SDRAM , SRAM , FLASH , SD CARD
WM8731
Cyclone IV EP4CE115 BANK1..BANK8 , POWER , CONFIG10 POWER
19
01 TOP 01 ~ 03
15 ~ 1609 ~ 14
PAGE
21 ~ 25
04 ~ 06
SCHEMATIC
ALTERA Cyclone IV Development & Education Board (DE2-115)
17 ~ 18
CONTENTCover Page, Placement,TOP
05 ETHERNETCLOCK, IrDA, PS2 , RS232 , BUTTON , SWITCH , HSMC, EEPROM
09 FPGA
LCD , LED , 7SEGMENT
08 USB DEVICE 20
02 MEMORY
88E1111
07 AUDIOADV7123, ADV718006 VIDEO
04 IN/OUT
ISP1362
POWER 1.2V, 1.8V, 2.5V, 3.3V, 5V 26 ~ 27
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_DQ[31..0]DRAM_ADDR[12..0]DRAM_DQM[3..0]
SRAM_DQ[15..0]SRAM_ADDR[19..0]
FL_DQ[7..0]FL_ADDR[22..0]
SD_DAT[3..0]
LCD_DATA[7..0]
HEX0[6..0]HEX1[6..0]HEX2[6..0]HEX3[6..0]HEX4[6..0]HEX5[6..0]HEX6[6..0]HEX7[6..0]
LEDG[8..0]LEDR[17..0]
SW[17..0]
KEY[3..0]
GPIO[35..0]
HSMC_D[3..0]
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
VGA_B[7..0]VGA_G[7..0]VGA_R[7..0]
ENET1_RX_DATA[3..0]
ENET0_TX_DATA[3..0]
ENET0_RX_DATA[3..0]DRAM_DQ[31..0]
SRAM_DQ[15..0]
FL_DQ[7..0]
SD_DAT[3..0]
LCD_DATA[7..0]
GPIO[35..0]
SW[17..0]
KEY[3..0]
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
DRAM_ADDR[12..0]
SRAM_ADDR[19..0]
FL_ADDR[22..0]
LEDR[17..0]LEDG[8..0]
HEX0[6..0]HEX1[6..0]HEX2[6..0]HEX3[6..0]HEX4[6..0]HEX5[6..0]HEX6[6..0]HEX7[6..0]
DRAM_BA1DRAM_CAS_NDRAM_RAS_NDRAM_CKEDRAM_WE_NDRAM_CS_NDRAM_CLK
SRAM_UB_NSRAM_LB_NSRAM_WE_NSRAM_OE_NSRAM_CE_N
FL_WP_NFL_CE_NFL_OE_NFL_WE_N
FL_RST_N
SD_CLK SD_CMD
FL_RY
LCD_ONLCD_BLONLCD_ENLCD_RSLCD_RW
SMA_CLKOUT CLOCK_50CLOCK2_50CLOCK3_50
SMA_CLKIN
PS2_CLK2PS2_DAT2PS2_CLKPS2_DAT
UART_RXDUART_RTS
IRDA_RXD
EEP_I2C_SDAT
JTAG_TDOI2C_SDATI2C_SCLK
HSMC_CLKOUT0
HSMC_CLKIN_P1HSMC_CLKIN_N1HSMC_CLKIN_P2HSMC_CLKIN_N2HSMC_CLKIN0
UART_TXDUART_CTS
EEP_I2C_SCLK
FPGA_TDOJTAG_TMSJTAG_TCK
HSMC_CLKOUT_P1HSMC_CLKOUT_N1
DRAM_CAS_NDRAM_RAS_NDRAM_BA0DRAM_BA1DRAM_CKEDRAM_WE_NDRAM_CS_NDRAM_CLK
SRAM_CE_NSRAM_OE_NSRAM_WE_NSRAM_UB_NSRAM_LB_N
FL_RST_NFL_WE_NFL_CE_NFL_WP_NFL_OE_NFL_RY
SD_CLKSD_WP_NSD_CMD
LCD_ONLCD_ENLCD_RWLCD_RSLCD_BLON
CLOCK_50CLOCK2_50CLOCK3_50
SMA_CLKINSMA_CLKOUT
IRDA_RXD
UART_TXDUART_RXDUART_RTSUART_CTS
PS2_CLKPS2_DATPS2_CLK2PS2_DAT2
HSMC_CLKIN_P1HSMC_CLKIN_N1HSMC_CLKIN_P2HSMC_CLKIN_N2HSMC_CLKOUT_P1HSMC_CLKOUT_N1HSMC_CLKOUT_P2HSMC_CLKOUT_N2HSMC_CLKIN0HSMC_CLKOUT0
ENET0_RX_ERENET0_RX_COLENET0_RX_CRSENET0_RX_DVENET0_RX_CLK
ENET0_TX_CLKENET0_GTX_CLKENET0_TX_ENENET0_TX_ERENET0_INT_NENET0_RST_NENET0_MDCENET0_MDIO
ENET1_RX_ERENET1_RX_COLENET1_RX_CRSENET1_RX_DVENET1_RX_CLK
ENET1_TX_CLKENET1_GTX_CLKENET1_TX_ENENET1_TX_ERENET1_INT_NENET1_RST_NENET1_MDCENET1_MDIO
VGA_CLK
AUD_XCKAUD_BCLKAUD_ADCDATAUD_ADCLRCKAUD_DACDATAUD_DACLRCK
JTAG_TMSJTAG_TCKJTAG_TDIFPGA_TDO
NSTATUSCONF_DONENCONFIGNCE
DCLKDATA0NCSOASDO
EEP_I2C_SCLKEEP_I2C_SDAT
ENET0_TX_DATA[3..0] ENET0_RX_DATA[3..0]
ENET1_TX_DATA[3..0] ENET1_RX_DATA[3..0]
VGA_R[7..0]VGA_G[7..0]VGA_B[7..0]
ENET0_RX_DVENET0_RX_ERENET0_RX_CRSENET0_RX_COLENET0_RX_CLKENET0_TX_CLKENET0_INT_NENET0_MDIO
ENET0_GTX_CLKENET0_TX_ENENET0_TX_ERENET0_RST_NENET0_MDC
ENET1_MDCENET1_GTX_CLKENET1_TX_ENENET1_TX_ERENET1_RST_N
ENET1_RX_DVENET1_RX_ERENET1_RX_CRSENET1_RX_COLENET1_RX_CLKENET1_TX_CLKENET1_INT_NENET1_MDIO
VGA_SYNC_NVGA_CLKVGA_VSVGA_HS
AUD_ADCDATAUD_BCLKAUD_DACLRCKAUD_ADCLRCK
AUD_DACDATAUD_XCKI2C_SDATI2C_SCLK
DRAM_DQM[3..0]
DRAM_BA0
SD_WP_N
HSMC_D[3..0]
HSMC_CLKOUT_P2HSMC_CLKOUT_N2
VGA_BLANK_N
TD_RESET_N TD_DATA[7..0]
TD_VSTD_HSTD_CLK27
I2C_SCLKI2C_SDAT
ENET1_TX_DATA[3..0]
EX_IO[6..0]
EX_IO[6..0]
VGA_BLANK_NVGA_SYNC_NVGA_VSVGA_HS
OTG_DATA[15..0]
OTG_INT1OTG_INT0OTG_DREQ1OTG_DREQ0OTG_FSPEEDOTG_LSPEEDOTG_DACK_N1OTG_DACK_N0OTG_ADDR1OTG_ADDR0OTG_RD_NOTG_WR_NOTG_CS_NOTG_RST_N
OTG_DATA[15..0]
OTG_FSPEEDOTG_LSPEEDOTG_INT1OTG_INT0OTG_DREQ1OTG_DREQ0
OTG_ADDR1OTG_ADDR0OTG_CS_NOTG_WR_NOTG_RD_NOTG_DACK_N1OTG_DACK_N0OTG_RST_NUSB_12MHz
TD_RESET_NTD_CLK27TD_HSTD_VS
TD_DATA[7..0]I2C_SDATI2C_SCLK
ENET1_LINK100ENETCLK_25
ENET0_LINK100
ENET0_LINK100
ENET1_LINK100
ENETCLK_25
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
PAGE 2008 USB DEVICE
OTG_INT0
OTG_LSPEED
OTG_DATA[15..0]
OTG_INT1
OTG_FSPEED
OTG_DREQ0OTG_DREQ1
USB_12MHz
OTG_CS_NOTG_ADDR0OTG_ADDR1
OTG_RST_NOTG_DACK_N0OTG_DACK_N1OTG_RD_NOTG_WR_N
PAGE 17-1806 VIDEO
VGA_HSVGA_VSVGA_CLK
TD_HSTD_VS
TD_RESET_n
TD_CLK27
TD_DATA[7..0]
VGA_G[7..0]VGA_R[7..0]
VGA_B[7..0]
VGA_BLANK_N
VGA_SYNC_N
I2C_SDATI2C_SCLK
PAGE 15-1605 ETHERNET
ENET0_GTX_CLK
ENET1_TX_ER
ENET0_RX_CLK
ENET1_MDIO
ENET0_MDIO
ENET0_MDC
ENET1_TX_DATA[3..0]
ENET0_RX_DV
ENET0_RX_CRS
ENET1_RX_DV
ENET1_LINK100
ENET1_MDC
ENET0_TX_EN
ENET1_TX_ENENET1_GTX_CLK
ENET0_TX_DATA[3..0]
ENET0_TX_ER
ENET0_RX_DATA[3..0]
ENET1_TX_CLK
ENET1_RX_COL
ENETCLK_25
ENET1_RX_CLK
ENET0_LINK100
ENET0_INT_N
ENET1_INT_N
ENET1_RX_CRS
ENET1_RX_DATA[3..0]
ENET0_RX_ER
ENET1_RX_ER
ENET0_TX_CLK
ENET0_RX_COLENET0_RST_N
ENET1_RST_N
PAGE 9 - 1404 IN/OUT
HSMC_TDI
HSMC_CLKIN0
HSMC_CLKOUT0HSMC_SCLHSMC_SDAHSMC_TMS
HSMC_TCK
UART_TXD UART_RXD
JTAG_TDO
SW[17..0]
KEY[3..0]
UART_CTS
SMA_CLKOUT
UART_RTS
SMA_CLKIN
IRDA_RXD
HSMC_D[3..0]
EX_IO[6..0]
CLOCK_50
CLOCK3_50CLOCK2_50
HSMC_CLKIN_P1
HSMC_CLKIN_P2HSMC_CLKIN_N1
HSMC_CLKIN_N2
HSMC_CLKOUT_P1
HSMC_CLKOUT_P2HSMC_CLKOUT_N1
HSMC_CLKOUT_N2
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
GPIO[35..0]
PS2_DAT2PS2_CLK
PS2_CLK2
PS2_DAT
EEP_I2C_SCLK EEP_I2C_SDAT
PAGE 7-803 DISPLAY
LCD_BLONLCD_ON
LCD_ENLCD_RSLCD_RW
LEDG[8..0]LEDR[17..0]
LCD_DATA[7..0]
HEX1[6..0]HEX2[6..0]
HEX4[6..0]HEX3[6..0]
HEX5[6..0]
HEX7[6..0]HEX6[6..0]
HEX0[6..0]
PAGE 1907 AUDIO
AUD_BCLKAUD_DACLRCKAUD_ADCLRCK
AUD_DACDATAUD_XCK
AUD_ADCDAT
I2C_SDATI2C_SCLK
PAGE 26 -2711 POWER
PAGE 21-2510 EP4CE115
DRAM_BA0DRAM_BA1
DRAM_CLK
DRAM_CKE
LCD_ON
LCD_BLONLCD_RS
NCSODATA0
DRAM_DQ[31..0]
LCD_DATA[7..0]
SRAM_DQ[15..0]
NSTATUS
NCONFIG
LCD_RW
DRAM_DQM[3..0]
IRDA_RXD
SRAM_ADDR[19..0]
SD_CLKSD_DAT[3..0]
CONF_DONE
DRAM_ADDR[12..0]
LCD_EN
ASDO
NCE
DCLK
SD_CMD
SW[17..0]
LEDG[8..0]
HSMC_CLKOUT0
UART_RXDUART_RTS
UART_TXD
HSMC_D[3..0]
UART_CTS
SMA_CLKOUT
LEDR[17..0]
SMA_CLKIN
HSMC_CLKIN0
KEY[3..0]
AUD_DACDATAUD_ADCLRCK
AUD_ADCDATAUD_BCLK
TDO
AUD_DACLRCK
AUD_XCK
VGA_CLKVGA_HSVGA_VS
TDI
TMSTCK
EX_IO[6..0]
OTG_DATA[15..0]
OTG_LSPEED
TD_HS
OTG_INT0OTG_INT1
TD_VS
OTG_FSPEED
TD_CLK27
OTG_DREQ0OTG_DREQ1
TD_DATA[7..0]
VGA_G[7..0]VGA_R[7..0]
VGA_B[7..0]
HEX1[6..0]HEX2[6..0]
HEX4[6..0]HEX3[6..0]
HEX5[6..0]HEX6[6..0]HEX7[6..0]
HEX0[6..0]
CLOCK_50
CLOCK3_50CLOCK2_50
HSMC_CLKIN_P1
HSMC_CLKIN_P2HSMC_CLKIN_N1
HSMC_CLKIN_N2HSMC_CLKOUT_P1
HSMC_CLKOUT_P2HSMC_CLKOUT_N1
HSMC_CLKOUT_N2
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
GPIO[35..0]
VGA_BLANK_NVGA_SYNC_N
I2C_SDATI2C_SCLK
PS2_DAT2
PS2_CLK
PS2_CLK2PS2_DAT
ENET0_GTX_CLK
ENET1_TX_ER
ENET0_RX_CLK
ENET1_MDIO
ENET0_RX_DV
ENET0_MDCENET0_MDIO
ENET1_RX_DV
ENET0_RX_CRS
ENET1_LINK100
ENET1_TX_CLK
ENET1_RX_COL
ENET0_RX_DATA[3..0]
ENETCLK_25
ENET1_RX_CLK
ENET0_INT_N
ENET0_LINK100
ENET1_TX_DATA[3..0]
ENET1_MDC
ENET0_TX_EN
ENET1_TX_ENENET1_GTX_CLK
ENET0_TX_ER
ENET0_TX_DATA[3..0]
ENET1_INT_N
ENET1_RX_CRS
ENET1_RX_DATA[3..0]
ENET0_RX_ER
ENET1_RX_ER
ENET0_TX_CLK
ENET0_RX_COL
TD_RESET_N
OTG_CS_N
OTG_ADDR0OTG_ADDR1
SRAM_UB_NSRAM_WE_N
SRAM_CE_NSRAM_OE_N
SRAM_LB_N
FL_CE_N
FL_ADDR[22..0]
FL_OE_N
FL_DQ[7..0]
FL_WP_N
FL_RY
FL_WE_N
EEP_I2C_SCLKEEP_I2C_SDAT
SD_WP_N
OTG_RST_N
OTG_DACK_N0OTG_DACK_N1
DRAM_CAS_N
DRAM_WE_NDRAM_CS_N
DRAM_RAS_N
OTG_RD_NOTG_WR_N
ENET0_RST_N
ENET1_RST_N
FL_RST_N
PAGE 4-602 MEMORY
SD_CMDSD_CLK
DRAM_CLK
DRAM_CKE
DRAM_BA0DRAM_BA1
DRAM_DQM[3..0]
SD_DAT[3..0]
DRAM_DQ[31..0]
SRAM_DQ[15..0]SRAM_ADDR[19..0]
DRAM_ADDR[12..0]
SRAM_UB_N
SRAM_WE_N
SRAM_CE_N
SRAM_LB_N
SRAM_OE_N
FL_CE_N
FL_ADDR[22..0]
FL_OE_N
FL_DQ[7..0]FL_WP_N
FL_WE_N FL_RY
SD_WP_N
DRAM_CAS_N
DRAM_CS_NDRAM_WE_N
DRAM_RAS_N
FL_RST_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDRAM0 SDRAM1
DRAM_DQM2DRAM_DQM3
DRAM_CKE
DRAM_CAS_N
DRAM_RAS_N
DRAM_CS_N
DRAM_WE_N
DRAM_ADDR3
DRAM_ADDR0
DRAM_ADDR2DRAM_ADDR1
DRAM_ADDR10
DRAM_DQM0
DRAM_DQ5
DRAM_DQ0
DRAM_DQ7DRAM_DQ6
DRAM_DQ3DRAM_DQ2
DRAM_DQ4
DRAM_DQ1
DRAM_ADDR3
DRAM_ADDR0
DRAM_ADDR2DRAM_ADDR1
DRAM_ADDR10
DRAM_DQ21
DRAM_DQ16
DRAM_DQ23DRAM_DQ22
DRAM_DQ19DRAM_DQ18
DRAM_DQ20
DRAM_DQ17
DRAM_ADDR12
DRAM_ADDR5
DRAM_ADDR7DRAM_ADDR6
DRAM_ADDR8
DRAM_ADDR11
DRAM_ADDR4
DRAM_ADDR9DRAM_DQ24
DRAM_DQ31
DRAM_DQ27
DRAM_DQ25DRAM_DQ26
DRAM_DQ29DRAM_DQ30
DRAM_DQ28DRAM_ADDR12
DRAM_ADDR5
DRAM_ADDR7DRAM_ADDR6
DRAM_ADDR8
DRAM_ADDR11
DRAM_ADDR4
DRAM_ADDR9
DRAM_DQM1
DRAM_DQ8
DRAM_DQ15
DRAM_DQ11
DRAM_DQ9DRAM_DQ10
DRAM_DQ13DRAM_DQ14
DRAM_DQ12DRAM_CLKDRAM_CKE
DRAM_WE_nDRAM_CAS_nDRAM_RAS_nDRAM_CS_nDRAM_BA0DRAM_BA1
DRAM_DQ[31..0]
DRAM_ADDR[12..0]
DRAM_CLKDRAM_CKE
DRAM_BA0DRAM_BA1
DRAM_WE_NDRAM_CAS_NDRAM_RAS_NDRAM_CS_N
DRAM_DQM[3..0]
DR_VCC3P3 DR_VCC3P3 DR_VCC3P3
DR_VCC3P3
DR_VCC3P3DR_VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
C287
0.1u
C284
0.1u
C281
0.1u
C282
0.1u
U13
SDRAM 32Mx16
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
nCAS17
nRAS18
LDQM15
nWE16
nCS19
CKE37 CLK38
UDQM39
D02
D14
D25
D37
D48
D510
D611
D713
D842
D944
D1045
D1147
D1248
D1350
D1451
D1553
A1236
BA020
VD
D1
VD
D2
7
VS
S2
8
VS
S4
1
A1022
VD
DQ
3
VD
DQ
9
VD
DQ
43
VD
DQ
49
VS
SQ
6
VS
SQ
12
VS
SQ
46
VS
SQ
52
A1135
BA121
VS
S5
4V
DD
14
R223 4.7K
C85
10u
R224 4.7K
U15
SDRAM 32Mx16
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
nCAS17
nRAS18
LDQM15
nWE16
nCS19
CKE37 CLK38
UDQM39
D02
D14
D25
D37
D48
D510
D611
D713
D842
D944
D1045
D1147
D1248
D1350
D1451
D1553
A1236
BA020
VD
D1
VD
D2
7
VS
S2
8
VS
S4
1
A1022
VD
DQ
3
VD
DQ
9
VD
DQ
43
VD
DQ
49
VS
SQ
6
VS
SQ
12
VS
SQ
46
VS
SQ
52
A1135
BA121
VS
S5
4V
DD
14
R226 4.7K
R225 4.7K
C286
0.1u
C260
0.1u
C272
0.1u
C258
0.1u
C261
0.1u
C259
0.1u
C280
0.1u
C283
0.1u
R235 0R234 4.7K
C262
0.1u
C273
0.1u
C82
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SRAM_ADDR19SRAM_ADDR18SRAM_ADDR17SRAM_ADDR16SRAM_ADDR15SRAM_ADDR14SRAM_ADDR13SRAM_ADDR12SRAM_ADDR11SRAM_ADDR10
SRAM_ADDR7SRAM_ADDR6SRAM_ADDR5SRAM_ADDR4SRAM_ADDR3SRAM_ADDR2SRAM_ADDR1SRAM_ADDR0
SRAM_DQ0SRAM_DQ1SRAM_DQ2SRAM_DQ3SRAM_DQ4SRAM_DQ5SRAM_DQ6SRAM_DQ7SRAM_DQ8SRAM_DQ9SRAM_DQ10SRAM_DQ11SRAM_DQ12SRAM_DQ13SRAM_DQ14SRAM_DQ15
SRAM_ADDR8SRAM_ADDR9
SRAM_CE_N
SRAM_DQ[15..0]
SRAM_ADDR[19..0]
SRAM_CE_NSRAM_OE_NSRAM_WE_NSRAM_UB_NSRAM_LB_N
SR_VCC3P3VCC3P3
SR_VCC3P3
SR_VCC3P3
SR_VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
C289
0.1u
U17
SRAM 1Mx16
A05 A14 A23 A32 A41 A5
48 A647 A746 A845 A930 A1029 A1128 A1227 A1326 A1425 A1524 A1623 A1722 A1821 A1920
I/O08I/O19I/O210I/O311I/O414I/O515I/O616I/O717I/O832I/O933I/O1034I/O1135I/O1238I/O1339I/O1440I/O1541
CE_n7
WE_n18 OE_n44
UB_n43
LB_n42
VD
D1
2
VD
D3
6
GN
D1
3
GN
D3
7NC1
6
NC219
NC331
C290
0.1u
R78 0
R240 4.7K
C86
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FL_ADDR0
FL_CE_N
FL_RY
FL_ADDR2
FL_ADDR18
FL_ADDR21
FL_ADDR17FL_ADDR16FL_ADDR15FL_ADDR14FL_ADDR13FL_ADDR12FL_ADDR11FL_ADDR10
FL_ADDR20FL_ADDR19
FL_ADDR9FL_ADDR8FL_ADDR7FL_ADDR6FL_ADDR5FL_ADDR4FL_ADDR3
FL_ADDR22
FL_ADDR1
FL_DQ7FL_DQ6FL_DQ5FL_DQ4FL_DQ3FL_DQ2FL_DQ1FL_DQ0
SD_DAT0SD_DAT1SD_DAT2SD_DAT3
SD_DAT1
SD_DAT3SD_DAT2
SD_CMDSD_DAT0
SD_WP_N
FL_RY
FL_DQ[7..0]
FL_ADDR[22..0]
FL_CE_NFL_OE_N
FL_WE_NFL_RST_NFL_WP_N
SD_CMD
SD_CLK
SD_DAT[3..0]
SD_WP_N
F_VCC3P3
F_VCC3P3
F_VCC3P3
F_VCC3P3VCC3P3
F_VCC3P3
F_VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Flash & SD B
DE2-115 Main Board
A
6 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Flash & SD B
DE2-115 Main Board
A
6 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Flash & SD B
DE2-115 Main Board
A
6 27Friday, September 24, 2010
912345678
11
U26
SD Card Socket
DAT3CMDVSSVCCCLKVSSDAT0DAT1
DAT2
VSSWPVSSVSSVSSVSS C274
10u
C285
0.1u
C291
0.1u R238 4.7K
C288
0.1u
U18
FLASH 8Mx8
A153 A144 A135 A126 A117 A108 A99 A8
10
A1911
A2012
WE#13
RESET#14
A2115
WP#ACC16
RY/BY#17
A1818 A1719
A720 A621 A522 A423 A324 A225 A126
A1654
BYTE#53
VSS52
DQ15/A-151
DQ750
DQ1449
DQ648
DQ1347
DQ546
DQ1245
DQ444
VCC43
DQ1142
DQ341
DQ1040
DQ239
DQ938
DQ137
DQ836
DQ035
OE#34
VSS33CE#
32
A031
A222
A231
A2456
A2555
VIO29
RFU027
RFU128
RFU230
C87
10u
R236 10K
RN2410K
12345
678
R239 4.7K
R79 0
R237 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LC
D_
VC
C
LC
D_
BL
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LC
D_
CO
NT
LC
D_
DA
TA
6L
CD
_D
AT
A7
LC
D_
DA
TA
5
LC
D_
DA
TA
2L
CD
_D
AT
A1
LC
D_
DA
TA
4L
CD
_D
AT
A3
LC
D_
DA
TA
0
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LEDR9LEDR8
LEDG8
LEDR3LEDR2LEDR1LEDR0
LEDR4LEDR5
LEDR7LEDR6
LEDR13LEDR12
LEDR10LEDR11
LEDR16LEDR15LEDR14
LEDR17
LEDG2LEDG1
LEDG3
LEDG0
LEDG4
LEDG7LEDG6LEDG5
LCD_BLON
LCD_ON
LC
D_
EN
LC
D_
RS
LEDR[17..0]
LC
D_
RW
LCD_DATA[7..0]
LEDG[8..0]
VCC43
VCC43
VCC43
VCC5
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
7 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
7 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
7 27Friday, September 24, 2010
D68 DNI1
23
LEDR16 LEDR
LEDR8 LEDR
RN25 120
1234 5
678
D71 DNI1
23
LEDR3 LEDR
R205
47
LEDR17 LEDR
Q9DNI
D65 DNI1
23
LEDR5 LEDR
R204
1K
LEDG0 LEDG
D70 DNI1
23
R214
DNI
LEDR4 LEDR
D64 DNI1
23
Q6 8550
R227 DNI
RN27 120
1234 5
678
LEDR7 LEDR
LEDR0 LEDR
R213
680
Q7 DNI
LEDG3 LEDG
LEDR6 LEDR
D69 DNI1
23
D67 DNI1
23
LEDG2 LEDG
LEDR11 LEDR
RN31 120
1234 5
678
2 X 16 DIGIT LCD
U11
LCD-2x16
GN
D1
VC
C2
CO
NT
3R
S4
RW
5E
N6
D0
7D
18
D2
9D
31
0D
41
1D
51
2D
61
3D
71
4B
L1
5G
ND
16
R212 680
LEDG4 LEDG
LEDR10 LEDR
RN28 120
1234 5
678
LEDG1 LEDG
LEDR1 LEDR
LEDG5 LEDG
RN32 120
1234 5
678
LEDR12 LEDR
C263
1u
LEDR2 LEDR
LEDG6 LEDG
Q8 8050
LEDR13 LEDR
D66 DNI1
23
RN34 120
1234 5
678
LEDG7 LEDG
LEDR14 LEDR
LEDR9 LEDR
LEDR15 LEDR
RN36 120
1234 5
678
LEDG8 LEDG
Q58050
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
F4
G5
G7
G4F0
D2
A2
E5
C2B2
D4
E3
C4
A3
B4
D6
A6
F1E1
C6B6
C1
E6F6
A1
D1
B1
D3
E4
C3B3
B5
D5
F2
C5
A5
E2
C7
E0
D7
B7
G0
A7
G6
A0B0C0D0
E7
HEX14HEX13HEX12
HEX00HEX16
HEX15
HEX01
HEX35
HEX30
HEX34
HEX33HEX32HEX31
HEX36
HEX53
HEX55HEX54
HEX52
HEX41HEX40HEX56
HEX70HEX71HEX72HEX73
HEX74HEX75HEX76
HEX06HEX05HEX04HEX03
HEX21HEX22HEX23HEX24
HEX25HEX26
HEX46
HEX43
HEX45HEX44
HEX10
HEX61HEX62HEX63HEX64
HEX65HEX66HEX50
G1
G2
F3
F5
F7G3
HEX60
HEX51
A4
HEX42
HEX20
HEX11
HEX02
HEX0[6..0]
HEX1[6..0]
HEX2[6..0]
HEX3[6..0]
HEX4[6..0]
HEX5[6..0]
HEX6[6..0]
HEX7[6..0]
VCC2P5
VCC2P5
VCC2P5
VCC2P5
VCC2P5
VCC2P5
VCC2P5
VCC2P5
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
8 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
8 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
LCD & LED B
DE2-115 Main Board
B
8 27Friday, September 24, 2010
RN4 6801234 5
678
RN6 6801234 5
678
RN7 6801234 5
678
RN8 6801234 5
678
RN10 6801234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX4
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX3
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX7
7Segment Display
1
23
45
6
1098
7
RN12 6801234 5
678
RN9 6801234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX6
7Segment Display
1
23
45
6
1098
7
RN3 6801234 5
678
RN11 6801234 5
678
RN13 6801234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX2
7Segment Display
1
23
45
6
1098
7
RN2 6801234 5
678
RN14 6801234 5
678
RN15 6801234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX1
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX0
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX5
7Segment Display
1
23
45
6
1098
7
RN5 6801234 5
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IRM
SMA_CLKIN SMA_CLKOUT
CLOCK2_50CLOCK_50
CLOCK3_50
IRDA_RXD
VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC3P3
GPIO_VCCIOVCC3P3
VCC3P3 GPIO_VCCIO
VCC3P3
GPIO_VCCIO
VCC3P3GPIO_VCCIO
VCC3P3 GPIO_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA B
DE2-115 Main Board
B
9 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA B
DE2-115 Main Board
B
9 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA B
DE2-115 Main Board
B
9 27Friday, September 24, 2010
C88
0.1u
J15
PLL_CLKOUT
VDD
GND
U16
PI49FCT3803
4
1
3571012
6
1415
28
91
11
31
6
C276
0.1u
C89
0.1u
C90
47u
R82 47IRM
U21
IRM_V538_TR1
VCC2
GND3
OUT1
CHASSIS4
VCCA VCCB
DIR GND
A B
U14
SN74AVC1T45
3 46
25
1
VCCA VCCB
DIR GND
A B
U20
SN74AVC1T45
3 46
25
1J16
EXT CLOCK
R83
10K
R81
DNI
C278
0.1u
C84
0.1u
C279
0.1u
C83
0.1u
C275
0.1u
R80
DNI
C277
0.1u
Y4
50MHZ
VCC4
OUT3
GND2
EN1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART_RXD
UART_TXD
TXD
RXD
KBCLK
KBDAT
MSDAT
MSCLK
RTS
CTSUART_TXD
PS2_CLK2PS2_DAT2
UART_RXD
PS2_DATPS2_CLK
UART_RTS
UART_CTS
VCC5
VCC5 VCC5 VCC5VCC5
VCC3P3 VCC3P3VCC3P3VCC3P3
VCC3P3
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2 & RS232 B
DE2-115 Main Board
A
10 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2 & RS232 B
DE2-115 Main Board
A
10 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2 & RS232 B
DE2-115 Main Board
A
10 27Friday, September 24, 2010
D5
BAT54S
1 23
C26 1u
R24
2K
R25
2K
C25 1u
R18 330
C13
0.1u
C28 0.1u
D7
BAT54S
1 23
J6
RS232
594837261
11
10
R26
2K
35
TOP
8 6
2 1
J7
PS2
356
91
01
1
21
8
U1
ZT3232LEEY
R1IN13
R2IN8
T1IN11
T2IN10
C+1
C1-3
C2+4
C2-5
V+2
V-6
R1OUT12
R2OUT9
T1OUT14
T2OUT7
VCC16
GND15
D4
BAT54S
1 23
R27
2K
R19 330
C12 0.1u
R21 120
TXD1 LEDG
C15
0.1u
R20 120R22 120
RXD1 LEDR
C14
1u
R23 120
D6
BAT54S
1 23
C27
1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KEYIN3
GNDGND
HSMC_VCCIOGND GND
GND
HSMC_VCCIO
GND
GND
GNDGND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GNDGND
GND
GND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GND
GND
GND
GNDHSMC_VCCIO
GNDGND
HSMC_VCCIO
GNDGND
GND
GND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GND
GND
GND
GNDHSMC_VCCIO
GNDGND
KEYIN1
GND
HSMC_VCCIOGND
GND
GND
GNDGND
HSMC_VCCIO
GND
GND
HSMC_VCCIO
SW17
GND
GND
GNDGND
HSMC_VCCIO
GNDGNDGND
SW14
GND
GND
HSMC_VCCIOSW15
GNDHSMC_VCCIO
GND
HSMC_VCCIO
SW12SW13
KEYIN2
KEYIN0 KEY0
KEY2KEY3
KEY1
SW3SW2SW1SW0
SW7SW6SW5SW4
SW11SW10SW9SW8
SW16
KEY3
KEY2
KEY1
KEY0
KEYIN3
KEYIN1KEYIN0
KEYIN2
SW[17..0]
KEY[3..0]
VCC3P3
VCC3P3
HSMC_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH B
DE2-115 Main Board
B
11 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH B
DE2-115 Main Board
B
11 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH B
DE2-115 Main Board
B
11 27Friday, September 24, 2010
D78
BAT54S
1
23
SW3
SLIDE SW
123
4
5
SW13
SLIDE SW
123
4
5
U19
74HC245
A12 A23 A34 A45 A56 A67 A78 A89
OE19
DIR1
B118B217B316B415B514B613B712B811
VCC20
GND10
SW9
SLIDE SW
123
4
5
SW0
SLIDE SW
123
4
5
RN30 12012345
678
SW4
SLIDE SW
123
4
5
KEY0
TACT SW
4 3
21
SW10
SLIDE SW
123
4
5
C295
1u
D77
BAT54S
1
23
SW5
SLIDE SW
123
4
5
C294
1u
RN35 12012345
678
SW11
SLIDE SW
123
4
5
BUTTON1
DNI
4 3
21
KEY1
TACT SW
4 3
21
C293
1u
SW6
SLIDE SW
123
4
5
RN26 100K1234 5
678
BUTTON2
DNI
4 3
21
SW16
SLIDE SW
123
4
5
RN29 12012345
678
C292
1u
KEY2
TACT SW
4 3
21
R242 120
BUTTON3
DNI
4 3
21
SW17
SLIDE SW
123
4
5
KEY3
TACT SW
4 3
21
SW7
SLIDE SW
123
4
5
D75
BAT54S
1
23
SW14
SLIDE SW
123
4
5
RN16 10K12345
678
BUTTON0
DNI
4 3
21
SW1
SLIDE SW
123
4
5
SW15
SLIDE SW
123
4
5
SW8
SLIDE SW
123
4
5
R241 120
RN33 12012345
678
SW2
SLIDE SW
123
4
5
D76
BAT54S
1
23
SW12
SLIDE SW
123
4
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO
Close to FPGA
IO_D6
IO_D34
IO_D27
IO_D33
IO_D9
IO_D4
IO_D25
IO_D5
IO_D14
IO_D7
IO_D29 IO_D30 IO_D31
IO_D2IO_D0
IO_D13
IO_D10
IO_D18IO_D16
IO_D22
IO_D2
IO_D9
IO_D34 IO_D35IO_D33
IO_D21
IO_D0
IO_D12
IO_D24
IO_D28
IO_D32
IO_D14
IO_D19IO_D17
IO_D8
IO_D1
IO_D26
IO_D13
IO_D20IO_D19
IO_D15
IO_D11
IO_D23
IO_D35
IO_D31
IO_D27
IO_D25
IO_D18
IO_D4IO_D3
IO_D22
IO_D11 IO_D16
IO_D20
IO_D3
IO_D30
IO_D21
IO_D32
IO_D10
IO_D7IO_D6
IO_D12
IO_D23 IO_D24
IO_D29
IO_D5
IO_D1 IO_D8
IO_D15 IO_D17
IO_D28
IO_D26
GPIO18
GPIO20
IO_D18
IO_D20
GPIO0 GPIO22
GPIO24GPIO2
IO_D22
IO_D24
IO_D0
GPIO26
GPIO28
IO_D26
IO_D28
GPIO1 IO_D2
GPIO30
GPIO32
IO_D30
IO_D32GPIO17GPIO21GPIO23GPIO27GPIO25GPIO29GPIO31GPIO35
GPIO3GPIO5
IO_D17IO_D21IO_D23IO_D27IO_D25IO_D29IO_D31IO_D35
GPIO7GPIO8GPIO11GPIO9GPIO13
IO_D1IO_D3IO_D5IO_D7IO_D8IO_D11IO_D9IO_D13
IO_D15GPIO15
IO_D19GPIO19
GPIO4
GPIO6
IO_D4
IO_D6
IO_D34GPIO34
GPIO10
GPIO12
IO_D10
IO_D12
IO_D33GPIO33
GPIO14
GPIO16
IO_D14
IO_D16
GPIO[35..0]
VCC5
GPIO_VCCIO
VCC3P3
GPIO_VCCIOGPIO_VCCIO GPIO_VCCIOGPIO_VCCIO GPIO_VCCIO GPIO_VCCIOGPIO_VCCIO GPIO_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO B
DE2-115 Main Board
B
12 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO B
DE2-115 Main Board
B
12 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO B
DE2-115 Main Board
B
12 27Friday, September 24, 2010
R19847
RN23 47123456789
10111213141516
R20847
D50
BAT54S
1
23
D33
BAT54S
1
23
D49
BAT54S
1
23
D55
BAT54S
1
23
D61
BAT54S
1
23
R23147
D37
BAT54S
1
23
R20947
R21947
D34
BAT54S
1
23
D63
BAT54S
1
23
D35
BAT54S
1
23
D51
BAT54S
1
23
R228DNI
D52
BAT54S
1
23
R22047
R19947
R206DNI
D27
BAT54S
1
23
D30
BAT54S
1
23
D57
BAT54S
1
23
R217DNI
R20047
D54
BAT54S
1
23
D58
BAT54S
1
23
R21547
R18247
R196DNI
D73
BAT54S
1
23
D28
BAT54S
1
23
R23247
D36
BAT54S
1
23
D60
BAT54S
1
23
D62
BAT54S
1
23
D59
BAT54S
1
23
R21647
R23347
R22147
D74
BAT54S
1
23
R21047
D24
BAT54S
1
23
R195DNI
D29
BAT54S
1
23
R229DNI
R21147
D25
BAT54S
1
23
R22247
D38
BAT54S
1
23
JP5
BOX Header 2X20M
1 23 45 67 89 10
1113
1214161820222426
27
151719212325
28293133353739
303234363840
D56
BAT54S
1
23
D47
BAT54S
1
23
R218DNI
D48
BAT54S
1
23
R207DNI
R18347
D39
BAT54S
1
23
D72
BAT54S
1
23
RN21 47123456789
10111213141516
R19747
D32
BAT54S
1
23
D26
BAT54S
1
23
D31
BAT54S
1
23
D53
BAT54S
1
23
R23047
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Short pin1 and pin2: JTAG chain not including HSMC
Short pin2 and pin3: JTAG chain including HSMC
HSMC_RX_D_n8HSMC_RX_D_p8
HSMC_RX_D_N3HSMC_RX_D_P3
HSMC_TX_D_P0HSMC_TX_D_N0
HSMC_RX_D_N4HSMC_RX_D_P4
HSMC_TX_D_P1HSMC_TX_D_N1
HSMC_RX_D_N5HSMC_RX_D_P5
HSMC_TX_D_P2HSMC_TX_D_N2
HSMC_RX_D_N6HSMC_RX_D_P6
HSMC_TX_D_P3HSMC_TX_D_N3
HSMC_RX_D_N7HSMC_RX_D_P7
HSMC_TX_D_P4HSMC_TX_D_N4
HSMC_TX_D_P5HSMC_TX_D_N5
HSMC_TX_D_P6HSMC_TX_D_N6
HSMC_TX_D_P7HSMC_TX_D_N7
HSMC_RX_D_n16HSMC_RX_D_p16
HSMC_RX_D_n9HSMC_RX_D_p9
HSMC_RX_D_n10HSMC_RX_D_p10
HSMC_RX_D_n11HSMC_RX_D_p11
HSMC_RX_D_n12HSMC_RX_D_p12
HSMC_RX_D_n13HSMC_RX_D_p13
HSMC_RX_D_n14HSMC_RX_D_p14
HSMC_RX_D_n15HSMC_RX_D_p15
HSMC_D3HSMC_D1
HSMC_PSNT_n
E_HSMC_CLKIN0E_HSMC_TDO E_HSMC_TDI
HSMC_RX_D_N0HSMC_RX_D_P0
HSMC_RX_D_N1HSMC_RX_D_P1
HSMC_D2HSMC_D0
HSMC_RX_D_N2HSMC_RX_D_P2
HSMC_TX_D_p16HSMC_TX_D_n16
HSMC_TX_D_p11HSMC_TX_D_n11
HSMC_TX_D_p12HSMC_TX_D_n12
HSMC_TX_D_p13HSMC_TX_D_n13
HSMC_TX_D_p14HSMC_TX_D_n14
HSMC_TX_D_p15HSMC_TX_D_n15
HSMC_TX_D_p8HSMC_TX_D_n8
HSMC_TX_D_p9HSMC_TX_D_n9
HSMC_TX_D_p10HSMC_TX_D_n10
HSMC_PSNT_n
E_HSMC_TMSE_HSMC_TCK
E_HSMC_TMSE_HSMC_TCKE_HSMC_TDIE_HSMC_TDO HSMC_TDO
E_HSMC_CLKIN0
EX_IO0EX_IO1EX_IO2EX_IO3
EX_IO4EX_IO5EX_IO6
HSMC_TDI
HSMC_TDO
HSMC_CLKIN_P1HSMC_CLKIN_N1
HSMC_CLKIN_P2HSMC_CLKIN_N2
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
HSMC_CLKOUT_P2HSMC_CLKOUT_N2
HSMC_SDA
HSMC_TMSHSMC_TCKHSMC_TDI
HSMC_CLKIN0
HSMC_CLKOUT_N1HSMC_CLKOUT_P1
HSMC_D[3..0]
EX_IO[6..0]
JTAG_TDO
HSMC_CLKOUT0
HSMC_SCL
VCC3P3
VCC3P3
VCC12
VCC3P3VCC2P5
VCC2P5 VCC3P3
VCC2P5
HSMC_VCCIOGPIO_VCCIO GPIO_VCCIO HSMC_VCCIO
VCC3P3
VCC3P3
VCC3P3VCC12
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC B
DE2-115 Main Board
C
13 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC B
DE2-115 Main Board
C
13 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC B
DE2-115 Main Board
C
13 27Friday, September 24, 2010
JP3
HEADER 3
123
D40
LEDG
C171
0.1u
R158
2.2K
R1592.2K
R77
120
C172
0.1u
R1812.2K
C180
10u
R1712.2K
R1702.2K
VCCA VCCB
DIR GND
A B
U25
SN74AVC1T45
3 46
25
1
VCCA VCCB
OE GND
U22
TXS0104ERGYR
45
2 13121110
14
15
8
1
3
7
R1692.2K
C182
10u
C241
22u
C179
0.1u
JP4
HEADER 7X2
12345678910
11121314
C181
0.1u
R147 10K
R160 33
161
162
163
164
168
165
166
167
169
172
170
171
JP8
HSMC
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
6161
6363
6565
6767
6969
7171
7373
7575
7777
7979
8181
8383
8585
8787
8989
9191
9393
9595
9797
9999
101101
103103
105105
107107
109109
111111
113113
115115
117117
119119
121121
123123
125125
127127
129129
131131
133133
135135
137137
139139
141141
143143
145145
147147
149149
151151
153153
155155
157157
159159
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
6262
6464
6666
6868
7070
7272
7474
7676
7878
8080
8282
8484
8686
8888
9090
9292
9494
9696
9898
100100
102102
104104
106106
108108
110110
112112
114114
116116
118118
120120
122122
124124
126126
128128
130130
132132
134134
136136
138138
140140
142142
144144
146146
148148
150150
152152
154154
156156
158158
160160
161161
162162
163163
164164
165165
166166
167167
168168
169169
170170
171171
172172
R1682.2K
C184
0.1u
C183
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C ADDRESS W/R = 0xA0/0xA1
EEP_I2C_SCLKEEP_I2C_SDAT
VCC3P3
VCC3P3VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE2-115 Main Board
A
14 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE2-115 Main Board
A
14 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE2-115 Main Board
A
14 27Friday, September 24, 2010
R165
DNI
R161
DNI R149
2KC173
0.1u
R1661K
R163
DNI
R1621K
R1641K
A1A0
VSSA2
VCC
SDASCL
WP
U24
24LC32A
4 56
87
123
R150
2K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PHYADR[4:0]=10000b
NET0_10
NET0_100
NET0_1K
NET0_DUP
NET0_RX
NET0_TX
Short pin1 and pin2: RGMII mode
Short pin2 and pin3: MII mode
ENET0_RSET
ENET0_LED_LINK10
ENET0_MDI_p1
ENET_25MHZ
ENET0_LED_LINK100
ENET0_MDI_n1
ENET0_TRST_N
ENET0_MDI_p2ENET0_MDI_n2
ENET0_MDI_n0
ENET0_MDI_p3ENET0_MDI_n3
ENET0_LED_TXENET0_LED_RX
ENET0_RX_DATA1
ENET0_RX_DATA3
ENET0_RX_DATA0
ENET0_RX_DATA2
ENET0_TX_DATA1
ENET0_TX_DATA3
ENET0_TX_DATA0
ENET0_TX_DATA2
ENET0_CONFIG4
ENET0_LED_DUPLEX
ENET0_MDI_p0
ENET0_LED_LINK1000
ENET_25MHZENET0_LED_LINK100
ENET0_LED_DUPLEXENET0_CONFIG4ENET_VCC2P5
ENET0_MDIOENET0_INT_N
ENET0_RST_NENET0_MDC
ENET0_TRST_NENET0_RSET
ENET0_GTX_CLK
ENET0_RX_DATA[3..0]
ENET0_TX_ENENET0_TX_ER
ENET0_RX_ER
ENET0_TX_DATA[3..0]
ENET0_RX_CRSENET0_RX_COL
ENET0_RX_DV
ENET0_RX_CLK
ENET0_MDC
ENET0_RST_N
ENET0_MDIO
ENET0_TX_CLK
ENET0_INT_N
ENETCLK_25ENET0_LINK100ENET1_LINK100
ENET0_VCC1P2A0_VCC2P5
ENET_VCC2P5 A0_VCC2P5
A0_VCC2P5
ENET0_VCC1P2
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
VCC2P5 ENET_VCC2P5
ENET0_VCC1P2VCC1P2
VCC3P3VCC2P5
VCC2P5 VCC3P3
VCC2P5
ENET_VCC2P5
ENET_25MHZ
ENET1_LED_LINK100
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 0 B
DE2-115 Main Board
B
15 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 0 B
DE2-115 Main Board
B
15 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 0 B
DE2-115 Main Board
B
15 27Friday, September 24, 2010
R4
49
.9
C38
0.1u
R121 4.99K
R7
49
.9
D15LEDG
R122 4.7K
R141 120
D16LEDG
C5
10n
C37
0.1u
C174
0.1u
R3
49
.9
C39
0.1u
C138
0.1u
D13LEDG
R6
49
.9
C168
10u
RN20 12012345
678
R2
49
.9
R142 120
R3522
Y2
25MHZ
VCC4
OUT3
GND2
EN1
C139
0.1u
R33 0
C35
0.1u
C142
10u
L15 BEAD
C6
10n
VCCA VCCB
OE GND
U23
TXS0104ERGYR
45
2 13121110
14
15
8
1
3
7
C7
10n
D17LEDG
C34
0.1u
JP1
HEADER 3
123
C20
0.1uS
GM
IIG
MII/M
II/T
BI
MD
I IN
TE
RF
AC
EM
GM
TT
ES
TJT
AG
2.5V
U8
88E1111
COMA27
RESET_n28
MDI0_p29
MDI0_n31
MDI1_p33
MDI1_n34
MDI2_p39
MDI2_n41
MDI3_p42
MDI3_n43
MDIO24
MDC25
INT_n23
HSDAC_p37
HSDAC_n38
RSET30
SEL_FREQ56
125CLK22
XTAL155
XTAL254
VSSC53
TRST_n47
TCK49
TDI44
TDO50
TMS46
GTX_CLK8
TX_CLK4
TX_EN9
TX_ER7
TXD011
TXD112
TXD214
TXD316
TXD417
TXD518
TXD619
TXD720
RXCLK2
RX_DV94
RX_ER3
RXD095
RXD192
RXD293
RXD391
RXD490
RXD589
RXD687
RXD786
CRS84
COL83
S_CLK_p79
S_CLK_n80
S_IN_p82
S_IN_n81
S_OUT_p77
S_OUT_n75
LED_TX68
LED_RX69
LED_DUPLEX70
LED_LINK100073
LED_LINK10074
LED_LINK1076
VS
S9
7
DVDD1
DVDD6
DVDD10
DVDD15
DVDD57
DVDD62
DVDD67
DVDD71
DVDD85
VD
DO
X2
6
VD
DO
X4
8
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H7
2V
DD
OH
66
VD
DO
H5
2
CONFIG065
CONFIG164
CONFIG263
CONFIG361
CONFIG460
CONFIG559
CONFIG658
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
RN18 4.7K1234 5
678
R9
49
.9
L12 BEAD
C19
0.1u
R32 0
C36
0.1u
D12LEDG
C141
0.1u
R148 10K
C17
10u
MX(2) -
MX(1) -
MX(0)+
MX(3) -
MX(1)+
MX(0) -
MX(2)+
MX(3)+
MX(2) -
MX(0) -
MX(3)+
MX(2)+
MX(1) -
MX(3) -
MX(0)+
MX(1)+
VCC
GND
SHIELED
CM
R C
HO
KE
S
J4Jack-RJ45-8P10C-B
2
4
3
19
6
5
11
7810
12
C4
10n
C40
0.1u
R5
49
.9
C140
0.1u
R37 DNI
D14LEDG
R8
49
.9
C18
0.1u
C176
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PHYADR[4:0]=10001b
NET1_TX
NET1_RX
NET1_DUP
NET1_1K
NET1_100
NET1_10
Short pin1 and pin2: RGMII mode
Short pin2 and pin3: MII mode
ENET1_LED_TXENET1_LED_RX
ENET1_LED_LINK1000
ENET1_LED_LINK10
ENET1_RX_DATA1
ENET1_RX_DATA3
ENET1_RX_DATA0
ENET1_RX_DATA2
ENET1_TX_DATA1
ENET1_TX_DATA3
ENET1_TX_DATA0
ENET1_TX_DATA2
ENET1_RSET
ENET_25MHZ
ENET1_TRST_N
ENET1_MDI_p1ENET1_MDI_n1ENET1_MDI_p2ENET1_MDI_n2ENET1_MDI_p3ENET1_MDI_n3
ENET1_MDI_n0ENET1_MDI_p0
ENET1_CONFIG4
ENET1_LED_DUPLEX
ENET1_LED_LINK100
ENET1_LED_DUPLEXENET1_CONFIG4ENET_VCC2P5
ENET1_RST_NENET1_MDCENET1_MDIOENET1_INT_N
ENET1_TRST_NENET1_RSET
ENET1_TX_DATA[3..0]
ENET1_GTX_CLK
ENET1_TX_ENENET1_TX_ER
ENET1_RX_DATA[3..0]
ENET1_RX_DVENET1_RX_ER
ENET1_RX_CRSENET1_RX_COL
ENET1_RX_CLK
ENET1_MDCENET1_MDIO
ENET1_RST_N
ENET1_TX_CLK
ENET1_INT_N
ENET1_VCC1P2
ENET1_VCC1P2
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
A1_VCC2P5
ENET_VCC2P5
ENET_VCC2P5
A1_VCC2P5
A1_VCC2P5
ENET1_VCC1P2VCC1P2
ENET_VCC2P5
ENET1_LED_LINK100
ENET_25MHZ
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 1 B
DE2-115 Main Board
B
16 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 1 B
DE2-115 Main Board
B
16 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet 1 B
DE2-115 Main Board
B
16 27Friday, September 24, 2010
L11 BEAD
C42
0.1u
JP2
HEADER 3
123
RN17 4.7K1234 5
678
R1
44
9.9
C23
0.1u
R1
24
9.9
D19LEDG
R1
04
9.9
C9
10n
D22LEDG
C136
0.1u
C137
10u
C43
0.1u
R119 4.99K
C24
0.1u
R1
64
9.9
R1
14
9.9
D20LEDG
R120 4.7K
R1
74
9.9
RN19 12012345
678
C47
0.1u
C21
10u
C44
0.1u
R140 120
C41
0.1u
C22
0.1u
C46
0.1u
C11
10n
MX(2) -
MX(1) -
MX(0)+
MX(3) -
MX(1)+
MX(0) -
MX(2)+
MX(3)+
MX(2) -
MX(0) -
MX(3)+
MX(2)+
MX(1) -
MX(3) -
MX(0)+
MX(1)+
VCC
GND
SHIELED
CM
R C
HO
KE
S
J5Jack-RJ45-8P10C-B
2
4
3
19
6
5
11
7810
12
D18LEDG
C167
10u
D21LEDG
R38 DNI
SG
MII
GM
II/M
II/T
BI
MD
I IN
TE
RF
AC
EM
GM
TT
ES
TJT
AG
2.5V
U9
88E1111
COMA27
RESET_n28
MDI0_p29
MDI0_n31
MDI1_p33
MDI1_n34
MDI2_p39
MDI2_n41
MDI3_p42
MDI3_n43
MDIO24
MDC25
INT_n23
HSDAC_p37
HSDAC_n38
RSET30
SEL_FREQ56
125CLK22
XTAL155
XTAL254
VSSC53
TRST_n47
TCK49
TDI44
TDO50
TMS46
GTX_CLK8
TX_CLK4
TX_EN9
TX_ER7
TXD011
TXD112
TXD214
TXD316
TXD417
TXD518
TXD619
TXD720
RXCLK2
RX_DV94
RX_ER3
RXD095
RXD192
RXD293
RXD391
RXD490
RXD589
RXD687
RXD786
CRS84
COL83
S_CLK_p79
S_CLK_n80
S_IN_p82
S_IN_n81
S_OUT_p77
S_OUT_n75
LED_TX68
LED_RX69
LED_DUPLEX70
LED_LINK100073
LED_LINK10074
LED_LINK1076
VS
S9
7
DVDD1
DVDD6
DVDD10
DVDD15
DVDD57
DVDD62
DVDD67
DVDD71
DVDD85
VD
DO
X2
6
VD
DO
X4
8
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H7
2V
DD
OH
66
VD
DO
H5
2
CONFIG065
CONFIG164
CONFIG263
CONFIG361
CONFIG460
CONFIG559
CONFIG658
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
R139 120
D23LEDG
C134
0.1u
C135
0.1u
R1
54
9.9
C8
10n
L14 BEAD
C10
10n
R3622
R1
34
9.9
C45
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VG
A_R
7
VG
A_B
1V
GA
_B
0
VG
A_B
5V
GA
_B
4V
GA
_B
3V
GA
_B
2
VG
A_B
7V
GA
_B
6
VG
A_R
6
VG
A_R
2V
GA
_R
3V
GA
_R
4V
GA
_R
5
VG
A_R
0V
GA
_R
1
VGA_G0
VGA_G3VGA_G2VGA_G1
VGA_G6VGA_G5VGA_G4
VGA_G7
VGA_G
RSET
VGA_B
VGA_R
VGA_BLANK_N
VGA_R[7..0]VGA_G[7..0]VGA_B[7..0]
VGA_SYNC_N
VG
A_C
LK
VGA_HSVGA_VS
VGA_VCC3P3
VGA_VCC3P3
VGA_VCC3P3VGA_VCC3P3
VCC3P3 VGA_VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7123 VGA B
DE2-115 Main Board
A
17 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7123 VGA B
DE2-115 Main Board
A
17 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7123 VGA B
DE2-115 Main Board
A
17 27Friday, September 24, 2010
C107
0.1u
R98
75
R97
75
C106
0.1u
R96 47
U7
ADV7123G6
7
SYNC12
G12
G23
B7
21
B8
22
B9
23
CL
OC
K2
4
GND25GND26IOB27IOB28
B3
17
B4
18
B5
19
B6
20
B2
16
B1
15
B0
14
VA
A1
3
G01
G34
BLANK11 G910
G45
G56
G78
G89 VAA
29VAA30IOG31IOG32IOR33IOR34COMP35VREF36
RS
ET
37
PS
AV
E3
8R
03
9R
14
0R
24
1R
34
2R
44
3R
54
4R
64
5R
74
6R
84
7R
94
8
C144
0.1u
R101 4.7K
R95 47
C109
0.1u
R100 560C108
0.1u
C143
10u
C105 0.1u
10
11
6
1
5 15
J13
VGA
5
9
4
8
3
7
2
6
1
17
16
101112131415
R99
75
R123 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C ADDRESS W/R = 0x40/0x41
TD_DATA1
28MHz
28MHz
TD_DATA2TD_DATA3TD_DATA4TD_DATA5TD_DATA6TD_DATA7
TD_DATA0
I2C_SCLK
TD_RESET_N
TD_HSTD_VS
TD_DATA[7..0]
TD_CLK27
I2C_SDAT
V_VCC3P3VGND
PV_VCC1P8
V_VCC3P3
V_VCC3P3
V_VCC1P8
V_VCC3P3
AV_VCC1P8 PV_VCC1P8
V_VCC1P8VCC1P8V_VCC3P3
AV_VCC1P8V_VCC1P8
VCC3P3
VGND
VGNDVGND VGND
VGND
VGND
VGND
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7180 DECODER B
DE2-115 Main Board
B
18 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7180 DECODER B
DE2-115 Main Board
B
18 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ADV7180 DECODER B
DE2-115 Main Board
B
18 27Friday, September 24, 2010
L7 BEAD
R103 39
C149 0.1u
R127 120
C148
10u
U6
ADV7180
HS39
DG
ND
3
XTAL112
XTAL13
DV
DD
14
DG
ND
35
P116P017
P48P39P210
LLC11
P57
P66
P75
INTRQ38
DV
DD
IO1
DV
DD
IO4
DG
ND
15
SFL2
PWRDWN18
PV
DD
20
AG
ND
21
DG
ND
40
AIN123
AIN229
AG
ND
24
TEST_022
VREFP25
AV
DD
27
AG
ND
28
VREFN26
AIN330
RESET31
ALSB32
SDATA33 SCLK34
DV
DD
36
VS/FIELD37
ELPF19
EX
PO
SE
D4
1
C116
0.1u
C146
0.1u
R125 0
J12
RCA JACK
C110
0.1u
C115 0.1u
L6 BEAD
R102
1.74K
C150
0.1u
R104 36
C112
10n
RN1 4712345678 9
10111213141516
C111
10u
C118 0.1u
C113 0.1u
C145
0.1u
C147
10u L8 BEAD
C114
0.1u
D41
BAT54S
123
Y1
28.63636MHZ
VCC4
OUT3
GND2
EN1
R124 0
R126 120
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C ADDRESS = 0x34 (write only)
LINE IN
MIC IN
LINE OUT
I2C_SDAT
AUD_BCLK
AUD_DACLRCK
AUD_ADCLRCK
AUD_DACDAT
I2C_SCLK
AUD_XCK
AUD_ADCDAT
AGND
AGND
AGND
AGNDAGND
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGNDAGND
A_VCC3P3
A_VCC3P3
A_VCC3P3
A_VCC3P3
A_VCC3P3
VCC3P3VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
WM8731 Audio B
DE2-115 Main Board
A
19 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
WM8731 Audio B
DE2-115 Main Board
A
19 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
WM8731 Audio B
DE2-115 Main Board
A
19 27Friday, September 24, 2010
R105
47K
C120 10u
R84
4.7K
C2 100u
C93
1n
R89
47K
R86 4.7K
U5
WM8731
BCLK7
HP
VD
D1
2
XTO2
DCVDD3
MBIAS21
MIC
IN2
2R
LIN
EIN
23
LL
INE
IN2
4M
OD
E2
5C
SB
26
SD
IN2
7S
CL
K2
8
ROUT17AVDD18AGND19VMID20
LOUT16
HPGND15
RH
PO
UT
14
LH
PO
UT
13
XTI/MCLK1
DGND4
AD
CL
RC
K1
1A
DC
DA
T1
0
DBVDD5
CLKOUT6
DA
CD
AT
8
DA
CL
RC
K9
EX
PO
SE
D2
9
C119
0.1u
R90 330
R85 4.7KC91 1u
J3
PHONE JACK G
L1
R2
GN
D3
NC
R4
NC
L5
C153
0.1u
C3 100u
J1
PHONE JACK P
L1
R2
GN
D3
NC
R4
NC
L5
R129
2K
C92 1u
R88 680
C117
0.1u
C151
10u
R128
2K
J2
PHONE JACK B
L1
R2
GN
D3
NC
R4
NC
L5
R106
47K
C94
1u
C152
0.1u
L9 BEAD
R87
4.7K
L13 BEAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GOOD
H_VCC5
O_VCC5
OTG_DATA15OTG_DATA14OTG_DATA13OTG_DATA12OTG_DATA11OTG_DATA10OTG_DATA9OTG_DATA8OTG_DATA7OTG_DATA6
OTG_DATA4OTG_DATA5
OTG_DATA3OTG_DATA2
OTG_DATA0OTG_DATA1
OTG_DATA[15..0]
OTG_FSPEEDOTG_LSPEED
OTG_WR_NOTG_RD_N
OTG_RST_N
OTG_DACK_N0
OTG_DACK_N1
OTG_CS_N
OTG_ADDR1OTG_ADDR0
USB_12MHz
OTG_INT1OTG_INT0
OTG_DREQ1
OTG_DREQ0
U_VCC5VCC5
U_VCC3P3
U_VCC3P3
U_VCC3P3
U_VCC3P3
U_VCC3P3
U_VCC5
U_VCC5
O_VCC5 O_VCC5
H_VCC5 H_VCC5
U_VCC3P3
H_VCC5 O_VCC5U_VCC3P3VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ISP1362 B
DE2-115 Main Board
B
20 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ISP1362 B
DE2-115 Main Board
B
20 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
ISP1362 B
DE2-115 Main Board
B
20 27Friday, September 24, 2010
C121
10n
D45
BAT54S
123
R138 0
R94 1.5K
C101
47p
C154
10n
D43
BAT54S
123
C100
47p
R93 1.5K
C162
10n
C98
47p
R91
15K
D44
BAT54S
123
C158
10u
C163
10n
C97
47p
C156
10n
R134 0
C157
10n
J11
USB A-TYPE
1234
56
R109 22
L10 BEAD
C155 0.1u
R133 10K
L5 BEAD
R110 22
R132 10K
C132
10u
R112 22
C102 0.1u
C95
100u
R108 4.7K
R130 100K D46
BAT54S
123
R111 22
C133
0.1u
C122
0.1u
R131 4.7K
R117 330
R107 4.7K
U4
ISP1362
D67
INT231
INT130
D1012
D22 D33
CS21
WR22
TEST023
DREQ124
DREQ225
VC
C2
6
DG
ND
27
DACK128
D1417 D1518
DG
ND
19
RD20
D1316
D1215
VC
C1
4
D1113
DACK229
RESET32
DG
ND
1
VC
C4
D911
D810
D45 D56
D78
DG
ND
9
H_SUSPEND/H_SUSWKUP33
H_SUSPEND/D_SUSWKUP34
H_PSW135
H_PSW236
DG
ND
37
CLKOUT38
GL39
VC
C4
0
H_OC241
H_OC142
X143
X244
OTGMODE45
H_DM246
H_DP247
ID48
OTG_DM149
OTG_DP150
AG
ND
51
VC
C5
2
CP_CAP153CP_CAP254VBUS55
VDD_5V56
DG
ND
57
VC
C5
8
TEST159TEST260
A061 A162
D063 D164
VBUS GND
D- D+
J10
USB B-TYPE
4
32
1
56
C96
0.1u
C164
10u
C99 0.1u
R92
15K
D2LEDG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_DQ30
DRAM_DQ21
LCD_DATA5
DRAM_DQM3
LCD_DATA0
DRAM_DQ27
DRAM_DQ23
DRAM_ADDR2
DRAM_DQ24
DRAM_ADDR10
DRAM_ADDR12
DRAM_ADDR0
DRAM_DQ3
DRAM_DQ19
DRAM_DQ7
DRAM_DQ31
LCD_DATA4
DRAM_DQ0
DRAM_DQ4
DRAM_DQ9
SRAM_ADDR7
SRAM_ADDR6
SRAM_ADDR14
SRAM_ADDR13
SRAM_DQ8
SRAM_DQ11
SRAM_DQ9
SRAM_DQ12
DRAM_ADDR8
SRAM_ADDR12
SRAM_DQ10
SRAM_ADDR10
DRAM_DQ15
DRAM_ADDR11
DRAM_ADDR9
DRAM_DQ14
SRAM_ADDR4
SRAM_ADDR11
DRAM_ADDR5
DRAM_DQ1
DRAM_DQ12
DRAM_DQ29
LCD_DATA7
LCD_DATA3
DRAM_ADDR6
DRAM_DQ10
LCD_DATA2
DRAM_DQ25
DRAM_DQM0
DRAM_DQM1DRAM_DQ20
LCD_DATA1
DRAM_DQ18
DRAM_ADDR4
DRAM_DQ5
DRAM_DQ17
DRAM_DQ16
DRAM_ADDR3
DRAM_DQ22
DRAM_DQ28
DRAM_DQ2
DRAM_DQ26
DRAM_DQ6
DRAM_DQ8
DRAM_DQM2
DRAM_DQ13
LCD_DATA6
DRAM_DQ11
OTG_DATA1
OTG_DATA14
OTG_DATA3
OTG_DATA11
OTG_DATA2
OTG_DATA10
OTG_DATA4
OTG_DATA12
OTG_DATA0
OTG_DATA13
OTG_DATA6
OTG_DATA8
OTG_DATA7
OTG_DATA9
OTG_DATA5
OTG_DATA15
DRAM_ADDR7
SRAM_ADDR9SRAM_ADDR19
DRAM_ADDR1
OTG_DATA[15..0]
PS2_DAT2
LCD_DATA[7..0]
DRAM_BA1
SRAM_ADDR[19..0]DRAM_DQ[31..0]
SRAM_UB_N
SRAM_DQ[15..0]
LCD_BLON
DRAM_RAS_N
PS2_CLK2
DRAM_DQM[3..0]
DRAM_ADDR[12..0]
OTG_DREQ0
AUD_DACDATPS2_CLK
CLOCK_50
DRAM_CS_N
OTG_ADDR0LCD_ON
PS2_DAT
LCD_RWLCD_RS
LCD_EN
AUD_BCLK
AUD_ADCLRCKAUD_ADCDAT
AUD_DACLRCK
AUD_XCK
FL_RY
DRAM_BA0
DRAM_WE_N
DRAM_CAS_N
DRAM_CKE
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 1 and BANK 2 B
DE2-115 Main Board
B
21 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 1 and BANK 2 B
DE2-115 Main Board
B
21 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 1 and BANK 2 B
DE2-115 Main Board
B
21 27Friday, September 24, 2010
BANK2
U12B
EP4CE115F29
DIFFIO_L25p/DQ0LR2
DIFFIO_L25nR1
DIFFIO_L26pR7
DIFFIO_L26nR6
DIFFIO_L27p/DM0LU3
DIFFIO_L27nU4
DIFFIO_L28p/DQ1LR3
DIFFIO_L28n/DQ1LR4
DIFFIO_L29p/DQ1LT4
DIFFIO_L29nT3
DIFFIO_L30pU2
DIFFIO_L30n/DQ1LU1
DIFFIO_L31p/DQ1LV4
IO_0/DQ1LR5
VREFB2N0T7
DIFFIO_L31nV3
DIFFIO_L32p/DQ1LV2
DIFFIO_L32n/DQ1LV1
DIFFCLK_1p/CLK2Y2
DIFFIO_L33p/DQS1L/CQ1L#,DPCLK1AB2
DIFFIO_L33nAB1
DIFFIO_L34p/DQ1LW2
DIFFIO_L34n/DM1L/BWS#1LW1
DIFFIO_L35p/DQ3LU6
DIFFIO_L35nU5
DIFFIO_L36p/DQ3LY4
DIFFIO_L36nY3
DIFFIO_L37p/DQ3LAC2
DIFFIO_L37n/DQ3LAC1
DIFFIO_L38p/DQ3LAC3
DIFFIO_L38nAD3
DIFFIO_L39p/DQ3LAD2
DIFFIO_L39nAD1
DIFFIO_L40p/DQ3LAA4
DIFFIO_L40nAA3
DIFFIO_L41p/DQ3LAE2
DIFFIO_L41nAE1
DIFFIO_L42pV6
DIFFIO_L42nV5
DIFFIO_L43PV8
DIFFIO_L43nV7
DIFFIO_L44pW4
DIFFIO_L44nW3
DIFFIO_L45pY6
DIFFIO_L45nY5
DIFFIO_L46pW8
DIFFIO_L46nY7
DIFFIO_L47pAA6
DIFFIO_L47nAA5
DIFFIO_L48p/DQS3L/CQ3L#,CDPCLK1AE3
DIFFIO_L48n/DM3L/BWS#3LAF2
DIFFIO_L49pAC5
DIFFIO_L49nAC4
DIFFIO_L50pAB6
DIFFIO_L50nAB5
DIFFCLK_1n/CLK3Y1
VREFB2N1T8
VREFB2N2AB4
IO_1/DQ3LAB3
IO_2W7
IO_3AA7
RUP1U7
RDN1U8
BANK1
U12A
EP4CE115F29
DIFFIO_L1n/DQ2LC2
DIFFIO_L2p/DQ2LD2
DIFFIO_L2n/DQ2LD1
DIFFIO_L3p/DQ2L/nRESETG6
DIFFIO_L3n/DQ2LG5
DIFFIO_L4p/DQS2L/CQ3L,CDPCLK0E3
DIFFIO_L4n/DQ2LF3
DIFFIO_L5p/DQ2LF5
DIFFIO_L6p/DQ2LG4
DIFFIO_L6nG3
DIFFIO_L7pH4
DIFFIO_L7nH3
DIFFIO_L8nE1
DIFFIO_L9p/DM2LF2
DIFFIO_L9n/DQ0LF1
DIFFIO_L10pJ4
DIFFIO_L10n/DQ0LJ3
DIFFIO_L11p/DQ0LG2
DIFFIO_L11nG1
DIFFIO_L12p/DQS0L/CQ1L,DPCLK0K2
DIFFIO_L12n/DQOLK1
DIFFIO_L13pK4
DIFFIO_L13nK3
DIFFIO_L14pL4
DIFFIO_L14nL3
DIFFIO_L15pM4
DIFFIO_L15nM3
DIFFIO_L16pJ6
DIFFIO_L16nJ5
DIFFIO_L17pJ7
DIFFIO_L17nK7
DIFFIO_L18pK8
DIFFIO_L18nL8
DIFFIO_L19pL7
DIFFIO_L19nL6
DIFFIO_L20pN4
DIFFIO_L20nN3
DIFFIO_L21pM8
DIFFIO_L21nM7
DIFFIO_L22pL2
DIFFIO_L22n/DQ0LL1
DIFFIO_L23pM2
DIFFIO_L23n/DQ0LM1
DIFFIO_L24pP2
DIFFIO_L24n/DQ0LP1 DIFFCLK_0n/CLK1
J1
IO_0H6
IO_1H5
IO_2N8
VREFB1N0H7
VREFB1N1L5
VREFB1N2M5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AThe LVDS pair can be exchanged eash other, don't exchange single-ended pins with LVDS pins during PCB layout
SRAM_DQ2
SRAM_DQ7
SRAM_ADDR1
SRAM_ADDR15
FL_ADDR13
SRAM_ADDR16
SRAM_DQ1
SRAM_ADDR3
SRAM_ADDR5
FL_ADDR1
SD_DAT1
FL_ADDR12
FL_DQ0
FL_ADDR20
SRAM_ADDR8
FL_ADDR10
FL_DQ1FL_DQ2FL_DQ3
FL_DQ7
FL_DQ4FL_ADDR9
SRAM_DQ13
FL_ADDR7
FL_DQ5FL_DQ6
FL_ADDR18FL_ADDR8SD_DAT0
FL_ADDR22
SRAM_ADDR2
SRAM_ADDR0
FL_ADDR4
FL_ADDR16
SRAM_DQ15
FL_ADDR6FL_ADDR2
SRAM_DQ4
FL_ADDR5
FL_ADDR0FL_ADDR17
HEX76
FL_ADDR21FL_ADDR11
SD_DAT2
SRAM_DQ3 SD_DAT3
FL_ADDR3
SRAM_DQ0
FL_ADDR14FL_ADDR19
SRAM_ADDR18
SRAM_DQ6SRAM_DQ5
SRAM_DQ14
GPIO9
GPIO16GPIO30GPIO32
GPIO15
HEX45GPIO14
GPIO29GPIO22GPIO24GPIO10GPIO12
GPIO19GPIO25
GPIO33
HEX35
GPIO18GPIO20
HEX40HEX52
GPIO23
GPIO3GPIO5
GPIO27
GPIO13HEX72
HEX36HEX41GPIO0GPIO2GPIO17
GPIO4GPIO6
HEX73
HEX64
GPIO21GPIO35
GPIO7
HEX33
HEX60HEX63
HEX50HEX34
HEX61HEX71HEX74HEX75HEX56
GPIO11HEX62
HEX32HEX51HEX65
HEX66HEX70HEX42HEX43
HEX54HEX53
GPIO26GPIO28GPIO31GPIO34
HEX44
HEX46HEX55
GPIO1GPIO8
FL_ADDR15
SRAM_ADDR17
SRAM_WE_N
GPIO[35..0]
FL_CE_N
SRAM_LB_N
HEX7[6..0]
FL_DQ[7..0]
FL_ADDR[22..0]
DRAM_CLK
FL_WE_N
SD_DAT[3..0]
HEX6[6..0]
CLOCK2_50
HEX5[6..0]
SRAM_DQ[15..0]
IRDA_RXD
SRAM_CE_N
SRAM_ADDR[19..0]
HEX4[6..0]
SMA_CLKIN
FL_RST_N
HEX3[6..0]
SRAM_OE_N
FL_OE_N
SD_CLK
SD_WP_N
SD_CMD
HSMC_CLKIN0
SMA_CLKOUT
CLOCK3_50
FL_WP_N
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 3 and BANK 4 B
DE2-115 Main Board
B
22 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 3 and BANK 4 B
DE2-115 Main Board
B
22 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 3 and BANK 4 B
DE2-115 Main Board
B
22 27Friday, September 24, 2010
BANK4
U12D
EP4CE115F29
DIFFIO_B31p/DM4BAC15
DIFFIO_B31nAD15
DIFFIO_B32pAE15
DIFFIO_B32n/DQ4BAF15
DIFFIO_B33p/DQ4BAG17
DIFFIO_B33n/DQ4BAH17
DIFFIO_B34pAE16
DIFFIO_B34n/DQ4BAF16
DIFFIO_B35pAA16
DIFFIO_B35n/DQ4BAB16
DIFFIO_B36p/DQ4BAE17
DIFFIO_B36n/DQS4B/CQ5B,DPCLK4AF17
DIFFIO_B37p/DQ4BAG18
DIFFIO_B37n/DQ4BAH18
DIFFIO_B38pAG19
DIFFIO_B38n/DM2BAH19
DIFFIO_B39pAC17
DIFFIO_B39n/DQ2BAD17
DIFFIO_B40p/DQ2BAG21
DIFFIO_B40n/DQ2BAH21
DIFFIO_B41p/DQS2B/CQ3B,DPCLK5AE18
DIFFIO_B41nAF18
DIFFIO_B42p/DQ2BAG22
DIFFIO_B42n/DQ2BAH22
DIFFIO_B43pAG23
DIFFIO_B43n/DQ2BAH23
DIFFIO_B44p/DQ2BAE19
DIFFIO_B44nAF19
DIFFIO_B45p/DQ2BAF24
DIFFIO_B45n/DM0BAF25
DIFFIO_B46pAE20
DIFFIO_B46n/DQ0BAF20
DIFFIO_B48p/DQ0BAE25
DIFFIO_B47p/DQ0BAE21
DIFFIO_B47nAF21
DIFFIO_B48n/DQS0B/CQ1B,CDPCLK3AF26
DIFFIO_B49pAG25
DIFFIO_B49n/DQ0BAH25
DIFFIO_B50pAC19
DIFFIO_B50nAD19
DIFFIO_B51pY17
DIFFIO_B51nY16
DIFFIO_B52pAE22
DIFFIO_B52n/DQ0BAF22
DIFFIO_B53pAB19
DIFFIO_B53nAB18
DIFFIO_B54pAD25
DIFFIO_B54n/DQ0BAE24
DIFFIO_B55pAC21
DIFFIO_B55nAD21
DIFFIO_B56pY19
DIFFIO_B56nAA19
DIFFIO_B57pAB22
DIFFIO_B57nAB21
DIFFIO_B58pAC22
DIFFIO_B58nAD22
DIFFIO_B59p/DQ0BAG26
DIFFIO_B59nAH26
DIFFCLK_7p/CLK13AG15
DIFFCLK_7n/CLK12AH15
IO_0AB15
IO_1/DQ0BAD18
IO_2AD24
IO_3AA21
VREFB4N0AB20
VREFB4N1AC18
VREFB4N2AA15
RUP2AA17
RDN2AB17
PLL4_CLKOUTpAE23
PLL4_CLKOUTnAF23
BANK3
U12C
EP4CE115F29
DIFFIO_B1pAD5
DIFFIO_B1n/DM1BAE6
DIFFIO_B2pAD4
DIFFIO_B2n/DQ1BAF4
DIFFIO_B3pAE4
DIFFIO_B3n/DQ1BAG3
DIFFIO_B4p/DQ1BAH3
DIFFIO_B4nAF3
DIFFIO_B5pAG4
DIFFIO_B5n/DQ1BAH4
DIFFIO_B6p/DQ1BAD8
DIFFIO_B6nAC7
DIFFIO_B7p/DQ1BAG6
DIFFIO_B7n/DQ1BAH6
DIFFIO_B8p/DM3B/BWS#3BAB9
DIFFIO_B8nAB8
DIFFIO_B9p/DQ3BAG7
DIFFIO_B9n/DQ3BAH7
DIFFIO_B10pAB7
DIFFIO_B10n/DQ3BAC8
DIFFIO_B11pAA8
DIFFIO_B11n/DQ3BAA10
DIFFIO_B12p/DQ3BAG8
DIFFIO_B12n/DQ3BAH8
DIFFIO_B13pAE7
DIFFIO_B13n/DQ3BAF7
DIFFIO_B14pAE8
DIFFIO_B14n/DM5B/BWS#5BAF8
DIFFIO_B15p/DQS3B/CQ3B#,DPCLK2AE10
DIFFIO_B15n/DQ5BAF10
DIFFIO_B16p/DQ5BAG10
DIFFIO_B16nAH10
DIFFIO_B17p/DQ5BAE12
DIFFIO_B17nAF12
DIFFIO_B18p/DQ5BAE11
DIFFIO_B18n/DQS5B/CQ5B#,DPCLK3AF11
DIFFIO_B19pAB10
DIFFIO_B19nAC10
DIFFIO_B20p/DQ5BAG11
DIFFIO_B20n/DQ5BAH11
DIFFIO_B21p/DQ5BAE13
DIFFIO_B21nAF13
DIFFIO_B22pAC12
DIFFIO_B22nAB12
DIFFIO_B23pAE14
DIFFIO_B23nAF14
DIFFIO_B24pAC11
DIFFIO_B24nAD11
DIFFIO_B25pY12
DIFFIO_B25nAA12
DIFFIO_B26pY13
DIFFIO_B26nAA13
DIFFIO_B27pAA14
DIFFIO_B27nAB14
DIFFIO_B28p/DQ5BAG12
DIFFIO_B28nAH12
DIFFIO_B29pAC14
DIFFIO_B29nAD14
DIFFIO_B30pY14
DIFFIO_B30nY15
DIFFCLK6p/CLK15AG14
DIFFCLK6n/CLK14AH14
IO_0/DQS1B/CQ1B#,CDPCLK2AD7
IO_1/DQ1BAF6
IO_2/DQ3BAD10
IO_3/DQ3BAF9
IO_4/DQ5BAE9
IO_5AD12
VREFB3N0AB13
VREFB3N1AB11
VREFB3N2Y10
PLL1_CLKOUTpAE5
PLL1_CLKOUTnAF5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The LVDS pair can be exchanged eash other, don't exchange single-ended pins with LVDS pins during PCB layout
Close to FPGA
HSMC_RX_D_n3HSMC_RX_D_p3
HSMC_RX_D_n15HSMC_RX_D_p15
HSMC_RX_D_n16HSMC_RX_D_p16
HSMC_RX_D_n4HSMC_RX_D_p4
HSMC_RX_D_n5HSMC_RX_D_p5
HSMC_RX_D_n6HSMC_RX_D_p6
HSMC_RX_D_n7HSMC_RX_D_p7
HSMC_CLKIN_P1
HSMC_RX_D_n8HSMC_RX_D_p8
HSMC_CLKIN_N1
HSMC_CLKIN_P2 HSMC_CLKIN_N2HSMC_RX_D_n1HSMC_RX_D_p1
HSMC_RX_D_n9HSMC_RX_D_p9
HSMC_RX_D_n10HSMC_RX_D_p10
HSMC_RX_D_n0HSMC_RX_D_p0
HSMC_RX_D_n11HSMC_RX_D_p11
HSMC_RX_D_n12HSMC_RX_D_p12
HSMC_RX_D_n2HSMC_RX_D_p2
HSMC_RX_D_n13HSMC_RX_D_p13
HSMC_RX_D_n14HSMC_RX_D_p14
HSMC_TX_D_N10HSMC_TX_D_P10
HSMC_TX_D_P8HSMC_TX_D_N8
SW8
SW13HEX15HEX16
HEX31KEY3
SW10HSMC_D3HSMC_D0SW6SW5
SW12SW15
SW11SW14
HEX13HEX11
HEX12
HEX26HEX25HEX14HEX23
HEX22HEX24
HEX20
HSMC_D2HSMC_D1
HEX30
HEX06HEX04HEX03HEX10KEY0
HEX05KEY1KEY2
SW0SW4
SW17SW1SW2SW7SW9
SW3SW16
HSMC_RX_D_N14HSMC_RX_D_P14
HSMC_RX_D_P10HSMC_RX_D_N10
HSMC_RX_D_N15HSMC_RX_D_P15
HSMC_TX_D_P16HSMC_TX_D_N16
HSMC_TX_D_P15
HSMC_RX_D_P16HSMC_RX_D_N16
HSMC_TX_D_N15
HSMC_TX_D_N14HSMC_TX_D_P14
HSMC_TX_D_P12HSMC_TX_D_N12
HSMC_TX_D_N13HSMC_TX_D_P13
HSMC_RX_D_N8HSMC_RX_D_P8
HSMC_RX_D_P9HSMC_RX_D_N9
HSMC_RX_D_P0HSMC_RX_D_N0
HSMC_TX_D_N5HSMC_TX_D_P5
HSMC_RX_D_P7HSMC_RX_D_N7
HSMC_TX_D_N7HSMC_TX_D_P7
HSMC_RX_D_P3HSMC_RX_D_N3
HSMC_RX_D_N12HSMC_RX_D_P12
HSMC_TX_D_P6HSMC_TX_D_N6
HSMC_TX_D_P1HSMC_RX_D_N4HSMC_RX_D_P4
HSMC_TX_D_N3HSMC_TX_D_P3
HSMC_TX_D_N2HSMC_TX_D_P2HSMC_TX_D_N1
HSMC_RX_D_N5HSMC_RX_D_P5
HSMC_RX_D_P11HSMC_RX_D_N11
HSMC_TX_D_N4HSMC_TX_D_P4
HSMC_TX_D_N0HSMC_TX_D_P0
HSMC_TX_D_N9HSMC_TX_D_P9
HSMC_RX_D_N13HSMC_RX_D_P13
HSMC_RX_D_N1HSMC_RX_D_P1
HSMC_RX_D_N6HSMC_RX_D_P6
HSMC_RX_D_N2HSMC_RX_D_P2
HSMC_TX_D_P11HSMC_TX_D_N11HEX21
HSMC_TX_D_P[16..0]
HSMC_TX_D_N[16..0]
HSMC_RX_D_P[16..0]
HSMC_RX_D_N[16..0]
HSMC_D[3..0]
SW[17..0]
KEY[3..0]
HEX2[6..0]
HEX1[6..0]
HEX0[6..0]HEX3[6..0]
HSMC_CLKOUT_P2HSMC_CLKOUT_N2
HSMC_CLKOUT0 HSMC_CLKIN_P2HSMC_CLKIN_N2
HSMC_CLKIN_P1HSMC_CLKIN_N1
HSMC_CLKOUT_P1HSMC_CLKOUT_N1
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 5 and BANK 6 B
DE2-115 Main Board
B
23 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 5 and BANK 6 B
DE2-115 Main Board
B
23 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 5 and BANK 6 B
DE2-115 Main Board
B
23 27Friday, September 24, 2010
R72 DNI
BANK5
U12E
EP4CE115F29
DIFFIO_R25pP21
DIFFIO_R25nR21
DIFFIO_R26pR22
DIFFIO_R26nR23
DIFFIO_R27pR27
DIFFIO_R27n/DM0RR28
DIFFIO_R28pR25
DIFFIO_R28n/DQ1RR26
DIFFIO_R29p/DEV_CLRnT21
DIFFIO_R29n/DEV_OET22
DIFFIO_R30p/DQS1R/CQ1R#,DPCLK6T25
DIFFIO_R30nT26
DIFFIO_R31pW22
DIFFIO_R31nY22
DIFFIO_R32pU27
DIFFIO_R32n/DQ1RU28
DIFFIO_R33pU25
DIFFIO_R33nU26
DIFFIO_R34pU22
DIFFIO_R34nV22
DIFFIO_R35pV21
DIFFIO_R35nW21
DIFFIO_R36pV23
DIFFIO_R36nV24
DIFFIO_R37p/DQ1RV25
DIFFIO_R37nV26
DIFFIO_R38pV27
DIFFIO_R38n/DQ1RV28
DIFFIO_R39p/DQ1RW28
DIFFIO_R39n/DQ1RW27
DIFFIO_R40pW25
DIFFIO_R40n/DQ1RW26
DIFFIO_R41pY25
DIFFIO_R41n/DQ1RY26
DIFFIO_R42p/DQ1RAB27
DIFFIO_R42n/DM1R/BWS#1RAB28
DIFFIO_R43pAA25
DIFFIO_R43n/DQ3RAA26
DIFFIO_R44pAB25
DIFFIO_R44n/DQ3RAB26
DIFFIO_R45p/DQ3RAC27
DIFFIO_R45n/DQ3RAC28
DIFFIO_R46pY23
DIFFIO_R46n/DQ3RY24
DIFFIO_R47p/DQ3RAD27
DIFFIO_R47n/DQ3RAD28
DIFFIO_R48pAE27
DIFFIO_R48n/DQ3RAE28
DIFFIO_R49pAC26
DIFFIO_R49n/DQ3RAD26
DIFFIO_R50pAE26
DIFFIO_R50n/DQS3R/CQ3R#,CDPCLK4AF27
DIFFIO_R51pAC24
DIFFIO_R51nAC25
IO_0R24
IO_1U21
IO_2AA23
IO_3/DM3R/BWS#3RAB24
RUP3AA22
RDN3AB23
VREFB5N0U24
VREFB5N1U23
VREFB5N2AA24
DIFFCLK_3p/CLK6Y27
DIFFCLK_3n/CLK7Y28
R58 DNI
BANK6
U12F
EP4CE115F29
DIFFIO_R1pG23
DIFFIO_R1nG24
DIFFIO_R2pF24
DIFFIO_R2nF25
DIFFIO_R3pG25
DIFFIO_R3nG26
DIFFIO_R4pH23
DIFFIO_R4nH24
DIFFIO_R5pK21
DIFFIO_R5nK22
DIFFIO_R6pJ23
DIFFIO_R6nJ24
DIFFIO_R7pL21
DIFFIO_R7nL22
DIFFIO_R8pD26
DIFFIO_R8n/DQS2R/CQ3R,CDPCLK5/PADD20C27
DIFFIO_R9p/DQ2R/PADD21D27
DIFFIO_R9n/PADD22D28
DIFFIO_R10p/DQ2RF26
DIFFIO_R10nE26
DIFFIO_R11pH25
DIFFIO_R11nH26
DIFFIO_R12p/DQ2RE27
DIFFIO_R12n/DQ2R/PADD23E28
DIFFIO_R13pF27
DIFFIO_R13n/DQ2R/nAVDF28
DIFFIO_R14pK25
DIFFIO_R14n/DQ2RK26
DIFFIO_R15p/DQ2R/nOEG27
DIFFIO_R15n/DQ2R/nWEG28
DIFFIO_R16pJ25
DIFFIO_R16nJ26
DIFFIO_R17p/DQ0RK27
DIFFIO_R17n/DQ0RK28
DIFFIO_R18pL23
DIFFIO_R18n/DQ0RL24
DIFFIO_R19p/DQ0RL27
DIFFIO_R19n/DQ0RL28
DIFFIO_R20pM25
DIFFIO_R20n/DQ0RM26
DIFFIO_R21p/DQ0RM27
DIFFIO_R21n/DQ0RM28
DIFFIO_R22pN25
DIFFIO_R22n/DQS0R/CQ1R,DPCLK7N26
DIFFIO_R23p/CLKUSRP27
DIFFIO_R23n/nCEOP28
DIFFIO_R24p/CRC_ERRORP25
DIFFIO_R24n/INIT_DONEP26
IO_0H22
IO_1L25
IO_2/DM2RL26
IO_3M24
IO_4M23
VREFB6N0J22
VREFB6N1M21
VREFB6N2N21
DIFFCLK_2p/CLK4J27
DIFFCLK_2n/CLK5J28
R71 DNI
R74 DNI
R61 DNI
R76 DNI
R75 DNI
R64 DNI
R59 DNI
R70 DNI
R55 DNI
R67 DNI
R73 DNI
R66 DNI
R57 DNI
R65 DNI
R56 DNI
R60 DNI
R69 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EX_IO1EX_IO3
EX_IO4
VGA_R5
EX_IO2
VGA_G3
EX_IO5
EX_IO0
EX_IO6
ENET1_RX_DATA0ENET1_RX_DATA2
LEDR3LEDG0
ENET1_TX_DATA1LEDG1
ENET1_TX_DATA2
HEX01
ENET1_RX_DATA3
LEDR8
LEDR1LEDR2
LEDR9LEDR15
ENET1_RX_DATA1
ENET0_TX_DATA0
ENET0_RX_DATA3
ENET1_TX_DATA0
ENET0_RX_DATA1
HEX00
LEDR14LEDR10LEDR17
HEX02
LEDR11LEDR12
LEDG8LEDR13LEDR16
ENET1_TX_DATA3
LEDR0LEDG6LEDG4LEDR6LEDR7LEDG7LEDG5
ENET0_TX_DATA3ENET0_TX_DATA2
ENET0_TX_DATA1
LEDG2LEDG3
LEDR4LEDR5
ENET0_RX_DATA0
ENET0_RX_DATA2
TD_DATA3
TD_DATA1
TD_DATA0
TD_DATA4
TD_DATA2
TD_DATA7
TD_DATA6TD_DATA5
VGA_R6VGA_G0
VGA_G5
VGA_G2
VGA_G4
VGA_R4VGA_G6
VGA_G7VGA_B6VGA_B2
VGA_G1
VGA_R1VGA_R3VGA_R0VGA_R2
VGA_B0VGA_B1
VGA_R7
VGA_B3VGA_B4
VGA_B7VGA_B5
ENET0_RX_DATA[3..0]
ENET0_TX_DATA[3..0] ENET1_TX_DATA[3..0]
ENET1_RX_DATA[3..0]
LEDG[8..0] LEDR[17..0]
UART_RTS
EEP_I2C_SCLK
EEP_I2C_SDAT
I2C_SCLK
I2C_SDAT
TD_CLK27
TD_DATA[7..0]
TD_VSTD_HS
TD_RESET_N
VGA_R[7..0]
VGA_G[7..0]
VGA_B[7..0] EX_IO[6..0]
OTG_RST_NOTG_INT1
OTG_DACK_N0OTG_DACK_N1
OTG_DREQ1OTG_WR_N
OTG_CS_NOTG_RD_N
OTG_LSPEED
OTG_FSPEED
OTG_INT0
ENETCLK_25
ENET0_LINK100ENET1_LINK100
ENET1_RST_N
ENET0_TX_EN
ENET1_TX_EN
ENET1_GTX_CLK
ENET1_RX_COL
ENET1_RX_CRS
ENET0_MDIO
ENET0_RX_CRS
ENET0_RST_N
ENET1_TX_ER
ENET0_RX_DV
ENET1_TX_CLK
ENET0_TX_ER
ENET0_GTX_CLK
ENET0_MDC
ENET1_MDIO
ENET1_RX_CLK
ENET1_RX_DV
ENET1_INT_N ENET0_RX_CLK
ENET1_MDC
ENET0_INT_N
ENET1_RX_ER
ENET0_RX_COL
ENET0_TX_CLK
ENET0_RX_ER
OTG_ADDR1
VGA_SYNC_N
VGA_HS
VGA_BLANK_N
VGA_CLK
VGA_VS
UART_CTSUART_RXDUART_TXD
HEX0[6..0]
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 7 and BANK 8 B
DE2-115 Main Board
B
24 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 7 and BANK 8 B
DE2-115 Main Board
B
24 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 BANK 7 and BANK 8 B
DE2-115 Main Board
B
24 27Friday, September 24, 2010
BANK7
U12G
EP4CE115F29
DIFFIO_T32p/DQ5T/PADD14D15
DIFFIO_T32n/PADD13C15
DIFFIO_T33p/DM4TE15
DIFFIO_T33nF15
DIFFIO_T34pJ15
DIFFIO_T34nH15
DIFFIO_T35p/DQS4T/CQ5T,DPCLK9/PADD12B17
DIFFIO_T35n/PADD11A17
DIFFIO_T36p/PADD10D16
DIFFIO_T36n/DQ4T/PADD9C16
DIFFIO_T37pH16
DIFFIO_T37nJ16
DIFFIO_T38p/DQ4TE17
DIFFIO_T38nF17
DIFFIO_T39pH17
DIFFIO_T39nG16
DIFFIO_T40pG18
DIFFIO_T40nG19
DIFFIO_T41pG22
DIFFIO_T41nH21
DIFFIO_T42pJ19
DIFFIO_T42nH19
DIFFIO_T43pG21
DIFFIO_T43nG20
DIFFIO_T44p/DQ4T/PADD8B18
DIFFIO_T44n/PADD7A18
DIFFIO_T45p/DQ4T/PADD6B19
DIFFIO_T45n/DQ4T/PADD5A19
DIFFIO_T46p/DQS2T/CQ3T,DPCLK8/PADD4D17
DIFFIO_T46n/DQ4T/PADD3C17
DIFFIO_T47pD19
DIFFIO_T47n/DQ4TC19
DIFFIO_T48pE25
DIFFIO_T48nE24
DIFFIO_T49p/DQ4TD20
DIFFIO_T49n/DM2TC20
DIFFIO_T50p/PADD2D18
DIFFIO_T50n/PADD1C18
DIFFIO_T51pF18
DIFFIO_T51n/DQ2TE18
DIFFIO_T52p/DQ2TB21
DIFFIO_T52n/DQ2TA21
DIFFIO_T53p/PADD0B22
DIFFIO_T53n/DQ2TA22
DIFFIO_T54p/DQ2TD21
DIFFIO_T54n/DQ2TC22
DIFFIO_T55pD24
DIFFIO_T55n/DQ2TC24
DIFFIO_T56p/DM0TB23
DIFFIO_T56n/DQ0TA23
DIFFIO_T57p/DQ0TC25
DIFFIO_T57nD25
DIFFIO_T58p/DQ0TF21
DIFFIO_T58nE21
DIFFIO_T59p/DQS0T/CQ1T,CDPCLK6A25
DIFFIO_T59n/DQ0TA26
DIFFIO_T60p/DQ0TE22
DIFFIO_T60n/DQ0TD22
DIFFIO_T61p/DQ0TB26
DIFFIO_T61nC26
IO_0J17
IO_1/DQ2TC21
IO_2/DQ0TB25
RUP4F19
RDN4E19
VREFB7N0F22
VREFB7N1G17
VREFB7N2G15
PLL2_CLKOUTpD23
PLL2_CLKOUTnC23
DIFFCLK_5p/CLK9B15
DIFFCLK_5n/CLK8A15
BANK8
U12H
EP4CE115F29
DIFFIO_T1pE5
DIFFIO_T1nE4
DIFFIO_T2p/DM1TD4
DIFFIO_T2n/DQ1TC4
DIFFIO_T3p/DQ1TA3
DIFFIO_T3nB3
DIFFIO_T4p/DQS1T/CQ1T#,CDPCLK7/DATA12B4
DIFFIO_T4n/DQ1TA4
DIFFIO_T5pF7
DIFFIO_T5nG7
DIFFIO_T6pH8
DIFFIO_T6nG8
DIFFIO_T7pF8
DIFFIO_T7nE8
DIFFIO_T8p/DQ1TD6
DIFFIO_T8nE7
DIFFIO_T9p/DATA11D7
DIFFIO_T9n/DQ1T/DATA10C7
DIFFIO_T10p/DQ1TD8
DIFFIO_T10n/DQ1TC8
DIFFIO_T11pB8
DIFFIO_T11n/DM3T/BWS#3T/DATA9A8
DIFFIO_T12pJ10
DIFFIO_T12nH10
DIFFIO_T13pG10
DIFFIO_T13nF10
DIFFIO_T14p/DATA8D9
DIFFIO_T14n/DQ3TC9
DIFFIO_T15pD11
DIFFIO_T15n/DQ3T/DATA7C11
DIFFIO_T16pH12
DIFFIO_T16nG11
DIFFIO_T17p/DQ3T/DATA6B6
DIFFIO_T17nA6
DIFFIO_T18p/DQ3T/DATA5B7
DIFFIO_T18n/DQ3TA7
DIFFIO_T19pF11
DIFFIO_T19n/DQ3TE11
DIFFIO_T20p/DATA13F12
DIFFIO_T20n/DQS3T/CQ3T#,DPCLK11/DATA14E12
DIFFIO_T21p/DQ3TD10
DIFFIO_T21n/DQ3TC10
DIFFIO_T22p/DQ3T/DATA15H13
DIFFIO_T22n/PADD19G13
DIFFIO_T23p/DM5T/BWS#5T/DATA4B10
DIFFIO_T23n/PADD18A10
DIFFIO_T24pJ12
DIFFIO_T24nJ13
DIFFIO_T25p/DQ5T/DATA3B11
DIFFIO_T25n/DQ5T/DATA2A11
DIFFIO_T26p/DQ5TE14
DIFFIO_T26nF14
DIFFIO_T27n/DQ5TA12
DIFFIO_T28pJ14
DIFFIO_T28nH14
DIFFIO_T29p/DQS5T/CQ5T#,DPCLK10/PADD17D12
DIFFIO_T29n/DQ5T/PADD16C12
DIFFIO_T30p/PADD15D14
DIFFIO_T30n/DQ5TC14
DIFFIO_T31p/DQ5TD13
DIFFIO_T31n/DQ5TC13
IO_0C3
IO_1/DQ1TC6
IO_2E10
VREFB8N0G14
VREFB8N1G12
VREFB8N2G9
PLL3_CLKOUTpD5
PLL3_CLKOUTnC5
DIFFCLK_4p/CLK11B14
DIFFCLK_4n/CLK10A14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bnak1 Bnak2 Bnak3 Bnak4
Bnak5 Bnak6 Bnak7 Bnak8
TDO
TCK
TMS
TDI
TMSTDO
TCKTDINCENCONFIGDATA0DCLK ASDO
NCSONSTATUSCONF_DONE
VCCA
VCCIO3P3
VCCINTVCC1P2
VCC3P3
VCCA
VCCA
VCCIO3P3 VCCIO3P3 VCCIO3P3 VCCIO3P3
VCCINT
HSMC_VCCIO HSMC_VCCIOGPIO_VCCIO VCCIO2P5
VCC2P5 VCCIO2P5
VCCINT VCCD_PLLVCC2P5 VCCA
VCCD_PLL
VCCA
VCCIO3P3 VCCIO3P3 VCCIO3P3 GPIO_VCCIO
HSMC_VCCIO HSMC_VCCIO VCCIO2P5 VCCIO3P3
VCCD_PLL VCCA
VCCINT
VCCINT
VCCINT
VCCINT
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 POWER and CONFIG B
DE2-115 Main Board
C
25 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 POWER and CONFIG B
DE2-115 Main Board
C
25 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE115 POWER and CONFIG B
DE2-115 Main Board
C
25 27Friday, September 24, 2010
C214
22n
C205
0.1u
C190
0.1u
C209
22n
C237
0.1u
C57
100u
C213
0.47u
C219
0.1u
C198
0.1u
C240
0.1u
C79
100u
C232
0.47u
C270
0.1u
C223
0.1u
R202
10K
C234
22n
R175
0
R45 0
C247
0.1u
R44 0
C216
0.1u
C250
0.1u
C230
22n
C201
DNI
C245
0.47u
C252
0.1u
C193
0.1u
R63 0
L2 BEAD
C71
100u
C251
0.1u
C249
0.1u
C186
0.1u
C228
10n
C243
0.1u
R46 0
C188
0.1u
C264
0.1u
C59
10u
L4 BEAD
C58
10u
C239
0.1u
C208
22n
C70
100u
R188 DNI
C226
0.1u
C217
10n
C231
22n
C244
0.1u
R62 0
R203
10K
C189
0.1u
C187
0.1u
C200
0.1u
C196
0.1u
C242
0.1u
R172
DNI
C218
10n
C255
0.1u
C269
0.1u
R201 DNI
POWER & GROUND
U12I
EP4CE115F29
GN
DK
10
GN
DK
12
GN
DK
14
GN
DK
16
GN
DK
18
GN
DK
20
GN
DL9
GN
DL11
GN
DL13
GN
DL15
GN
DL17
GN
DL19
GN
DM
10
GN
DM
12
GN
DM
14
GN
DM
16
GN
DM
18
GN
DM
20
GN
DN
9
GN
DN
11
GN
DN
13
GN
DN
15
GN
DN
17
GN
DN
19
GN
DP
10
GN
DP
12
GN
DP
14
GN
DP
16
GN
DP
18
GN
DP
20
GN
DR
9
GN
DR
11
GN
DR
13
GN
DR
15
GN
DR
17
GN
DR
19
GN
DT
10
GN
DT
12
GN
DT
14
GN
DT
16
GN
DT
18
GN
DT
20
GN
DU
9
GN
DU
11
GN
DU
13
GN
DU
15
GN
DU
17
GN
DU
19
GN
DV
10
GN
DV
12
GN
DV
14
GN
DV
16
GN
DV
18
GN
DV
20
GN
DW
9
GN
DW
11
GN
DW
13
GN
DW
15
GN
DW
17
GN
DW
19
GNDAA2GNDAA27GNDAC6GNDAC9GNDAC13GNDAC16GNDAC20GNDAC23GNDAF1GNDAF28GNDAG2GNDAG5GNDAG9GNDAG13GNDAG16GNDAG20GNDAG24GNDAG27GNDB2GNDB5GNDB9GNDB13GNDB16GNDB20GNDB24GNDB27GNDC1GNDC28GNDF6GNDF9GNDF13GNDF16GNDF20GNDF23GNDH2GNDH27GNDJ11GNDJ18GNDK6GNDK23GNDN2GNDN6GNDN23GNDN27GNDT2GNDT6GNDT23GNDT27GNDW6GNDW23GNDY11GNDY18GNDJ2GNDD3GNDB12
GNDA1AA9GNDA2H20GNDA3H9GNDA4AA20VCCINT
K9
VCCINTK11
VCCINTK13
VCCINTK15
VCCINTK17
VCCINTK19
VCCINTL10
VCCINTL12
VCCINTL14
VCCINTL16
VCCINTL18
VCCINTL20
VCCINTM9
VCCINTM11
VCCINTM13
VCCINTM15
VCCINTM17
VCCINTM19
VCCINTN10
VCCINTN12
VCCINTN14
VCCINTN16
VCCINTN18
VCCINTN20
VCCINTP9
VCCINTP11
VCCINTP13
VCCINTP15
VCCINTP17
VCCINTP19
VCCINTR10
VCCINTR12
VCCINTR14
VCCINTR16
VCCINTR18
VCCINTR20
VCCINTT9
VCCINTT11
VCCINTT13
VCCINTT15
VCCINTT17
VCCINTT19
VCCINTU10
VCCINTU12
VCCINTU14
VCCINTU16
VCCINTU18
VCCINTU20
VCCINTV9
VCCINTV11
VCCINTV13
VCCINTV15
VCCINTV17
VCCINTV19
VCCINTW10
VCCINTW12
VCCINTW14
VCCINTW16
VCCINTW18
VCCINTW20
VCCD_PLL1Y9
VCCD_PLL2J20
VCCD_PLL3J9
VCCD_PLL4Y20
VCCA1Y8
VCCA2J21
VCCA3J8
VCCA4Y21
VC
CIO
1B
1
VC
CIO
1H
1
VC
CIO
1K
5
VC
CIO
1N
1
VC
CIO
1N
5
VC
CIO
2A
A1
VC
CIO
2A
G1
VC
CIO
2T
1
VC
CIO
2T
5
VC
CIO
2W
5
VC
CIO
3A
A11
VC
CIO
3A
D6
VC
CIO
3A
D9
VC
CIO
3A
D13
VC
CIO
3A
H2
VC
CIO
3A
H5
VC
CIO
3A
H9
VC
CIO
3A
H13
VC
CIO
4A
A18
VC
CIO
4A
D16
VC
CIO
4A
D20
VC
CIO
4A
D23
VC
CIO
4A
H16
VC
CIO
4A
H20
VC
CIO
4A
H24
VC
CIO
4A
H27
VC
CIO
5A
A28
VC
CIO
5A
G28
VC
CIO
5T
24
VC
CIO
5T
28
VC
CIO
5W
24
VC
CIO
6B
28
VC
CIO
6H
28
VC
CIO
6K
24
VC
CIO
6N
24
VC
CIO
6N
28
VC
CIO
7A
16
VC
CIO
7A
20
VC
CIO
7A
24
VC
CIO
7A
27
VC
CIO
7E
16
VC
CIO
7E
20
VC
CIO
7E
23
VC
CIO
7H
18
VC
CIO
8A
2
VC
CIO
8A
5
VC
CIO
8A
9
VC
CIO
8A
13
VC
CIO
8E
6
VC
CIO
8E
9
VC
CIO
8E
13
VC
CIO
8H
11
R173
0CONTROL SIGNAL
U12J
EP4CE115F29
MSEL0N22
MSEL1P23
MSEL2M22
MSEL3P22
CONF_DONEP24
ASDOF4
nCSOE2
nSTATUSM6
DCLKP3
DATA0N7
nCONFIGP4
nCER8
TDIP7
TCKP5
TMSP8
TDOP6
C238
0.1u
C268
0.1u
C221
10n
C197
0.1u
C233
22n
C206
0.1u
C195
0.1u
C207
0.1u
C199
0.1u
C225
10n
C81
10u
C194
0.1u
C265
0.1u
R187
0
C80
100u
C227
10n
R185
DNI
C254
0.47u
C248
0.1u
C204
0.1u
C271
0.1u
C266
0.1u
C224
10n
C212
22n
C215
22n
C246
0.47u
C235
0.1u
C220
10n
C222
0.1u
C257
0.1u
R186
DNI
C253
0.47u
C192
0.1u
R47 0
C267
0.1u
C236
0.1u
C256
0.1u
C210
0.47u
R184
0
C211
22n
C229
0.47u
R174
DNI
C185
0.1u
R68 0
R1891K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2V/5A
3.3V/6A
POWER
VCC12
VCC1P2
VCC12
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V B
DE2-115 Main Board
B
26 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V B
DE2-115 Main Board
B
26 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V B
DE2-115 Main Board
B
26 27Friday, September 24, 2010
Q1
IRF7455PbF
5 6 7 8
123
4
C29
330u
D11 SM340A
R245
75K
L1 3.3uH
Q3
IRF7455PbF
5 6 7 8
123
4
C203
0.1u
1V2
C49
2.2u
C73
3.3n
C61
15n
C51
15n
R118
120
R146
10K
C191
0.47u
D1
LEDB
C53
0.1u
C74
2.2u
SW18
POWER SW
51
6
24
3
3V3
Q4
IRF7455PbF
5 6 7 8
123
4
REG2
LM3150MH
VIN2
RON7
SS6
EN3
SGND5
SGND9
FB
4
PG
ND
14
LG13
ILIM8
SW10
BST12
VCC1
HG11
EP
15
C54
2.2u
R244
DNI
D10 SM340A
C170
1.2n
R191
4.87K
C30
DNI
D9 SM340A
L3 3.3uH
R145
10K
R39
34K
R48
52.3K
C60
22u
C31
DNI
J8 DC_12V123
C48
0.1u
REG3
LM3150MH
VIN2
RON7
SS6
EN3
SGND5
SGND9
FB
4
PG
ND
14
LG13
ILIM8
SW10
BST12
VCC1
HG11
EP
15
C202
390p
R180
2.4K
C50
22u
D8 SM340A
C72
330u
R157
1.78K
C32
0.1u
C175
0.47u
Q2
IRF7455PbF
5 6 7 8
123
4
R190
22K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ADJ/1A for Bank 4 I/O Voltage/1A
ADJ/1A for Bank 5 & 6 I/O Voltage/1A
5V/3A
1.8V/1A
2.5V/1A
JP6:1-2 : 1.5V3-4 : 1.8V5-6 : 2.5V7-8 : 3.3V
JP7:1-2 : 1.5V3-4 : 1.8V5-6 : 2.5V7-8 : 3.3V
VCC12 VCC5
VCC3P3
VCC3P3
GPIO_VCCIO
HSMC_VCCIO
VCC3P3 VCC1P8
VCC3P3 VCC2P5
VCC3P3
GPIO_VCCIO
VCC3P3
HSMC_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V B
DE2-115 Main Board
B
27 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V B
DE2-115 Main Board
B
27 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V B
DE2-115 Main Board
B
27 27Friday, September 24, 2010
R153 1K
C63
0.1u
C68
10u
MH7
R151 4.99K
R421K
R17710K
R152 2.2K
C67
0.1u
5V
R49
4.99K
MH5
R4034K
MH8
C76
10u
GND2
R156 1K
C69
0.1u
R4111.8K
MH2 MH1
JP6
HEADER 2X4
1 23 45 67 8
REG5
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
R544.99K
MH6
C296
100u
R17910K
FID7
R167
68.1KREG6
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
R17610K
C64
10u
MH4
FID10
C52
100u
R534.99K
R155 2.2K
MH3
C55
10u
REG7
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
R51
2.2K
FID6
C75
10u
C65
0.1u
REG4
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
HSMC_VCCIO
FID5
JP7
HEADER 2X4
1 23 45 67 8
C56
0.1u
GND3
FID2
C177
22n
C78
10u
GPIO_VCCIO
FID1
2V5
C77
10u
1V8
FID4
R504.99K
FID3
C62
10u
REG1
LMZ12003 TZ-ADJ
VIN1
RON2
EN3
GN
D4
SS5
FB6
VOUT7
EP
8
C66
10u
R435.23K
R17810K
GND1
FID9
R154 4.99K
FID8
C178
10n
R524.99K
