ALTDLL and ALTDQ DQS Megafunctions User Guide

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ALTDLL and ALTDQ_DQSMegafunctions User Guide

Software Version: 8.0Document Version: 1.0Document Date: July 2008

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Contents

Chapter 1. About these MegafunctionsDevice Family Support ......................................................................................................................... 1–1Introduction ............................................................................................................................................ 1–1How to Use the User Guide ................................................................................................................. 1–2Dedicated I/O Circuitry for External Memory Interfaces ............................................................... 1–3Internal Structure of ALTDLL and ALTDQ_DQS Megafunctions ................................................ 1–5

Overview of Megafunction Structure ............................................................................................ 1–5ALTDLL Features ............................................................................................................................. 1–6ALTDQ_DQS Features .................................................................................................................... 1–9ALTDQ_DQS–ALTIOBUF Connectivity .................................................................................... 1–10Configuring the DQS Input .......................................................................................................... 1–13Configuring the DQS Output Path .............................................................................................. 1–26Configuring the DQS OE Path ..................................................................................................... 1–33Configuring the DQ/DQS OCT Path .......................................................................................... 1–39Configuring the DQ Input Path ................................................................................................... 1–44Configuring the DQ Output Path ................................................................................................ 1–51Configuring the DQ OE Path ........................................................................................................ 1–53Configuring the DQSn I/O Pin .................................................................................................... 1–55Configuring the DQS_CONFIG / IO_CONFIG Block .............................................................. 1–56

Delay Chains For External Memory Interfaces ............................................................................... 1–56Examples of Custom External Memory Interface Data Paths ....................................................... 1–60

DDR/DDR2-SDRAM Full-Rate Interface ................................................................................... 1–60DDR/DDR2-SDRAM Half-Rate Interface .................................................................................. 1–62RLDRAMII/QDRII Half-Rate Interface ...................................................................................... 1–64General Ports and Parameters for the DDR, QDR, and RLDRAM Interfaces ....................... 1–65

Timing Analysis ................................................................................................................................... 1–69Common Applications for the ALTDLL Megafunction ................................................................ 1–69Common Applications for the ALTDQ_DQS Megafunction ........................................................ 1–70Resource Usage and Performance ..................................................................................................... 1–71

Chapter 2. Getting StartedSystem Requirements ............................................................................................................................ 2–1MegaWizard Plug-In Manager Page Description for the ALTDLL Megafunction ..................... 2–1Clear-Box Generator Customization for the ALTDQ_DQS Megafunction ................................. 2–11Clear-Box Generator Options for ALTDQ_DQS Megafunction ................................................... 2–12Instantiating Megafunctions in HDL Code or Schematic Designs ............................................... 2–13

Generating a Netlist for EDA Tool Use ....................................................................................... 2–14Using the Port and Parameter Definitions .................................................................................. 2–14

Identifying a Megafunction after Compilation ............................................................................... 2–15Simulation ............................................................................................................................................. 2–15

Quartus II Simulation .................................................................................................................... 2–15

Confidential—Internal Use Only iiiALTDLL and ALTDQ_DQS Megafunctions User Guide

Contents

EDA Tool Simulation ..................................................................................................................... 2–16Design Example: Using DLL and DQ/DQS Circuitry in Stratix III Devices .............................. 2–16

Design Files ..................................................................................................................................... 2–16Procedure ......................................................................................................................................... 2–16Functional Simulation in the ModelSim-Altera Simulator ...................................................... 2–21

Conclusion ............................................................................................................................................ 2–34

Chapter 3. SpecificationsPorts and Parameters ............................................................................................................................ 3–1ALTDLL Megafunction ........................................................................................................................ 3–1ALTDQ_DQS Megafunction ................................................................................................................ 3–6

Additional InformationRevision History ............................................................................................................................... Info–1Referenced Documents .................................................................................................................... Info–1How to Contact Altera ..................................................................................................................... Info–1Typographic Conventions ............................................................................................................... Info–2

iv Confidential—Internal Use Only Altera CorporationALTDLL and ALTDQ_DQS Megafunctions User Guide

Altera Corporation Confidential—IJuly 2008

Chapter 1. About theseMegafunctions

Device Family Support

The ALTDLL and ALTDQ_DQS megafunctions support the following Altera® device families:

■ Stratix® IV■ Stratix III

Introduction As design complexities increase, the use of vendor-specific intellectual property (IP) blocks has become a common design methodology. Altera provides parameterizable megafunctions that are optimized for Altera device architectures. Using megafunctions instead of coding your own logic saves valuable design time. Additionally, the Altera-provided functions may offer more efficient logic synthesis and device implementation.

Stratix III and Stratix IV devices have complex dedicated I/O circuitries that are primarily designed for supporting memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards such as the DDR/DDR 2 SDRAM, DDR3 SDRAM, and QDR II+/QDR II SRAM (in burst length of 4) interfaces. Altera recommends that you use the ALTMEMPHY megafunction whenever possible because the megafunction allows you to benefit from the Altera intellectual property (IP) and timing closure methodologies. However, the ALTMEMPHY megafunction does not support memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2), and other proprietary standards. For these standards, you must use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build your own custom interface.

With the ALTDLL and ALTDQ_DQS megafunctions, you can design for a broader range of memory interfaces in Stratix III and Stratix IV devices. These megafunctions support the memory standards that are not supported by the ALTMEMPHY megafunction.

The target users for the ALTDLL and ALTDQ_DQS megafunctions include the following:

■ Users who cannot use the ALTMEMPHY-megafunction-based versions of the supported memory interfaces because of a mismatch in features (for example, a lower latency is required.)

nternal Use Only 1–1ALTDLL and ALTDQ_DQS Megafunctions User Guide

How to Use the User Guide

■ Users who need to create a memory interface not supported by Altera such as Mobile DDR.

This user guide discusses the following:

■ General features of the ALTDLL megafunction and the ALTDQ_DQS megafunction

■ How you can access the features of the megafunctions with the MegaWizard® Plug-In Manager (for the ALTDLL megafunction) or the Clear-Box Generator (for the ALTDQ_DQS megafunction)

■ Ports and parameters of the ALTDLL and ALTDQ_DQS megafunctions

How to Use the User Guide

This section provides the guidelines for designing with the ALTDLL and ALTDQ_DQS megafunctions.

1 You must use an ALTIOBUF variation to connect an ALTDQ_DQS variation to the FPGA pins for accessing I/O features such as on-chip termination (OCT) and differential capabilities. For more details about the ALTIOBUF megafunction, refer to the I/O Buffer (ALTIOBIF) Megafunction User Guide.

Before designing with these megafunctions, you must understand the features of the external memory interface that Stratix III and Stratix IV devices provide by referring to the following sections:

■ To understand the hardware requirements of the dedicated I/O circuitry for custom memory interfaces, refer to “Dedicated I/O Circuitry for External Memory Interfaces” on page 1–3.

■ For more details about dedicated I/O circuitry, refer to the External Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook and the External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.

After you are familiar with the dedicated I/O circuitry, you must analyze the software components (the ALTDLL and ALTDQ_DQS megafunctions and their related sub-blocks) that correlate with the hardware components of the dedicated I/O circuitry. This includes knowing how the ALTDLL and ALTDQ_DQS megafunctions work in the dedicated circuitry, how to use the hardware components from the megafunctions, how to connect I/O buffers with the megafunctions, and how to configure specific data paths in the megafunctions. For details about how to use the megafunctions, refer to “Internal Structure of ALTDLL and ALTDQ_DQS Megafunctions” on page 1–5.

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About these Megafunctions

Next, you must know how to use the delay elements in the ALTDLL and ALTDQ_DQS megafunctions to get better timing margins for the custom external memory interfaces by referring to “Delay Chains For External Memory Interfaces” on page 1–56.

The preceding sections provide the necessary information for you to implement custom external memory-interface data paths. For implementation examples in DDR2 SDRAM, QDR II SRAM, and RLDRAM II interfaces, refer to “Examples of Custom External Memory Interface Data Paths” on page 1–60.

The following sections provide information on the ALTDLL and ALTDQ_DQS megafunctions:

■ For details about how to use the ALTDLL megafunction, refer to “MegaWizard Plug-In Manager Page Description for the ALTDLL Megafunction” on page 2–1.

■ For details about how to use the ALTDQ_DQS megafunction, refer to “Clear-Box Generator Options for ALTDQ_DQS Megafunction” on page 2–12.

■ For details about the available ports and parameters for these megafunctions, refer to Chapter 3, Specifications.

■ For timing analysis on custom external memory interfaces, refer to “Timing Analysis” on page 1–69.

Dedicated I/O Circuitry for External Memory Interfaces

Stratix III and Stratix IV devices have dedicated circuitry to support custom external memory interfaces. Figure 1–1 shows an overview of the external memory interface data path.

Altera Corporation Confidential—Internal Use Only 1–3July 2008 ALTDLL and ALTDQ_DQS Megafunctions User Guide

Dedicated I/O Circuitry for External Memory Interfaces

Figure 1–1. External Memory Interface Data Path Overview Note (1), (2)

Notes to Figure 1–1:(1) You can bypass each register block.(2) The blocks for each memory interface may differ slightly.(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the

signal is active during both read and write operations.

You can use the ALTDLL megafunction to configure the DLL block, and the ALTDQ_DQS megafunction to configure DQS logic blocks, half-data rate register blocks, alignment and synchronization register blocks, and double-data rate (DDR) register blocks, as shown in Figure 1–1. The external memory interface data path supports full-rate and half-rate capabilities, as shown in Figure 1–2.

DDR OutputRegisters

MemoryStratix III / Stratix IV FPGA

DLL

DDR Input Registers

Alignment & Synchronization

Registers

Half Data Rate Output Registers

Clock Management & Reset

4n 2nn

n

2n4n

DPRAM(2)

DQ (Read) (3)

DQ (Write) (3)

DQS Logic Block

DQS (Read) (3)

Half Data Rate Input Registers

2n

DDR OutputRegisters


4 2 DQS (Write) (3)

Resynchronization Clock

Alignment Clock

DQS Write Clock

Half-

Rate

Re

sync

hron

izatio

n Cl

ock

Half-Rate Clock

AlignmentRegisters

AlignmentRegisters

2n

2

DQ Write Clock

DQS EnableCircuit

Postamble Enable

Postamble Clock

Postamble Control Circuit



Figure 1–2. Full-Rate and Half-Rate Capabilities Supported by External Memory Interfaces

Table 1–1 describes the terms used in Figure 1–2.

Internal Structure of ALTDLL and ALTDQ_DQS Megafunctions

Overview of Megafunction Structure

Figure 1–3 shows the connections of the ALTDLL and ALTDQ_DQS megafunctions in a dedicated I/O circuitry for external memory interfaces. It also shows the external memory interface data paths that the megafunctions control.

8 16DDRto SDR User

Logic

FPGA

8 16DDRto SDR User

Logic

FPGA

Full Rate Half Rate

SDR to HDR

32

Mem

ory

Mem

ory

DDR SDRDDR200 MHz

SDR200 MHz 200 MHz 100 MHz200 MHz

HDR

Table 1–1. Description of Terms Used in Figure 1–2

Term Description

Full-rate clock Clock with a frequency that equals the frequency of thememory interface clock.

Half-rate clock Clock with a frequency that equals half the frequency of the memory interface clock.

DDR (double-data rate) Data that changes on both edges of a clock/strobe operating at the full-rate clock frequency.

SDR (single-data rate) Data that changes on one edge of a full-rate clock frequency (twice the width of the DDR data).

HDR (half-data rate) Data that changes on one edge of a half-rate clock (twice the width of the SDR data and four times the width of the DDR data).



1 You must use an ALTIOBUF variation to connect an ALTDQ_DQS variation to the FPGA pins for accessing I/O features such as on-chip termination (OCT) and differential capabilities. For more details about the ALTIOBUF megafunction, refer to the I/O Buffer (ALTIOBIF) Megafunction User Guide.

Figure 1–3. How the ALTDLL and ALTDQ_DQS Megafunctions Connect in a Dedicated I/O Circuitry Note (1)

Note to Figure 1–3:(1) The ALTDLL megafunction controls the red block and the ALTDQ_DQS megafunction controls the blue blocks.

ALTDLL Features

Stratix III and Stratix IV devices have delay-locked loop (DLL) blocks. Associated with each DLL are two phase-offset control blocks—one for each edge adjacent to the DLL, which resides in the corner of the device.

The ALTDLL megafunction controls the delay-chain settings to achieve a compensated delay for PVT (process, voltage, and temperature). For example, a DQS read strobe/clock that is edge-aligned to its associated read data can be used to clock the data into I/O registers if the data is delayed before reaching the register.

DDR OutputRegisters

MemoryStratix III / Stratix IV FPGA

DLL

DDR Input Registers

Alignment & Synchronization

Registers


Clock Management & Reset

4n 2nn

n

2n4n

DPRAM(2)

DQ (Read) (3)

DQ (Write) (3)

DQS Logic Block

DQS (Read) (3)


2n

DDR OutputRegisters


4 2 DQS (Write) (3)

Resynchronization Clock

Alignment Clock

DQS Write Clock

Hal

f-Rat

e R

esyn

chro

niza

tion

Clo

ck

Half-Rate Clock

AlignmentRegisters

AlignmentRegisters

2n

2

DQ Write Clock

DLL

DQS EnableCircuit

Postamble Enable

Postamble Clock


DDR InputRegisters

Alignment &Synchronization

Registers

2n


2n

DDR OutputRegisters


2n

AlignmentRegisters

2n

DQ Output Path

DDR OutputRegisters


2AlignmentRegisters

2

DQS Output Path

DQ Input Path

DQS EnableCircuit


DQS LogicBlock

DQS Input Path

ALTDLL





The DLL block computes the necessary delay settings by comparing the period of an input reference clock to the delay through an internal delay chain. The DLL offset control block can then be used to fine-tune the delay setting with an offset.

The ALTDLL megafunction controls the DLL and its two associated phase-offset control blocks by making the appropriate connections between the DLL and the phase-offset control blocks.

Figure 1–4 shows the components of the ALTDLL megafunction. The DLL_OFFSET_CTRL_A block is the first phase-offset control block, and the DLL_OFFSET_CTRL_B block is the second phase-offset control block. When connected together, these blocks form the ALTDLL megafunction. Each offset control block can only control the DQS delay chains on one edge of the device. To feed the same offset to the DQS delay chains on two edges, you must use both phase-offset controls.

Figure 1–4. Components of the ALTDLL Megafunction

The names DLL_OFFSET_CTRL_A and DLL_OFFSET_CTRL_B are logical and do not denote the placement of the actual phase-offset blocks. With location assignments, you can assign these blocks to the top, bottom, or side of the FPGA, depending on which DLL your design uses. If location assignments are not used, these blocks can be located at the top, bottom, or side of the FPGA device, depending on how the Quartus® II Fitter places it.

DLL

DLL

_OFF

SET_

CTR

L_A

DLL

_OFF

SET_

CTR

L_B

offsetdelayctrlin

clk

aload

aload

clk

offsetdelayctrlin

offsetdelayctrlclkout

offsetdelayctrlout

delayctrlout

dqsupdate

clk

aload

offsetdll_offset_ctrl_a_offset

addnsubdll_offset_ctrl_a_addnsuboffsetctrlout

offsetctrlout

offsetdll_offset_ctrl_b_offset

addnsubdll_offset_ctrl_b_addnsub

dll_clk

dll_aload

dll_offset_ctrl_a_offsetctrlout

dll_delayctrlout

dll_dqsupdate

dll_offset_ctrl_b_offsetctrlout

ALTDLL



The following ports are Gray-coded:

■ dll_offset_ctrl_a_offset■ dll_offset_ctrl_b_offset ■ dll_offset_ctrl_a_offsetctrlout■ dll_offset_ctrl_b_offsetctrlout■ dll_delayctrlout

1 The values at these ports are Gray-coded to minimize jitter caused by toggling.

f For more details about the dedicated circuitry of this block, refer to the following documents:

■ External Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook

■ External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook

Figure 1–5 shows an example implementation of these blocks in Stratix III devices. Figure 1–5 also shows the actual DLL circuitry and its phase-offset control blocks in the device.





Figure 1–5. Simplified Diagram of the DQS Phase-Shift Circuitry Note (1)

Notes to Figure 1–5:(1) All features of the DQS phase-shift circuitry are accessible from the ALTDLL and ALTDQ_DQS megafunctions in

the Quartus II software.(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin.(3) Phase-offset settings can only go to the DQS logic blocks.(4) DQS delay settings can go to the logic array, the DQS logic block, and the leveling circuitry.

ALTDQ_DQS Features

A typical memory interface consists of the following:

■ Zero or one DQS I/O pin (read or write strobe/clock) with an optional DQSn I/O pin (differential strobe/clock), or a CQ/CQn I/O pair (complementary clock)

■ One or more DQ I/O pins (read or write data)■ Zero or one DM/D pin (output-only data mask and/or write data)■ Zero or one QVLD/Q pin (input-only data)

The ALTDQ_DQS megafunction allows you to instantiate a group of DQ pins (ranging from x4 to x36) along with their corresponding DQS block and/or DQSn block, which is optional. The ALTDQ_DQS megafunction enables you to generate the necessary DQ/DQS circuitry to use with external memory interfaces.

6

6

6

PhaseOffsetControl

6

Phase-offset settingsfrom the logic array

Phase-offsetsettings to DQS pinson top or bottom edge (3)

DQS DelaySettings (4)

Input ReferenceClock (2) upndn

clock enable

DLL

6

addnsub_a

PhaseComparator

Delay Chains

Up/DownCounter

6

PhaseOffsetControl

Phase-offset settingsfrom the logic array

Phase-offsetsettings to DQS pin on left or right edge (3)

6

addnsub_b



The DQS and DQSn I/O pins can be configured as input-only, output-only, or bidirectional.

All the BIDIR_DQ I/O pins are configured identically. All the OUTPUT_DQ I/O pins (output-only DQ/DM I/O pins) and all the INPUT_DQ I/O pins (input-only DQ/QVLD I/O pins) are also configured identically, which means that if delay chains or half-data rate blocks are used in a path, the configuration applies to all paths of the same type. The paths can be all-input paths, all-output paths, or all-bidirectional paths in the ALTDQ_DQS variation.

For example, if there are 8-bit DQ output-only pins that use half-rate blocks and have both the output delay chains enabled, the ALTDQ_DQS instance has to configure all the eight output DQ paths using half-rate blocks with both output delay chains enabled. You cannot vary the settings for a path—all settings are applied identically to a path for an ALTDQ_DQS instance.

1 The ALTDQ_DQS megafunction generates only one DQS I/O pin per instantiation. If you need a 72-bit data interface composed of x9 data groups, you must generate a x9 data group with the megafunction and then instantiate it eight times.

1 For more details about the ports and parameters, refer to Chapter 3, Specifications.

ALTDQ_DQS–ALTIOBUF Connectivity

In the ALTDQ_DQS megafunction, you must externally configure the IO_IBUF (input buffer block), IO_OBUF (output buffer block), and PSEUDO_DIFF_OUT (differential output buffer block) using the ALTIOBUF megafunction.

The ALTIOBUF megafunction can configure the dynamic delay chains (D1, D5, and D6) on the output, output-enable (oe), and input paths that are controlled by an IO_CONFIG block. The IO_CONFIG block is a shift register to change the delay settings in the I/O buffer. It cannot configure the dynamic delay chains (D2, D3_0, D3_1, D4, D5 OCT, and D6 OCT) on the OCT path or on the DQS input path that are controlled by a DQS_CONFIG block. The DQS_CONFIG block is a shift register to change the delay settings in the I/O buffer; it is used for only DQS pins. The DQS_CONFIG block also controls other blocks in the ALTDQ_DQS megafunction and shares signals with the IO_CONFIG block. The IO_CONFIG block and DQS_CONFIG blocks are delay configuration blocks for normal I/O pins and DQ/DQS I/O pins, respectively.



c When used together with the ALTDQ_DQS megafunction, the ALTIOBUF megafunction cannot be used to configure any dynamic delay chains. The ALTIOBUF megafunction can only be used to configure the I/O buffers to avoid any conflict with the dynamic configuration and delay chain circuitry that are encapsulated in the ALTDQ_DQS megafunction. The configuration circuitry encapsulated in the ALTDQ_DQS megafunction provides extended dynamic control over more circuit elements than the ALTIOBUF megafunction.

Figures 1–6 to 1–11 show the various configurations for the ALTDQ_DQS megafunction when used together with the ALTIOBUF megafunction. These configurations apply to both the DQ and DQS I/O pins. The usage of the datain and datout signals in these figures is generic—it can represent both data or clock/strobe in external memory interfaces.

Figure 1–6. Input Only—Single-Ended

Figure 1–7. Input Only—Differential

ALTIOBUF

IO_PAD ALTDQ_DQSdatain dataout

IO_IBUF

ALTIOBUF

IO_PADdatain

dataout

datain_nIO_PAD

IO_IBUF ALTDQ_DQS



Figure 1–8. Output Only—Single-Ended

Note to Figure 1–8:(1) The oe port is optional.

Figure 1–9. Output Only—Differential

Note to Figure 1–9:(1) The oe_p and oe_n ports are optional.

ALTIOBUF

oe(1)

dataoutALTDQ_DQS

datainIO_OBUF IO_PAD

ALTIOBUF

oe_p(1)

oe_n(1)

dataout

ALTDQ_DQSdatain

IO_PAD

dataout_nIO_PADIO_OBUF

IO_OBUF

PSEUDO_DIFF_OUT



Figure 1–10. Bidir—Single-Ended

Note to Figure 1–10:(1) The dyn_term_ctrl port is optional.

Figure 1–11. Bidir—Differential

Note to Figure 1–11:(1) The dyn_term_ctrl_p and dyn_term_ctrl_n ports are optional.

Configuring the DQS Input

Figure 1–12 shows the different blocks in the DQS input path that can be configured. To instantiate this path, use the following parameters:

■ use_dqs=TRUE■ use_dqs_input_path=TRUE

ALTIOBUF

dyn_term_ctrl(1)

dataout

dataio

ALTDQ_DQS

oe

datain

IO_PAD

IO_IBUF

IO_OBUF

ALTIOBUF

dyn_term_ctrl_p(1)

dataout

dataio

datain

dyn_term_ctrl_n(1)

oe_n

IO_OBUF

PSEUDO_DIFF_OUT

oe_p IO_PAD

dataioIO_PAD

IO_IBUF

IO_OBUF

ALTDQ_DQS



1 The DQS_IBUF block is configured with the ALTIOBUF megafunction.

Figure 1–12. DQS Input Path Blocks

Notes to Figure 1–12:(1) The DQS_IBUF block is not part of the ALTDQ_DQS megafunction. Use the ALTIOBUF megafunction to generate

this block.(2) The input is fed to DQS_INPUT_DELAY_CHAIN (D1) as the dqs_input_data_in signal.(3) Output generated at the dqs_input_data_out port.(4) Output generated at the dqs_bus_out port.(5) Input from FPGA core.

Figure 1–13 shows the valid configurations for the DQS input path and the possible connections between the blocks (shown in Figure 1–12) in this path. This path is between the DQS input buffer and the FPGA core. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.

f For more details about the blocks shown in Figure 1–12, refer to the relevant subsections in this section.

DQS_CONFIG IO_CLOCK_DIVIDER

DQS_IBUF(1) DQS_INPUT_DELAY_CHAIN (D1)

DQS_DELAY_CHAIN DQSBUSOUT_DELAY_CHAIN DQS_ENABLE

DQSENABLE_DELAY_CHAIN

DQS_ENABLE_CTRL

DQS_ENABLE_CTRL_HR_DDIO_OUT

(2) (3)

(4)

(5)



Figure 1–13. Valid Configurations for DQS Input Path Note (1)

Note to Figure 1–13:(1) For each configuration, the far-left arrow indicates the DQS input buffer and the far-right arrow indicates the FPGA

core.

DQS_DELAY_CHAIN

DQS_DELAY_CHAIN DQSBUSOUT_DELAY_CHAIN

DQS_DELAY_CHAIN DQS_ENABLEDQSBUSOUT_DELAY_CHAIN

DQS_DELAY_CHAIN DQS_ENABLE

DQS_ENABLE_CTRL

DQSBUSOUT_DELAY_CHAIN





DQS_ENABLE_CTRL HR_DDIO_OUT



DQS_ENABLE_CTRL HR_DDIO_OUT

HR_DDIO_OUT


DQS_ENABLE_CTRL


DQS_ENABLE_CTRL

HR_DDIO_OUT


DQS_ENABLE_CTRL




DQS_ENABLE_CTRL




DQS_ENABLE_CTRL



In every configuration, the DQS_IBUF logic, DQS_INPUT_DELAY_CHAIN (D1) block, or both can be directly fed to the core logic. By doing this, you can clock the core registers to avoid any hold-time violations during data transfer from the DDIO input registers (clocked by the delayed DQS pin) to the core registers.

DQS_DELAY_CHAIN

Figure 1–15 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_DELAY_CHAIN block. The DQS delay chain represents the DLL-controlled delay chain used to phase-shift the DQS read clock. Each DQS pin contains a DQS delay chain.

To instantiate this block, use the following parameter:

■ use_dqs_delay_chain=TRUE

If use_dqs_delay_chain=FALSE, all subsequent blocks are ignored and the dqs_input_data_in signal is directly connected to the dqs_input_data_out signal, if the output port is specified.

f For more details about the implementation of this block, refer to the following documents:



Figure 1–14 shows an example implementation of the delay chain in Stratix III devices and Figure 1–15 shows the DQS_DELAY_CHAIN connectivity.





Figure 1–14. DQS Logic Block in Stratix III Devices

Notes to Figure 1–14:(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin.(2) The dqsenable signal can also come from the Stratix III FPGA fabric.

D QD Q

Update-Enable Circuitry

66

66

6 6

DQS delaysettings from DQS phase-shift circuitry

DQS orCQn Pin

Input ReferenceClock (1)

DQS Delay Chain

Bypass

Phase-offsetsettings from

DQS phase-shift circuitry

6

6

DQS Enable

gated_dqs control

DQS bus

PRN

CLR

Q

DFF

reset

AB VCC

DQS'

D

PostambleEnable

ResynchronizationClock

PostambleClock

dqsenable (2)

D

D D

Q

Q Q



Figure 1–15. DQS_DELAY_CHAIN Connectivity

Notes to Figure 1–15:(1) This input is from the ALTIOBUF IO_IBUF output of the DQS pin.(2) This input is from the dll_delayctrlout signal of the ALTDLL megafunction or core logic.(3) This input is from the dll_offset_ctrl_a_offsetctrlout or dll_offset_ctrl_b_offsetctrlout

signal of the ALTDLL megafunction.(4) This input is from the dll_dqsupdate signal of the ALTDLL megafunction.

DQS_ENABLE

Figure 1–16 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_ENABLE block. The DQS_ENABLE block represents the AND-gate control on the DQS input signal that is used to ground the DQS input strobe after a DDR read postamble. Each DQS pin contains a DQS_ENABLE block.




The DQS_ENABLE block can be bypassed. To instantiate this block, use the following parameter:

■ use_dqs_enable=TRUE

dqsbusout datain

delayctrlin

dataout dqsin

datain dataout

dqsin

delayctrlin

dll_delayctrlin /core_delayctrlin (2)

offsetctrlinoffsetctrlin (3)

dqsupdateendqsupdateen (4)

phasectrlin

dqs_input_data_inDQS_IBUF_ALTIOBUF (1)

dqs_input_data_out

dqs_bus_out

dqsinputphasesetting

dqsbusoutdelaysetting

DQS_INPUT_DELAY_CHAIN (D1)

DQ

S_D

ELAY

_CH

AIN

DQS_CONFIG

DQ

SBU

SOU

T_D

ELAY

_CH

AIN

DQS_ENABLE

IO_CLOCK_DIVIDER

DQ_DDIO_IN

clk / clkn

clk / clkn





If use_dqs_enable=FALSE, the DQSENABLE_DELAY_CHAIN, DQS_ENABLE_CTRL, and DQS_ENABLE_CTRL_HR_DDIO_OUT blocks are not instantiated.

Figure 1–16. DQS_ENABLE Connectivity

DQS_ENABLE_CTRL

The DQS_ENABLE_CTRL block represents the circuitry used to control the DQS_ENABLE circuit. Each DQS_ENABLE block is controlled by a DQS_ENABLE_CTRL block.




Figure 1–17 shows an example implementation of the block in Stratix III devices. Figure 1–18 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_ENABLE_CTRL block.

dqssin

dqs_enable_in dqsenable dqs_bus_outdqsbusout

DQS_DELAY_CHAIN: dqsbusout /DQSBUSOUT_DELAY_CHAIN: dataout

DQ_DDIO_INclk / clkn

DQS_ENABLE_CTRL: dqsenableout /DQSENABLE_DELAY_CHAIN: dataout

DQ

S_E

NA

BLE





Figure 1–17. DQS Postamble Circuitry in Stratix III Devices Note (1)

Notes to Figure 1–17:(1) The postamble clock can come from any of the delayed resynchronization clock taps although it is not necessarily

of the same phase as the resynchronization clock.(2) The dqsenable signal can also come from the Stratix III FPGA fabric.

The DQS_ENABLE_CTRL block can be bypassed. To instantiate this block, use the following parameter:

■ use_dqs_enable_ctrl=TRUE

If use_dqs_enable_ctrl=FALSE, the DQS_ENABLE_CTRL_HR_DDIO_OUT and DQSENABLE_DELAY_CHAIN blocks are not instantiated.

DQS Enable

gated_dqs control

DQS Bus

PRN

CLR

Q

DFF

reset

AB VCC

DQS'

D

PostambleEnable

ResynchronizationClock

PostambleClock

D

D D

Q

Q Qdqsenable (2)



Figure 1–18. DQS_ENABLE_CTRL Connectivity

DQSBUSOUT_DELAY_CHAIN / DQSENABLE_DELAY_CHAIN

There are two dynamically configurable, but not PVT-compensated, delay chains on the DQS input path: DQSBUSOUT_DELAY_CHAIN and DQSENABLE_DELAY_CHAIN. These delay chains represent run-time adjustable delay chains. The delay-chain settings are controlled by the DQS_CONFIG outputs. Each DQS block contains a delay chain after the dqsbusout output signal. Each DQS_ENABLE block contains a delay chain before the dqsenable input signal.

Both delay chains can be bypassed. To instantiate these blocks, use the following parameters:

■ use_dqsbusout_delay_chain=TRUE■ use_dqsenable_delay_chain=TRUE

Refer to Figures 1–15, 1–16, and 1–18 to see how the datain and dataout ports of the delay chains are connected.

To dynamically configure the delay through the DQSBUSOUT_DELAY_CHAIN block, connect the delayctrlin port of DQSBUSOUT_DELAY_CHAIN to the dqsbusoutdelaysetting output from the DQS_CONFIG block.

dataout

dqsenableindqs_enable_ctrl_in

clkdqs_enable_ctrl_clk

delayctrlindll_delayctrlin

phasectrlin

phaseinvertctrl

enaphasetransferreg

dqsenablectrlphasesetting

dqsenablectrlphaseinvert

enadqsenablephasetransferreg

DQ

S_EN

ABLE

_CTR

L

DQ

S_C

ON

FIG


dqsenableout

DQS_ENABLE:dqsenable /DQSENABLE_DELAY_CHAIN:datain



To dynamically configure the delay with the DQSENABLE_DELAY_CHAIN block, connect the delayctrlin port of DQSENABLE_DELAY_CHAIN to the dqsenabledelaysetting output from the DQS_CONFIG block.

DQS_INPUT_DELAY_CHAIN (D1)

The DQS_INPUT_DELAY_CHAIN (D1) block is a dynamically configurable, but not PVT-compensated, delay chain on the DQS input path that directly feeds the core logic. This delay chain represents the run-time adjustable delay chain. The delay-chain setting is controlled by the IO_CONFIG output. Every I/O pin contains one delay chain between the input buffer and input register.

The DQS_INPUT_DELAY_CHAIN (D1) block can be bypassed. To instantiate this block, use the following parameter:

■ use_dqs_input_delay_chain=TRUE

Refer to Figure 1–15 to see how the datain and dataout ports of the delay-chain are connected.

To dynamically configure the delay through the DQS_INPUT_DELAY_CHAIN (D1) block, connect the delayctrlin port of DQS_INPUT_DELAY_CHAIN (D1) block to the padtoinputregisterdelaysetting output from the IO_CONFIG block of the DQS pin.


Figure 1–19 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_ENABLE_CTRL_HR_DDIO_OUT block. This block is used to transfer input to the DQS_ENABLE_CTRL block from a half-rate clock to a full-rate clock.

The DQS_ENABLE_CTRL_HR_DDIO_OUT block can be bypassed. To instantiate this block, use the following parameters:

■ use_half_rate=TRUE■ use_dqs_enable_ctrl=TRUE



Figure 1–19. DQS_ENABLE_CTRL_HR_DDIO_OUT Connectivity

IO_CLOCK_DIVIDER

Figure 1–20 shows the connectivity in the ALTDQ_DQS megafunction for the IO_CLOCK_DIVIDER block. The IO_CLOCK_DIVIDER represents a divide-by-two clock divider for transferring data to the core at half the speed of the I/O clock. Each divider can feed up to six pins (a x4 DQS group) in the device. To feed wider DQS groups, multiple clock dividers are chained together by feeding the slaveout output of one divider to the masterin input of the neighboring pin divider with use_masterin=true.

Figure 1–20. IO_CLOCK_DIVIDER Connectivity

datainhidqs_enable_ctrl_hr_datainhi

datainlodqs_enable_ctrl_hr_datainlo

clkhiIO_CLOCK_DIVIDER: clkout

clklo

muxsel

DQ

S_EN

ABLE

_CTR

L_H

R_D

DIO

_OU

T

dataout

DQS_ENABLE_CTRL: dqsenablein

dqsbusout

clk

clk

io_clock_divider_clk

masterinio_clock_divider_masterin IO_CLOCK_DIVIDER: slaveout


phaseselect

phasectrlin

phaseinvertctrl

dividerphasesetting

resyncinputphasesetting

resyncinputphaseinvert

DQ

S_C

ON

FIG

slaveout

clkout

IO_CLOCK_DIVIDER: masterin

DQS_DELAY_CHAIN DQHALF_RATE_INPUT

io_clock_divider_clkout

io_clock_divider_slaveout

IO_C

LOC

K_D

IVID

ER






Figure 1–21 shows an example implementation of the block in Stratix III and Stratix IV devices.




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DL

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QS

Meg

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s

al clock line.

the I/O clock divider can also be fed

DFF

D Q

DFF

D Q

gisters

To Core (rdata0) (7)

To Core (rdata1)

(7)

To Core (rdata2) (7)

To Core (rdata3)

(7)

to core (7)

tion Clock (resync_clk_1x)

0

1

dataoutbypass(8)

0

1

Figure 1–21. IOE Input Registers in Stratix III and Stratix IV Devices Note (1)

Notes to Figure 1–21:(1) You can bypass each register block in this path.(2) This is a 0-phase resynchronization clock (from the read-leveling delay chain).(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a glob(4) This input clock comes from the CQn logic block.(5) This resynchronization clock can come either from the PLL or from the read-leveling delay chain.(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock,

by the DQS bus or CQn bus.(7) The half-rate data and clock signals feed into the FPGA core.(8) You can dynamically change the dataoutbypass signal after configuration.

DFF

I

DFF

Input Reg A

Input Reg B

neg_reg_out

I

D Q

D Q

0

1

DQS (3)

CQn (4)

DQ

Input Reg CI

DFF

D Q

DFF

DFF

D Q

D Q

DFF

DFF

D Q

D Q

Resynchronization Clock(resync_clk_2x)(5)

Alignment & Synchronization Registers

Double Data Rate Input Registers

Half Data Rate Re

Half-Rate Resynchroniza

I/O Clock Divider (6)

(2)

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DQSn

DifferentialInput Buffer

0..7



■ use_half_rate=TRUE

The ALTDQ_DQS megafunction instantiates one IO_CLOCK_DIVIDER block per x6 group of I/O pins (one DQS, one DQSn, and up to six DQ I/O pins). To synchronize the output phase shift of the io_clock_divider_clkout output between multiple I/O clock dividers, connect the slaveout and masterin ports on the IO_CLOCK_DIVIDER block according to the position in the chain.

1 The IO_CLOCK_DIVIDER blocks in an ALTDQ_DQS instance are chained. You can also chain IO_CLOCK_DIVIDER blocks across instances. If the IO_CLOCK_DIVIDER blocks are chained across instances, only one of the groups has a master IO_CLOCK_DIVIDER block. If the IO_CLOCK_DIVIDER blocks are not chained across instances, each group has its own master IO_CLOCK_DIVIDER block.

For the master ALTDQ_DQS instance, the parameter use_io_clock_divider_masterin is set to FALSE.

For the first IO_CLOCK_DIVIDER instantiated by the ALTDQ_DQS megafunction, the masterin port can be fed the synchronizing signal from another ALTDQ_DQS instance through the io_clock_divider_masterin port if use_io_clock_divider_masterin=TRUE. Otherwise, it is connected to GND. For all subsequent IO_CLOCK_DIVIDER blocks, the masterin port is connected to the slaveout port of the previous block. The slaveout port of the last IO_CLOCK_DIVIDER block is connected to the io_clock_divider_slaveout port, if specified.

Configuring the DQS Output Path

Figure 1–22 shows the different blocks in the DQS output path that can be configured.

The DQS output path is optional. To instantiate this path, use the following parameters:

■ use_dqs=TRUE ■ use_dqs_output_path=TRUE

1 The DQS_OBUF block is configured using the ALTIOBUF megafunction.



Figure 1–22. DQS Output Path Blocks

Notes to Figure 1–22:(1) The DQS_OBUF block is not part of the ALTDQ_DQS megafunction. Use the ALTIOBUF megafunction to generate

this block.(2) The output of the DQS_OUTPUT_DELAY_CHAIN2 (D6) block is the dqs_output_data_out signal.(3) This is an output register block.(4) This is a half-data rate block.

Figure 1–23 shows the valid configurations for the DQS output path and the possible connections between the blocks (shown in Figure 1–22) in this path. This path is between the DQS output buffer and the FPGA core. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.


DQS_OBUF (1) DQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_DELAY_CHAIN1 (D5)

DQS_OUTPUT_HR_DDIO_OUT_HIGH (4)

DQS_OUTPUT_HR_DDIO_OUT_LOW (4)

DQS_OUTPUT_FF /DQS_OUTPUT_DDIO_OUT (3)

(2)



Figure 1–23. Valid Configurations for the DQS Output Path Note (1)

Note to Figure 1–23:(1) For each configuration, the far-left arrow indicates the DQS output buffer and the far-right arrow indicates the

FPGA core.

DQS_OUTPUT_DELAY_CHAIN1 (D5)/ DQS_OUTPUT_DELAY_CHAIN2 (D6)

There are two delay chains on the DQS Output path:

■ DQS_OUTPUT_DELAY_CHAIN1 (D5) ■ DQS_OUTPUT_DELAY_CHAIN2 (D6)

These delay chains represent the run-time adjustable, but not PVT-compensated, delay chains. The delay-chain settings can be controlled by the IO_CONFIG block. Every I/O pin contains two delay chains arranged in series between the output registers and the output buffer.

Each of these delay chain blocks can be bypassed. To instantiate these delay chains, use the following parameters:

■ use_dqs_output_delay_chain1=TRUE■ use_dqs_output_delay_chain2=TRUE

Figure 1–24 shows the port connectivity.

DQS_OUTPUT_DELAY_CHAIN1 (D5)

DQS_OUTPUT_DELAY_CHAIN2 (D6)

DQS_OUTPUT_DELAY_CHAIN1 (D5)DQS_OUTPUT_DELAY_CHAIN2 (D6)

DQS_OUTPUT_DELAY_CHAIN1 (D5)DQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_FF

DQS_OUTPUT_FFDQS_OUTPUT_DELAY_CHAIN1 (D5)

DQS_OUTPUT_FF

DQS_OUTPUT_DELAY_CHAIN1 (D5) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_DELAY_CHAIN1 (D5)DQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_HR_DDIO_OUT_HIGH/LOWDQS_OUTPUT_DELAY_CHAIN1 (D5) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_HR_DDIO_OUT_HIGH/LOW

DQS_OUTPUT_DELAY_CHAIN1 (D5)DQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_HR_DDIO_OUT_HIGH/LOWDQS_OUTPUT_DELAY_CHAIN2 (D6) DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_HR_DDIO_OUT_HIGH/LOWDQS_OUTPUT_DDIO_OUT

DQS_OUTPUT_FFDQS_OUTPUT_DELAY_CHAIN2 (D6)



Figure 1–24. DQS_OUTPUT_DELAY_CHAIN1 (D5) / DQS_OUTPUT_DELAY_CHAIN2 (D6) Connectivity

DQS_OUTPUT_FF

Figure 1–25 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OUTPUT_FF block. This block is a basic I/O register on the output path.

The DQS_OUTPUT_FF block is optional. To instantiate this block, use the following parameter:

■ dqs_output_reg_mode=FF

This block cannot be used if use_half_rate=TRUE.




dataindqs_output_data_out datain

delayctrlin delayctrlin

dataoutdataout dqs_output_data_in

outputdelaysetting2

outputdelaysetting1 IO_CONFIG

DQ

S_O

UTP

UT_

DEL

AY_C

HAI

N2

(D6)

DQS_OUTPUT_FF /DQS_OUTPUT_DDIO_OUT

DQ

S_O

UTP

UT_

DEL

AY_C

HAI

N1

(D5)





Figure 1–25. DQS_OUTPUT_FF Connectivity

Figure 1–26 shows an example implementation of the block in Stratix III and Stratix IV devices.

d

clk

clrndqs_output_data_out q

sclr

ena

dqs_output_data_in

dqs_output_reg_clk

dqs_areset

dqs_sreset

dqs_output_reg_clkenaDQ

S_O

UTP

UT_

FF

DQS_OUTPUT_DELAY_CHAIN1 (D5) / DQS_OUTPUT_DELAY_CHAIN2 (D6)


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QS

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lock have a 90° offset between them.

01

OR2

TRI

Output-Enable Registers

ata Rate Output Registers

DQ or DQS

Figure 1–26. IOE Output and Output-Enable Path Registers in Stratix III and Stratix IV Devices Note (1)

Notes to Figure 1–26:(1) You can bypass each register block of the output and output-enable paths.(2) Data coming from the FPGA core are at half the frequency of the memory interface.(3) Half-rate and alignment clocks come from the PLL.(4) These registers are used only in DDR3 SDRAM interfaces.(5) The write clock can come from either the PLL or the write-leveling delay chain. The DQ write clock and DQS write c

Alignment Registers (4)

DFF

DFF

D Q

D Q

DFF

D Q

DFF

DFF

D Q

D Q

DFF

D Q

Half Data Rate to Single Data Rate Output Registers

DFF

DFF

D Q

D Q

DFF

D Q

Half Data Rate to Single Data Rate Output-Enable Registers

Alignment Registers (4)

AlignmentClock (3)

01

0

1

01

From Core (2)

From Core (2)

From Core (wdata2) (2)




D Q

DFF

D Q

DFF

Output Reg Ao

Output Reg Bo

D Q

DFF

D Q

DFF

OE Reg BOE

OE Reg AOE

0

1

Double Data Rate

Double D

WriteClock (5)

Half-Rate Clock (3)

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q

DFF

D QDFF

D Q

DFF

D Q

DFF

D Q

DFF

D Q


DQS_OUTPUT_DDIO_OUT

Figure 1–27 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OUTPUT_DDIO_OUT block. This block is a DDIO register on the output path.




Figure 1–26 on page 1–31 shows an example implementation of the block in Stratix III devices.

The DQS_OUTPUT_DDIO_OUT block is optional. To instantiate this block, use the following parameter:

■ dqs_output_reg_mode=DDIO

Figure 1–27. DQS_OUTPUT_DDIO_OUT Connectivity

DQS_OUTPUT_HR_DDIO_OUT_HIGH / DQS_OUTPUT_HR_DDIO_OUT_LOW

Figure 1–28 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OUTPUT_HR_DDIO_OUT_HIGH / DQS_OUTPUT_HR_DDIO_OUT_LOW block. This block is used to transfer the output data signals from a half-rate clock to a full-rate clock.


datainhi

datainlo

clkhidataout

clklo

ena

muxsel

dqs_hr_output_data_in_high

dqs_hr_output_data_in_low

dqs_output_reg_clk

dqs_output_reg_clkena

areset dqs_areset

sreset dqs_sresetDQ

S_O

UTP

UT_

HR

_DD

IO_O

UT

DQS_OUTPUT_DELAY_CHAIN1 (D5)/DQS_OUTPUT_DELAY_CHAIN2 (D6)

DQS_OUTPUT_HR_DDIO_OUT_HIGH

DQS_OUTPUT_HR_DDIO_OUT_LOW

dqs_output_data_out










Figure 1–28. DQS_OUTPUT_HR_DDIO_OUT Connectivity

Configuring the DQS OE Path

Figure 1–29 shows the different blocks in the DQS OE path that can be configured.

The DQS OE path is optional. To instantiate this path, use the following parameters:

■ use_dqs=TRUE■ use_dqs_output_path=TRUE■ use_dqs_input_path=TRUE or use_dqs_oe_path=TRUE

1 The DQS_OBUF block is configured with the ALTIOBUF megafunction.

datainhi

datainlo

clkhidataout

clklo

ena

muxsel

dqs_hr_output_data_in_high

dqs_hr_output_data_in_low

dqs_output_reg_clk


areset dqs_areset

sreset dqs_sresetDQ

S_O

UTP

UT_

HR

_DD

IO_O

UT

DQS_OUTPUT_DELAY_CHAIN1 (D5)/DQS_OUTPUT_DELAY_CHAIN2 (D6)

DQS_OUTPUT_HR_DDIO_OUT_HIGH

DQS_OUTPUT_HR_DDIO_OUT_LOW

dqs_output_data_out





Figure 1–29. DQS OE Path Blocks


this block.(2) The output of the DQS_OE_DELAY_CHAIN2 (D6) block is the dqs_oe_out signal.(3) This is an output register block.(4) This is a half-data rate block.

Figure 1–30 shows the valid configurations for the DQS OE path and the possible connections between the blocks (shown in Figure 1–29) in this path. This path is between the FPGA core and the DQS output buffer. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.

f For more details about the blocks shown in Figure 1–29, refer to the relevant subsections in this section

DQS_OBUF (1)(2)

DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DELAY_CHAIN1 (D5)

DQS_OE_HR_DDIO_OUT (4)DQS_OE_FF /

DQS_OE_DDIO_OE (3)



Figure 1–30. Valid Configurations for DQS OE Path Note (1)

Note to Figure 1–30:(1) For each configuration, the far-left arrow indicates the DQS output buffer and the far-right arrow indicates the

FPGA core.

DQS_OE_DELAY_CHAIN1 (D5) / DQS_OE_DELAY_CHAIN2 (D6)

There are two delay chains on the DQS OE path: DQS_OE_DELAY_CHAIN1 (D5) and DQS_OE_DELAY_CHAIN2 (D6). These delay chains represent the run-time adjustable, but not PVT-compensated, delay chains. The delay-chain settings can be controlled by the IO_CONFIG block. Every I/O pin contains two delay chains between the output-enable port and output buffer. DQS_OE_DELAY_CHAIN1 (D5) must have the same delay setting as DQS_OUTPUT_DELAY_CHAIN1 (D5). DQS_OE_DELAY_CHAIN2 (D6) must have the same delay setting as DQS_OUTPUT_DELAY_CHAIN2 (D6).

DQS_OE_DELAY_CHAIN1 (D5)

DQS_OE_DELAY_CHAIN2 (D6)

DQS_OE_DELAY_CHAIN1 (D5)DQS_OE_DELAY_CHAIN2 (D6)

DQS_OE_DELAY_CHAIN1 (D5)DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_FF

DQS_OE_FFDQS_OE_DELAY_CHAIN1 (D5)

DQS_OE_FF

DQS_OE_DELAY_CHAIN1 (D5) DQS_OE_DDIO_OE

DQS_OE_DELAY_CHAIN1 (D5)DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DDIO_OE

DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_DELAY_CHAIN1 (D5) DQS_OE_FF

HR_DDIO_OUTDQS_OE_DELAY_CHAIN1 (D5)DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_FF

HR_DDIO_OUTDQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DDIO_OUT

DQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_DELAY_CHAIN1 (D5) DQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_DELAY_CHAIN1 (D5)DQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_DELAY_CHAIN2 (D6) DQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_DDIO_OE

HR_DDIO_OUTDQS_OE_FF

DQS_OE_FFDQS_OE_DELAY_CHAIN2 (D6)



Each of these delay chains can be bypassed. To instantiate these blocks , use the following parameters:

■ use_dqs_oe_delay_chain1=TRUE■ use_dqs_oe_delay_chain2=TRUE


Figure 1–31. DQS_OE_DELAY_CHAIN1 (D5) /DQS_OE_DELAY_CHAIN2 (D6) Connectivity

DQS_OE_FF

Figure 1–32 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OE_FF block. This block is a basic I/O register on the output-enable path.





dataindqs_oe_out dataout


dataoutdataout dqs_oe_inD

QS_

OE_

DEL

AY_C

HAI

N1

(D5)

outputdelaysetting2

outputdelaysetting1 IO_CONFIG

DQ

S_O

E_D

ELAY

_CH

AIN

2 (D

6)

DQS_OE_FF /DQS_OE_DDIO_OE





The DQS_OE_FF block is optional. To instantiate this block, use the following parameter:

■ dqs_oe_reg_mode=FF

Figure 1–32. DQS_OE_FF Connectivity

DQS_OE_DDIO_OE

Figure 1–33 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OE_DDIO_OE block. This block is a DDIO register on the output-enable path.





The DQS_OE_DDIO_OE block is optional. To instantiate this block, use the following parameter:

■ dqs_oe_reg_mode=DDIO

d

clk

clrndqs_oe_out q

sclr

ena

dqs_oe_in

dqs_output_reg_clk

dqs_areset

dqs_sreset


DQ

S_O

E_FF

DQS_OE_DELAY_CHAIN1 (D5) /DQS_OE_DELAY_CHAIN2 (D6)

DQS_OE_HR_DDIO_OUT





Figure 1–33. DQS_OE_DDIO_OE Connectivity

DQS_OE_HR_DDIO_OUT

Figure 1–34 shows the connectivity in the ALTDQ_DQS megafunction for the DQS_OE_HR_DDIO_OUT block. This block is used to transfer the output-enable signals from a half-rate clock to a full-rate clock.





The DQS_OE_HR_DDIO_OUT block can be bypassed. To instantiate this block, use the following parameter:


oe

clk

enadqs_oe_out dataout

areset

sreset

dqs_oe_in

dqs_output_reg_clk

dqs_output_reg_clken

dqs_areset

dqs_sreset

DQ

S_O

E_D

DIO

_OE

DQS_OE_DELAY_CHAIN1 (D5) / DQS_OE_DELAY_CHAIN2 (D6)

DQS_OE_HR_DDIO_OUT





Figure 1–34. DQS_OE_HR_DDIO_OUT Connectivity

Configuring the DQ/DQS OCT Path

Figure 1–35 shows the different blocks in the OCT path that can be configured. All the I/O pins have identically configured OCT paths. The possible values for <IO> are DQS, DQSn, BIDIR_DQ and OUTPUT_DQ.

The DQ/DQS OCT path is optional. This path is instantiated for bidirectional and output-only I/O pins if the parameter use_dynamic_oct=TRUE.

1 The OBUF block is configured with the ALTIOBUF megafunction.

Figure 1–35. OCT Path Blocks


this block.(2) The output of the <IO>_OCT_DELAY_CHAIN2 (D6 OCT) block is the <io>_oct_out signal.(3) This is an output register block.(4) This is a half-data rate block.

datainhi

datainlo

clkhidataout

clklo

areset

muxsel

dqs_hr_oe_in[1]

dqs_hr_oe_in[0]

dqs_hr_output_reg_clk

dqs_areset

DQ

S_O

E_H

R_D

DIO

_OU

T

DQS_OE_DDIO_OE_DQS_OE_FF

<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DELAY_CHAIN1 (D5 OCT)

<IO>_OCT_HR_DDIO_OUT (4)<IO>_OCT_FF /

<IO>_OCT_DDIO_OE (3)

OBUF (1)(2)



Figure 1–36 shows the valid configurations for the DQ/DQS OCT path and the possible connections between the blocks (shown in Figure 1–35) in this path. This path is between the FPGA core and the DQ/DQS output or bidirectional buffer. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.


Figure 1–36. Valid Configurations for the DQ/DQS OCT Path Note (1)

Note to Figure 1–36:(1) For each configuration, the far-left arrow indicates the DQ/DQS output or bidirectional buffer, and the far-right

arrow indicates the FPGA core.

<IO>_OCT_DELAY_CHAIN1 (D5 OCT)

<IO>_OCT_DELAY_CHAIN2 (D6 OCT)

<IO>_OCT_DELAY_CHAIN1 (D5 OCT)<IO>_OCT_DELAY_CHAIN2 (D6 OCT)

<IO>_OCT_DELAY_CHA IN1 (D5 OCT)<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_FF

<IO>_OCT_FF<IO>_OCT_DELAY_CHAIN1 (D5 OCT)

<IO>_OCT_FF

<IO>_OCT_DELAY_CHAIN1 (D5 OCT) <IO>_OCT_DDIO_OE

<IO>_OCT_DELAY_CHAIN1 (D5 OCT)<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DDIO_OE

<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN1 (D5 OCT) <IO>_OCT_FF

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN1 (D5 OCT)<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_FF

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DDIO_OUT

<IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN1 (D5 OCT) <IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN1 (D5 OCT)<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_DELAY_CHAIN2 (D6 OCT) <IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_DDIO_OE

HR_DDIO_OUT<IO>_OCT_FF

<IO>_OCT_FF<IO>_OCT_DELAY_CHAIN2 (D6 OCT)



<IO>_OCT_DELAY_CHAIN1 (D5 OCT) / <IO>_OCT_DELAY_CHAIN2 (D6 OCT)

There are two delay chains on the OCT path:

■ <IO>_OCT_DELAY_CHAIN1 (D5 OCT)■ <IO>_OCT_DELAY_CHAIN2 (D6 OCT)

These delay chains represent the run-time adjustable, but not PVT-compensated, delay chains. The delay-chain settings are controlled by the DQS_CONFIG output. There are two delay chains between the OCT Rt enable control register and output buffer.

These delay chain blocks are optional. To instantiate these blocks, use one or more of the following parameters:

■ use_oct_delay_chain1=TRUE■ use_oct_delay_chain2=TRUE


Figure 1–37. <IO>_OCT_DELAY_CHAIN1 (D5 OCT) / <IO>_OCT_DELAY_CHAIN2 (D6 OCT) Connectivity

datain<io>_oct_out datain


dataoutdataout <io>_oct_in

<IO

>_O

CT_

DEL

AY_C

HAI

N1

(D5

OC

T)

outputdelaysetting2

outputdelaysetting1 DQS_CONFIG

<IO

>_O

CT_

DEL

AY_C

HAI

N2

(D6

OC

T)

<IO>_OCT_FF /<IO>_OCT_DDIO_OE



<IO>_OCT_FF

Figure 1–39 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_OCT_FF block. This block is a basic I/O register on the OCT path.




Figure 1–38 shows an example implementation of the block in Stratix III devices.

Figure 1–38. Dynamic OCT Control Block in Stratix III Devices

Note to Figure 1–38:(1) Write clock comes from either the PLL or the write-leveling delay chain.

The <IO>_OCT_FF block is optional. To instantiate this block, use the following parameter:

■ oct_reg_mode=FF

Figure 1–39. <IO>_OCT_FF Connectivity

OCT Control

WriteClock (1)

OCT Enable

Resynchronization Registers

OCT Half-Rate Clock

OCT Control Path

DFFDFF

2

HDRBlock

clk

d

q<io>_oct_out

oct_reg_clk

<io>_oct_in

<IO

>_O

CT_

FF

<IO>_OCT_DELAY_CHAIN1 (D5 OCT) /<IO>_OCT_DELAY_CHAIN2 (D6 OCT)

<IO>_OCT_HR_DDIO_OUT





<IO>_OCT_DDIO_OE

Figure 1–40 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_OCT_DDIO_OE block. This block is a DDIO register on the OCT path.

For more details about the implementation of this block, refer to the following literature:


■ External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.


The <IO>_OCT_DDIO_OE block is optional. To instantiate this block, use the following parameter:

■ oct_reg_mode=DDIO

Figure 1–40. <IO>_OCT_DDIO_OE Connectivity


Figure 1–41 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_OCT_HR_DDIO_OUT block. This block is used to transfer the OCT signals from a half-rate clock to a full-rate clock.

f For more details about the implementation of this block, refer to the following literature:


clk

oe

dataout<io>_oct_out

oct_reg_clk

<io>_oct_in

<IO

>_O

CT_

DD

IO_O

E

<IO>_OCT_DELAY_CHAIN1 (D5 OCT) / <IO>_OCT_DELAY_CHAIN2 (D6 OCT)











Figure 1–41. <IO>_OCT_HR_DDIO_OUT Connectivity

Configuring the DQ Input Path

Figure 1–42 shows the different blocks in the DQ input path that can be configured.

Instantiate this path for all input-only and bidirectional DQ I/O pins. The <IO> in this section can be BIDIR_DQ or INPUT_DQ.

1 The IBUF block is configured with the ALTIOBUF megafunction.

datainhi

datainlo

clkhidataout

clklo

muxsel

<io>_hr_oe_in[1]

<io>_hr_oe_in[0]

hr_output_reg_clk

<IO

>_O

CT_

HR

_DD

IO_O

UT

<IO>_OCT_DDIO_OE




Figure 1–42. DQ Input Path

Notes to Figure 1–42:(1) The IBUF block is not part of the ALTDQ_DQS megafunction. Use the ALTIOBUF megafunction to generate this

block.(2) This is an input register block.(3) This is an alignment or synchronization block.(4) This is a half-data rate block.

Figure 1–43 shows the valid configurations for the DQ input path and the possible connections between the blocks (shown in Figure 1–42) in this path. This path is between the DQ input buffer and the FPGA core. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.


IBUF (1)

<IO>_INPUT_DELAY_CHAIN (D1)<IO>_IPA_HIGH (3)

<IO>_IPA_LOW (3)

<IO

>_IN

PUT_

FF /

<IO

>_D

DIO

_IN

(2)

<IO

>_H

ALF_

RAT

E_IN

PUT

(4)



Figure 1–43. Valid Configurations for DQ Input Path Note (1)

Note to Figure 1–43:(1) For each configuration, the far-left arrow indicates the DQ input buffer and the far-right arrow indicates the FPGA

core.

<IO>_INPUT_DELAY_CHAIN (D1)

The <IO>_INPUT_DELAY_CHAIN (D1) block is a delay chain on the DQ input path. This delay chain represents the run-time adjustable delay chain. The delay-chain setting is controlled by the IO_CONFIG output. Every I/O pin contains one delay chain between the input buffer and input register.

The <IO>_INPUT_DELAY_CHAIN (D1) block can be bypassed. To instantiate this block, use the following parameter:

■ use_dq_input_delay_chain=true






<IO>_INPUT_FF

<IO>_INPUT_FF

<IO>_HALF_RATE_INPUT




<IO>_DDIO_IN

<IO>_DDIO_IN

<IO>_INPUT_DELAY_CHAIN (D1) <IO>_DDIO_IN

<IO>_DDIO_IN

<IO>_DDIO_IN <IO>_IPA_LOW<IO>_IPA_LOW

<IO>_IPA_HIGH


<IO>_IPA_HIGH

<IO>_INPUT_DELAY_CHAIN (D1) <IO>_DDIO_IN <IO>_IPA_LOW<IO>_IPA_LOW

<IO>_IPA_HIGH


<IO>_IPA_HIGH



Figure 1–44. <IO>_INPUT_DELAY_CHAIN (D1) Connectivity

<IO>_INPUT_FF

Figure 1–45 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_INPUT_FF block. This block is a basic I/O register on the input path.





The <IO>_INPUT_FF block is optional. To instantiate this block, use the following parameter:

■ dq_input_reg_mode=FF

The block cannot be used if use_half_rate=TRUE.

dataout

<io>_input_data_in

datain

delayctrlin <IO>_INPUT_DELAY_CHAIN (D1)

<IO>_FF_IN /<IO>_DDIO_IN

<io>_input_data_out

padtoinputregisterdelaysetting<IO>_CONFIG





Figure 1–45. <IO>_INPUT_FF Connectivity

<IO>_DDIO_IN

Figure 1–46 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_DDIO_IN block. This block is a DDIO register on the input path.





The <IO>_DDIO_IN block is optional. To instantiate this block, use the following parameter:

■ dq_input_reg_mode=DDIO

d<io>_input_data_in

clkdq_input_reg_clk

clrn<io>_areset

dq_input_reg_clkena

sclr<io>_sreset

ena

<IO

>_IN

PUT_

FF

q


DQS_BUS

<io>_input_data_out





Figure 1–46. <IO>_DDIO_IN Connectivity

<IO>_IPA_HIGH / <IO>_IPA_LOW

Figure 1–47 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_IPA_HIGH/<IO>_IPA_LOW block.

The input phase-alignment primitive represents the circuitry required to phase-shift the input signal. This is primarily used to match the arrival delay of the DQS (triggered by the fly-by clock on a DDR3-DIMM memory module) to the latest arrival delay of a DQS signal from the DIMM memory module.





These blocks can be bypassed. To instantiate these blocks, use the following parameter:

■ use_dq_ipa=TRUE

datain regouthi<io>_input_data_in

clkdq_input_reg_clk

clkn

<io>_areset

dq_input_reg_clkena ena

<io>_sreset

areset

sreset

<IO

>_D

DIO

_IN


DQS_BUS

DQSN_BUS

<io>_input_data_out_high

<io>_input_data_out_low

<IO>_IPA_HIGH / <IO>_HALF_RATE_INPUT

regoutlo<IO>_IPA_LOW / <IO>_HALF_RATE_INPUT





Figure 1–47. <IO>_IPA_HIGH / <IO>_IPA_LOW Connectivity


Figure 1–48 shows the connectivity in the ALTDQ_DQS megafunction for the <IO>_HALF_RATE_INPUT block. This block is used to transfer the input signals from a full-rate clock to a half-rate clock.







<io>_areset

clk

datain [1..0]

dp_ipa_clk


phasectrlin

phaseinvertctrl

enainputcycledelay

enainputphasetransferreg

<io>_input_data_out_high /<io>_input_data_out_lowareset

resyncinputphasesetting

resyncinputphaseinvert

enainputcycledelaysetting

enainputphasetransferreg

<IO

>_IP

A_H

IGH

/ <I

O>_

IPA>

LOW

DQ

S_C

ON

FIG

dataout [3..0]


<IO>_DDIO_IN





Figure 1–48. <IO>_HALF_RATE_INPUT Connectivity

Configuring the DQ Output Path

The DQ output path is configured in the same way as the DQS output path. This path must be configured for all BIDIR_DQ and OUTPUT_DQ blocks.

f For more details about the blocks used in this path, refer to “Configuring the DQS Output Path” on page 1–26

Figure 1–49 shows the different blocks in the DQ output path that can be configured. The possible values for <IO> are BIDIR_DQ and OUTPUT_DQ.

datain

directin<io>_input_data_in

clk

dataoutbypass

enadataoutbypass

areset <io>_hr_input_data_out<io>_areset

IO_CLOCK_DIVIDER: clkout

<IO

>_H

ALF_

RAT

E_IN

PUT

DQ

S_C

ON

FIG

dataout

<IO>_DDIO_IN /<IO>_IPA_HIGH / <IO>_IPA_LOW_



Figure 1–49. DQ Output Path Blocks

Notes to Figure 1–49:(1) The <IO>_OBUF block is not part of the ALTDQ_DQS megafunction. Use the ALTIOBUF megafunction to generate

this block.(2) This is an output register block.(3) This is a half-data rate block.

Figure 1–50 shows the valid configurations for the DQ output path and the possible connections between the blocks (shown in Figure 1–49) in this path. This path is between the DQ output buffer and the FPGA core. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.


<IO>_OBUF (1) <IO>_OUTPUT_DELAY_CHAIN2 (D5) <IO>_OUTPUT_DELAY_CHAIN1 (D6)

<IO>_OUTPUT_HR_DDIO_OUT_HIGH (3)

<IO>_OUTPUT_HR_DDIO_OUT_LOW (3)

<IO>_OUTPUT_FF /<IO>_OUTPUT_DDIO_OUT (2)



Figure 1–50. Valid Configurations for DQ Output Path Note (1)

Note to Figure 1–50:(1) For each configuration, the far-left arrow indicates the DQ output buffer and the far-right arrow indicates the FPGA

core.

Configuring the DQ OE Path

The DQ OE path can be configured in the same way as the DQS OE path. This path must be configured for all BIDIR_DQ blocks. This path must also be configured for all OUTPUT_DQ blocks if the parameter use_dq_oe_path=TRUE.

f For descriptions of the blocks used in this path, refer to the block descriptions in “Configuring the DQS OE Path” on page 1–33

Figure 1–51 shows the different blocks in the DQ OE path that need to be configured. The possible values for <IO> are BIDIR_DQ and OUTPUT_DQ.

<IO>_OUTPUT_DELAY_CHAIN1 (D5)


<IO>_OUTPUT_DELAY_CHAIN2 (D6) <IO>_OUTPUT_DELAY_CHAIN1 (D5)


<IO>_OUTPUT_FF

<IO>_OUTPUT_FF

<IO>_OUTPUT_DDIO_OUT



<IO>_OUTPUT_DELAY_CHAIN2 (D6) <IO>_OUTPUT_DDIO_OUT



<IO>_OUTPUT_DDIO_OUT HR_DDIO_OUT_HIGH / LOW

HR_DDIO_OUT_HIGH / LOW




<IO>_OUTPUT_DDIO_OUT<IO>_OUTPUT_DELAY_CHAIN2 (D6) <IO>_OUTPUT_DELAY_CHAIN1 (D5)



<IO>_OUTPUT_FF

<IO>_OUTPUT_FF<IO>_OUTPUT_DELAY_CHAIN2 (D6)



Figure 1–51. DQ OE Path Blocks

Notes to Figure 1–51:(1) The <IO>_OBUF block is not part of the ALTDQ_DQS megafunction. Use the ALTIOBUF megafunction to generate

this block.(2) This is an output register block.(3) This is a half-data rate block.

Figure 1–52 shows the valid configurations for the DQ OE path and the possible connections between the blocks (shown in Figure 1–51) in this path. This path is between the DQ output buffer and the FPGA core. You must know the configurations that are valid for this path based on the data path requirements of your custom external memory interface.


<IO>_OE_DELAY_CHAIN2 (D6) <IO>_OE_DELAY_CHAIN1 (D5)

<IO>_OE_HR_DDIO_OUT (3)<IO>_OE_FF /

<IO>_OE_DDIO_OE (2)

<IO>_OBUF (1)



Figure 1–52. Valid Configurations for DQ OE Path Note (1)

Note to Figure 1–52:(1) For each configuration, the far-left arrow indicates the DQ output buffer and the far-right arrow indicates the FPGA

core.

Configuring the DQSn I/O Pin

The DQSn I/O pin is configured based on the parameter dqs_dqsn_mode.

If dqs_dqsn_mode=NONE, no DQSn I/O pin is configured.

If dqs_dqsn_mode=differential, the DQSn I/O pin is configured in a differential pair together with the DQS I/O pin. This means that the OE and OCT paths are configured for the DQSn I/O pin, which is the same as the DQS I/O pin, whereas the input and output paths are shared with the DQS I/O pin. This mode is used mainly for DDR2/DDR3-SDRAM and RLDRAMII applications.

If dqs_dqsn_mode=complementary, the DQSn I/O pin is configured in a complementary pair together with the DQS I/O pin. In this mode, the DQSn I/O pin is configured in the same way as the DQS I/O pin. This mode is used mainly for QDR applications.

<IO>_OE_DELAY_CHAIN1 (D5)




<IO>_OE_FF

<IO>_OE_FF

<IO>_OE_DDIO_OE

HR_DDIO_OUT

HR_DDIO_OUT

HR_DDIO_OUT

<IO>_OE_DDIO_OE

<IO>_OE_DDIO_OE

<IO>_OE_DELAY_CHAIN2 (D6) <IO>_OE_DDIO_OE

<IO>_OE_DDIO_OE

<IO>_OE_FF

HR_DDIO_OUT<IO>_OE_FF<IO>_OE_DELAY_CHAIN2 (D6) <IO>_OE_DELAY_CHAIN1 (D5)




<IO>_OE_FF

<IO>_OE_FF<IO>_OE_DELAY_CHAIN1 (D5)

HR_DDIO_OUT<IO>_OE_FF<IO>_OE_DELAY_CHAIN2 (D6)

<IO>_OE_FF<IO>_OE_DELAY_CHAIN2 (D6)


Delay Chains For External Memory Interfaces

Configuring the DQS_CONFIG / IO_CONFIG Block

The IO_CONFIG block represents the shift register that can be used to dynamically change the settings of various device configuration bits. The shift register powers up low. Every I/O pin contains one IO_CONFIG block.

The DQS_CONFIG block also represents the shift register that can be used to dynamically change the settings of various device configuration bits. The shift register powers up low. Every DQS pin contains one DQS_CONFIG block and one IO_CONFIG block.

One IO_CONFIG block is configured per I/O pin, while one DQS_CONFIG block is configured per x4 group of I/O pins (similar to the IO_CLOCK_DIVIDER blocks).

These blocks share the same datain, clk, and update signals. However, each block has its own ena signal.


Figure 1–53 shows an overview of the IOE structure for Stratix III and Stratix IV devices. It also shows the delay chains for external memory interfaces and the location of delay elements. Delay elements can be dynamically controlled to provide a better sampling window for external memory interfaces.



Figure 1–53. IOE Structure for Stratix III and Stratix IV Devices Note (1)

Notes to Figure 1–53:(1) D3_0 and D3_1 delays have the same available settings in the Quartus II software.(2) One dynamic OCT control is available per DQ/DQS group.

2 OEfromCore

4

Open Drain

On-ChipTermination

Bus-HoldCircuit

Programmable Current

Strength and Slew Rate

Control

PCI Clamp

VCCIO

VCCIO

ProgrammablePull-Up Resistor

Half Data Rate Block

Alignment Registers

Half Data Rate Block

WriteDatafromCore

Alignment Registers

4 Half Data Rate Block

Alignment andSynchronization

Registers

PRND Q

PRND Q

PRND Q

PRND Q

PRND Q

OE Register

OE Register

Output Register

Output Register

clkout

ToCore

ToCore

D5, D6Delay

Input Register

PRND Q

Input Register

PRND Q

Input Register

clkin

D5, D6Delay

ReadDatatoCore

From OCTCalibration

Block

D2 DelayD3_0Delay

D3_1Delay

D1Delay

Output Buffer

Input Buffer

D5_OCT D6_OCT

Firm Core

DQS Logic Block

Dynamic OCT Control (2)

D4 DelayDQSCQn



Table 1–2 shows the delay chains that you can use in the ALTDLL and ALTDQ_DQS megafunctions.

Table 1–2. Delay Chains in the ALTDLL and ALTDQ_DQS Megafunctions (Part 1 of 2)

Instance Name Block Type Path Block Name Control BlockDelay

Element Type

dqsbusout_delay_chain_inst / dqsnbusout_delay_chain_inst

DELAY_CHAIN DQS Input Path DQSBUSOUT_DELAY_CHAIN

DQS_CONFIG —

dqs_delay_chain_inst / dqsn_delay_chain_inst

DQS_DELAY_CHAIN

DQS Input Path DQS_DELAY_CHAIN

DLL —

dqsenable_delay_chain_inst

DELAY_CHAIN DQS Input Path DQSENABLE_DELAY_CHAIN

DQS_CONFIG —

dqs_oct_delay_chain1_inst / dqsn_oct_delay_chain1_inst / bidir_dq_oct_delay_chain1_inst

DELAY_CHAIN DQ/DQS/DQSn OCT Path

<IO>_OCT_DELAY_CHAIN1

DQS_CONFIG D5 OCT

dqs_oct_delay_chain2_inst / dqsn_oct_delay_chain2_inst / bidir_dq_oct_delay_chain2_inst

DELAY_CHAIN DQ/DQS/DQSn OCT Path

<IO>_OCT_DELAY_CHAIN2

DQS_CONFIG D6 OCT

bidir_dq_input_delay_chain_inst / input_dq_input_delay_chain_inst / dqs_input_delay_chain_inst / dqsn_input_delay_chain_inst

DELAY_CHAIN DQ/DQS/DQSn Input Path

<IO>_INPUT_DELAY_CHAIN

IO_CONFIG D1

bidir_dq_output_delay_chain1 / output_dq_output_delay_chain1 / dqs_output_delay_chain1_inst

DELAY_CHAIN DQ/DQS Output Path

<IO>_OUTPUT_DELAY_CHAIN1

IO_CONFIG D5



Table 1–3 shows the delay elements and their respective settings.

bidir_dq_output_delay_chain2 / output_dq_output_delay_chain2 / dqs_output_delay_chain2_inst

DELAY_CHAIN DQ/DQS Output Path

<IO>_OUTPUT_DELAY_CHAIN2

IO_CONFIG D6

bidir_dq_oe_delay_chain1_inst / output_dq_oe_delay_chain1_inst / dqs_oe_delay_chain1_inst / dqsn_oe_delay_chain1_inst

DELAY_CHAIN DQ/DQS/DQSn OE Path

<IO>_OE_DELAY_CHAIN1

IO_CONFIG D5

bidir_dq_oe_delay_chain2_inst / output_dq_oe_delay_chain2_inst / dqs_oe_delay_chain2_inst / dqsn_oe_delay_chain2_inst

DELAY_CHAIN DQ/DQS/DQSn OE Path

<IO>_OE_DELAY_CHAIN2

IO_CONFIG D6

Table 1–2. Delay Chains in the ALTDLL and ALTDQ_DQS Megafunctions (Part 2 of 2)

Instance Name Block Type Path Block Name Control BlockDelay

Element Type

Table 1–3. Delay Elements and Settings (Part 1 of 2)

Delay Chain Type (1) Function Available

SettingsStep Value

(ps) (4)

Minimum Delay Value

(ps) (5)

Maximum Delay Value

(ps) (5)

D1 (1) This delay chain is set to tune the DQ delay (read calibration) in DDR applications

16 (2) 50 0 750

D5 and D5 OCT (1),(6)

This delay chain is used for write calibration in DDR applications

16 (2) 50 0 750


Examples of Custom External Memory Interface Data Paths


Figures 1–54 to 1–56 show the block diagrams for the circuitry involved in implementing memory interfaces in Stratix III and Stratix IV devices.

1 The block diagrams do not show the IO_CONFIG and DQS_CONFIG blocks, but you can add these blocks to fine-tune the delay chains. These blocks are necessary to tune the leveling delay chains in the INPUT_PHASE_ALIGNMENT blocks. The block diagrams also do not show any reset signals, but all registers in the I/O blocks can be controlled by reset signals.

The DQS/DQS# inputs can go through a differential input buffer. Altera recommends that you use differential input buffers for DDR2 SDRAM interfaces. However, differential output buffers are not available on all I/O pins; therefore the DQS/DQS# outputs must use single-ended output buffers with the DQS#-fed inverted data compared to the DQS.

DDR/DDR2-SDRAM Full-Rate Interface

The ALTDLL, ALTDQ_DQS, ALTPLL and ALTIOBUF megafunctions implement the circuitry in Figure 1–54 for a full-rate operation. The read data from the core is transferred from the resync_postamble_clk clock domain to the PHY clock domain via a dual-clock FIFO. Similarly,

D6 and D6 OCT (1),(6)

To reduce simultaneous switching noise (SSN). This delay chain can be adjusted on a group basis for non-DDR3 applications. This delay chain works with a write-leveling clock to adjust the delay among groups for DDR3 applications.

8 (3) 50 0 350

Notes to Table 1–3:(1) For hardware details about the delay chain, refer to the respective Stratix III and Stratix IV device handbook or

datasheet.(2) The delay control in the chain is 4 bits wide, which means there are 16 possible settings.(3) The delay control in the chain is 3 bits wide, which means there are 8 possible settings.(4) Each step value is either 50 or 400 ps. Setting a value of 10 means 10 x 50 = 500 ps of delay if the step value is 50 ps.(5) The minimum delay value factors in only variable delays, but not the intrinsic delay present in the delay chain. For

more information on intrinsic delays, refer to the respective Stratix III and Stratix IV device handbook or datasheet.(6) D5 and D6 can be cascaded together to generate the sum of delays.

Table 1–3. Delay Elements and Settings (Part 2 of 2)

Delay Chain Type (1) Function Available

SettingsStep Value

(ps) (4)

Minimum Delay Value

(ps) (5)

Maximum Delay Value

(ps) (5)



the DQS-enable signal from the core is transferred from the PHY clock domain to the resync_postamble_clk domain via another dual-clock FIFO.

Figure 1–54. Typical DDR/DDR2-SDRAM Full-Rate Interface

Notes to Figure 1–54:(1) Da represents the DQSBUSOUT_DELAY_CHAIN block.(2) Db represents the DQSENABLE_DELAY_CHAIN block.(3) You must use this parameter. Set use_dq_ipa_phasectrlin = FALSE and

dq_ipa_bypass_output_register = TRUE.(4) You must use this parameter. Set use_dqs_enable_ctrl_phasectrlin = FALSE and

level_dqs_enable = FALSE.

6

FF (oe)

DDIO_OUT

INPUT_PHASE_ALIGN(3)


DDIO_IN

DDIO_OE

DDIO_OE(extended_rtena)

DDIO_OUT

DQSENABLE

DQS DelayChain

DLL OffsetControl

DLL

PLL

DQS EnableControl

(4)

6

mem_clk

write_clk

resync_postamble_clk

DQ OE

WriteData

DQS OE

rtena

DDIO_OE(extended_rtena) rtena

DQSEnable

DQSOutput

ReadData

D6 D5

D6 D5

D1

D6

D5D5

OCT

D6OCT

DQ

D6

D5D5

OCT

D6OCT

DQS

Da(1)

Db(2)



DDR/DDR2-SDRAM Half-Rate Interface

The ALTDLL, ALTDQ_DQS, ALTPLL, and ALTIOBUF megafunctions implement the circuitry in Figure 1–55 for a half-rate operation. The data read from the core is transferred from the half-rate resync_clk clock domain to the PHY clock domain via a dual-clock FIFO. Similarly, the DQS-enable signal from the core is transferred from the PHY clock domain to the half-rate resync_clk domain via another dual-clock FIFO. To conserve global routing, the half-rate resync_clk should be restricted to local routing by setting the GLOBAL_SIGNAL=OFF.



Figure 1–55. DDR/DDR2-SDRAM Half-Rate Interface

Notes to Figure 1–55:(1) Da represents the DQSBUSOUT_DELAY_CHAIN block.(2) Db represents the DQSENABLE_DELAY_CHAIN block.(3) You must use this parameter. Set use_dq_ipa_phasectrlin = FALSE and

dq_ipa_bypass_output_register = TRUE.(4) You must use this parameter. Set use_dqs_enable_ctrl_phasectrlin = FALSE and

level_dqs_enable = FALSE.

2

2

2

2

6

FF (oe)

DDIO_OUT



DDIO_IN

DDIO_OE

DDIO_OE(extended_rtena)

DDIO_OUT

DQSENABLE

I/O ClockDivider

DQS DelayChain

DLL OffsetControl

DLL

PLL

DQS EnableControl

(4)

6

mem_clk

write_clk

resync_postamble_clk

PHY_clk (half-rate)

DQ OE

WriteData

DQS OE

rtena

DDIO_OE(extended_rtena) DDIO_OUT

(half_rate_mode=true)

DDIO_OUT(half_rate_mode=true)














2DDIO_OUT(half_rate_mode=true)



rtena

DQSEnable

DQSOutput

ReadData

D6 D5

D6 D5

D1

D6

D5D5

OCT

D6OCT

DQ

D6

D5D5

OCT

D6OCT

DQS

Da(1)

Db(2)

Half-RateInput

2

2

2

2

4

half-rate resync_clk



RLDRAMII/QDRII Half-Rate Interface

Figure 1–56 shows a RLDRAMII/QDRII half-rate interface.

Figure 1–56. RLDRAMII/QDRII Half-Rate Interface

Note to Figure 1–56:(1) Da represents the DQSBUSOUT_DELAY_CHAIN block.

6

FF (oe)

DDIO_OUT

DDIO_IN

DDIO_OUT

DLL OffsetControl

DLL

PLL

6

mem_clk

write_clk

PHY_clk (half-rate)

DQ OE

WriteData

FF(rtena) DDIO_OUT

(half_rate_mode=true)








rtena

ReadData

D6 D5

D6 D5

D1

D6

D5D5

OCT

D6OCT

DQ

CK

DQSDa(1)

Half-RateInput

2

2

2

2

4

DQS DelayChain

I/O ClockDivider

DS_clk (half-rate)

VCC

GND



General Ports and Parameters for the DDR, QDR, and RLDRAM Interfaces

Table 1–4 shows the general parameters for the DDR, QDR, and RLDRAM interfaces.

Table 1–4. General Parameters for DDR, QDR and RLDRAM Interfaces (Part 1 of 2)

Parameter DDRQDR RLDRAM

read write read write

number_of_bidir_dq n (1) 0 0 n (1)

number_of_input_dq 0 n (1) 0 0

number_of_output_dq 0 0 n (1) 0

use_dq_oe_path TRUE FALSE TRUE TRUE

use_half_rate For full-rate controller: FALSE For half-rate controller: TRUE

use_dynamic_oct Dynamic OCT not enabled: FALSE Dynamic OCT enabled: TRUE

number_of_clk_divider

For full-rate controller: 0 For half-rate controller: 2

dq_input_reg_mode DDIO DDIO NONE DDIO

dq_input_reg_power_up

LOW LOW LOW

dq_input_reg_async_mode

NONE NONE NONE

dq_input_reg_sync_mode

NONE NONE NONE

dq_input_reg_clk_source

DQS_BUS DQS_BUS DQS_BUS

dq_input_reg_use_clkn

FALSE TRUE FALSE FALSE

dq_output_reg_mode DDIO NONE DDIO DDIO

dq_output_reg_power_up

LOW LOW LOW

dq_output_reg_async_mode

NONE NONE NONE

dq_output_reg_sync_mode

NONE NONE NONE

use_dqs TRUE TRUE FALSE TRUE FALSE

use_dqs_input_path TRUE TRUE FALSE TRUE FALSE



use_dqs_output_path TRUE FALSE FALSE

use_dqs_oe_path TRUE FALSE FALSE

dqs_dqsn_mode If used: DIFFERENTIALIf single_ended:

NONE

COMPLEMENTARY DIFFERENTIAL

dqs_input_frequency <x> MHz (e.g. 400 MHz)

dqs_delay_chain_phase_setting

<n> = phase_shift / 360 x DLL_delay_chain_length

dqs_delay_chain_delayctrlin_source

DLL

use_dqs_input_delay_chain

Default: FALSEIf used: TRUE

delay_buffer_mode HIGH or LOW (depending on the ALTDLL instantiation settings)

use_dqs_delay_chain TRUE

Note to Table 1–4:(1) n represents the number of pins in a path. The value of n can be from 0 to 48, but varies according to the memory

interface used. To get the valid n value of a particular memory interface, refer to the External Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook or the External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.

Table 1–4. General Parameters for DDR, QDR and RLDRAM Interfaces (Part 2 of 2)

Parameter DDRQDR RLDRAM

read write read write







Table 1–5 shows the general ports for the DDR, QDR, and RLDRAM interfaces.

Table 1–5. General Ports for DDR, QDR and RLDRAM Interfaces

PortController

Full-Rate Half-Rate

input_dq_input_data_in Used Used

input_dq_input_data_out_high Used Unused

input_dq_input_data_out_low Used Unused

input_dq_hr_input_data_out Unused Used

output_dq_output_data_out Used Used

output_dq_output_data_in_low Used Unused

output_dq_output_data_in_high Used Unused

output_dq_hr_output_data_in Unused Used

output_dq_hr_oe_in Unused Used

output_dq_oe_in Used Unused

output_dq_oe_out Used Used

bidir_dq_input_data_in Used Used

bidir_dq_hr_input_data_out Unused Used

bidir_dq_output_data_out Used Used

bidir_dq_hr_output_data_in Unused Used

dqs_input_data_in Used Used

dqs_hr_output_data_in Unused Used

dqsn_input_data_in Used Used

dqsn_hr_output_data_in Unused Used

dqs_bus_out Used Used

dqs_output_data_out Used Used

dqs_oe_out Used Used

dqs_hr_oe_in Unused Used

dqs_oe_in Used Unused

dq_input_reg_clk Used Used

dq_output_reg_clk Used Unused

dq_hr_output_reg_clk Unused Used

dll_delayctrlin Used Used

io_clock_divider_clk Used Used



Table 1–6 shows the general OCT parameters for the DDR, QDR, and RLDRAM interfaces..

Table 1–7 shows the general OCT ports for the DDR, QDR, and RLDRAM interfaces..

Table 1–6. General OCT Parameters for DDR, QDR and RLDRAM Interfaces

Parameter Controller

use_dynamic_oct TRUE

use_oct_delay_chain1 TRUE / FALSE

use_oct_delay_chain2 TRUE / FALSE

oct_reg_mode FF

Table 1–7. General OCT Ports for DDR, QDR and RLDRAM Interfaces

Parameter Controller

dqs_oct_in Used

dqsn_oct_in Used

bidir_dq_oct_in Used if DQ pin is bidirectional

input_oct_in Used for DQ pin as input

output_oct_in Used for DQ pin as output

dqs_hr_oct_in Used if controller is at half-rate

dqsn_hr_oct_in Used if controller is at half-rate

bidir_dq_hr_oct_in Used if controller is at half-rate

input_dq_hr_oct_in Used if controller is at half-rate

output_dq_hr_oct_in Used if controller is at half-rate

oct_reg_clk Used

hr_oct_reg_clk Used if controller is at half-rate

dqs_oct_out Used

dqsn_oct_out Used

bidir_dq_oct_out Used if DQ pin is bidirectional

input_dq_oct_out Used for DQ pin as input

output_dq_oct_out Used for DQ pin as output



Timing Analysis Unlike the ALTMEMPHY megafunction, which provides the complete solution for external memory interface standards, the ALTDLL and ALTDQ_DQS megafunctions provide only mid-level support for timing analysis. These megafunctions do not provide automatic timing scripts for custom external memory interfaces; therefore, you must perform your own timing analysis.

Because the timing analysis for custom external memory interfaces are the same as the timing analysis for source-synchronous interfaces, you can refer to the following literature:

■ Timing Analysis section in volume 3 of the Quartus II Handbook ■ AN 433: Constraining and Analyzing Source-Synchronous Interfaces

Common Applications for the ALTDLL Megafunction

The ALTDLL megafunction can be used in the following ways:

■ Instantiate the ALTMEMPHY megafunction with the option to instantiate the DLL externally. Then use the ALTDLL megafunction to instantiate the DLL and connect the instantiations. This is useful for cases where you have multiple ALTMEMPHY instantiations in the design and you want to share the DLL between the ALTMEMPHY instantiations, as shown in Figure 1–57.

Figure 1–57. Sharing a DLL with Multiple ALTMEMPHY Instantiations

■ Instantiate a DLL using the ALTDLL megafunction. Then use the ALTDQ_DQS and ALTIOBUF megafunctions to instantiate the memory interface I/O pins.

f For more information on how to connect the instantiations in this configuration, refer to “ALTDQ_DQS Features” on page 1–9.

Figure 1–58 shows how you can configure both the ALTDLL and ALTDQ_DQS megafunctions.

ALTMEMPHY ALTMEMPHY

ALTDLL


http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf

http://www.altera.com/literature/an/an433.pdf

Common Applications for the ALTDQ_DQS Megafunction

Figure 1–58. Using the ALTDLL Megafunction with the ALTDQ_DQS Megafunction

Common Applications for the ALTDQ_DQS Megafunction

Figure 1–59 shows a high-level overview of how you can connect the ALTDQ_DQS megafunction with other blocks to create a full memory interface.

Figure 1–59. System-Level View

ALTIOBUF (DQS/DQSN)

ALTIOBUF (BIDIR_DQ)

ALTIOBUF (INPUT_DQ)

ALTIOBUF (OUTPUT_DQ)

ALTDQ_DQSx9

ALTDQ_DQSx9ALTDQ_DQS

x9

ALTPLL

ALTDQ_DQSx9

ALTDLL

ALTIOBUF (DQS/DQSN)

ALTIOBUF (BIDIR_DQ)

ALTIOBUF (INPUT_DQ)

ALTIOBUF (OUTPUT_DQ)

ALTDQ_DQSx9

ALTDQ_DQSx9ALTDQ_DQS

x9ALTDQ_DQS

x9

ALTDLL

ALTPLL



For example, Figure 1–59 shows a 36-bit interface created with ALTDQ_DQS instantiations, where each instantiation is configured in the x9 mode.

The ALTDQ_DQS megafunction differs from the ALTDQ and ALTDQS megafunctions in the following ways:

■ The DLL block is instantiated separately using the ALTDLL megafunction

■ The buffers (IO_IBUF, IO_OBUF, and PSEUDO_DIFF_OUT blocks) are configured using the ALTIOBUF megafunction

Resource Usage and Performance

For details about the resource usage of the ALTDLL and ALTDQ_DQS megafunctions in various configurations, refer to the “resc_count“ command from the Clear-Box Generator and the compilation reports in the Quartus II software.

f For details about the Clear-Box Generator, refer to “Clear-Box Generator Options for ALTDQ_DQS Megafunction” on page 2–12.


Resource Usage and Performance


Altera Corporation July 2008

Chapter 2. Getting Started

System Requirements

The instructions in this section require the following hardware and software:

■ The Quartus® II software version 8.0 or later■ For operating system support information, refer to

www.altera.com/support/software/os_support/oss-index.html

MegaWizard Plug-In Manager Page Description for the ALTDLL Megafunction

This section provides descriptions of the options available on the individual pages of the ALTDLL MegaWizard® Plug-In Manager.

1 The ALTDQ_DQS megafunction does not have any graphical user interface (GUI). For details about generating this megafunction, refer to “Clear-Box Generator Options for ALTDQ_DQS Megafunction” on page 2–12

On page 1 of the MegaWizard Plug-In Manager, select Create a new custom megafunction variation, Edit an existing custom megafunction variation, or Copy an existing custom megafunction variation (Figure 2–1).

Figure 2–1. MegaWizard Plug-In Manager [page 1]

Confidential—Internal Use Only 2–1ALTDLL and ALTDQ_DQS Megafunctions User Guide

http://www.altera.com/support/software/os_support/oss-index.html


On page 2a of the MegaWizard Plug-In Manager, specify the device family to use, type of output file to create, and the name of the output file (Figure 2–2). You can choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type.

Figure 2–2. MegaWizard Plug-In Manager [page 2a]


Getting Started

On page 3 of the ALTDLL MegaWizard Plug-In Manager, you can turn jitter reduction on or off, and specify the chain delay length, delay buffer mode, and input frequency (Figure 2–3).

Figure 2–3. MegaWizard Plug-In Manager [page 3 of 6]



Table 2–1 shows the options available on page 3 of the ALTDLL MegaWizard Plug-In Manager.

Table 2–1. ALTDLL MegaWizard Plug-In Manager [page 3] Options (Part 1 of 2)

Options Description

Turn on jitter reduction If turned on, the jitter reduction circuit is enabled on the dll_delayctrlout[5..0] and dll_offset_ctrl_a_offsetctrlout [5..0] or dll_offset_ctrl_b_offsetctrlout [5..0] output ports. The DLL may require up to 1024 clock cycles to lock.

If turned off, the jitter reduction circuit is disabled and the DLL requires only up to 256 clock cycles to lock. By default, this option is turned off.

Jitter affects the signal integrity of the clock signal from a PLL clock source or an external clock pin. Turn on this option to reduce jitter. However, with this option turned on, the DLL has a longer lock time. Turn off this option if jitter is not a concern. If this option is turned off, the DLL has a shorter lock time. (2)

What is the delay chain length? Represents the number of delay buffers in the delay loop. The available values are 6, 8, 10, 12, and 16. The default value is 12.

The DLL consists of 6, 8, 10, 12, or 16 DLL-controlled delay buffers chained together. The delay chain length is specified by the delay_chain_length parameter. The total delay in the DLL delay chain can be computed with the following equation:

The DLL uses the delay chain to implement a 360° phase shift. By comparing the incoming clock to the 360°-shifted clock, the DLL determines the delay setting to implement an actual 360° phase shift in its delay chain. Because each delay buffer is identical, each buffer in the delay chain implements a phase shift that is equal to (360/delay_chain_length)°.(1), (2)

delay delay_chain_length delay_buffer_delay×=


Getting Started

On page 4 of the ALTDLL MegaWizard Plug-In Manager, you can instantiate the DLL offset control blocks (A and B), specify whether to use static offset or not, and create the optional ports of dll_aload and dll_dqsupdate (Figure 2–4).

What is the delay buffer mode? Determines whether the variable delay buffers are working in low-frequency mode or high-frequency mode. Available values are low and high. The default is low.

For Stratix III devices, a low-frequency mode has a frequency range of 100 to 250 MHz. A high-frequency mode has a frequency range of 250 to 400 MHz.

For details about the frequency of Stratix IV devices, refer to the Stratix IV Device Handbook.

If set to low, the dll_offset_ctrl_a_offsetctrlout [5..0] or dll_offset_ctrl_b_offsetctrlout [5..0] output is limited to a maximum of 63.

If set to high, the output is limited to a maximum of 31. (2), (3)

What is the input frequency? Frequency of the clock (in MHz) that is connected to the clk input port. Check the value to ensure that it is within the valid range. The default value is 0. You can specify a duration by placing a time unit after the value (e.g., 2.5 ns). The value is in floating-point format with no decimal point limit.

Notes to Table 2–1:(1) To get the appropriate delay-chain length for a frequency, refer to the respective device datasheet or External

Memory Interfaces chapter in the Stratix III Device Handbook and Stratix IV Device Handbook.(2) For hardware details about the DLL block and its phase-offset control blocks, refer to the respective External

Memory Interfaces chapter of the Stratix III Device Handbook and Stratix IV Device Handbook.(3) To get the appropriate delay-buffer mode for a frequency range, refer to the respective device datasheet or External

Memory Interfaces chapter in the Stratix III Device Handbook and Stratix IV Device Handbook.


Options Description



Figure 2–4. MegaWizard Plug-In Manager [page 4 of 6]

Table 2–2 shows the options available on page 4 of the ALTDLL MegaWizard Plug-In Manager.


Getting Started


Options Description

Instantiate DLL offset control (DLL Offset Control A)

Specifies whether to instantiate the DLL_OFFSET_CTRL_A block. The name DLL_OFFSET_CTRL_A is logical and does not denote the placement of the actual phase-offset block. The block can be placed either at the top, bottom, or side of the FPGA device, depending on how the Quartus II Fitter places it.

Use DLL offset (DLL Offset Control A) Determines the output of the dll_offset_ctrl_a_offsetctrlout[5..0] output bus.

If set to true, depending on whether the dll_offset_ctrl_a_addnsub input is asserted or not, the phase offset specified on the offset input bus is added or subtracted from the DLL feedback counter output to get the dll_offset_ctrl_a_offsetctrlout[5..0] output.

If set to false, the phase offset specified by the DLL Static Offset (DLL Offset Control A) option is added to the offsetdelayctrlin (an internal signal in the ALTDLL megafunction) input to get the dll_offset_ctrl_a_offsetctrlout[5..0] output.

This field defaults to false.

DLL static offset (DLL Offset Control A) This is a Gray-coded signed integer expressed with a range from –63 to 63.

If Use DLL offset (DLL Offset Control A) is set to false, the value is added to the DLL feedback counter value and output is generated on the dll_offset_ctrl_a_offsetctrlout[5..0] output bus.

If Use DLL offset (DLL Offset Control A) is set to true, this value is ignored.

This field defaults to 0.

Instantiate DLL offset control (DLL Offset Control B)

Specifies whether to instantiate the DLL_OFFSET_CTRL_B block. The name DLL_OFFSET_CTRL_B is logical and does not denote the placement of the actual phase-offset block. The block can be placed either at the top, bottom, or side of the FPGA device, depending on how the Quartus II Fitter places it.



Use DLL offset (DLL Offset Control B) Determines the output of the dll_offset_ctrl_b_offsetctrlout[5..0] output bus.

If set to true, depending on whether the dll_offset_ctrl_b_addnsub input is asserted or not, the phase offset specified on the offset input bus is added or subtracted from the DLL feedback counter output to get the dll_offset_ctrl_b_offsetctrlout [5..0] output.

If set to false, the phase offset specified by the DLL Static Offset (DLL Offset Control B) option is added to the offsetdelayctrlin (an internal signal in the ALTDLL megafunction) input to get the dll_offset_ctrl_b_offsetctrlout[5..0] output.

This field defaults to false.

DLL static offset (DLL Offset Control B) This is a Gray-coded signed integer expressed with a range from –63 to 63.

If Use DLL offset (DLL Offset Control B) is set to false, the value is added to the DLL feedback counter value and output is generated on the dll_offset_ctrl_b_offsetctrlout[5..0] output bus.

If Use DLL offset (DLL Offset Control B) is set to true, this value is ignored.

This field defaults to 0.

Create a dll_aload port (Optional Ports) This is an asynchronous-load signal for the up/down counter of the DLL. When dll_aload signal is high, the counter is asynchronously loaded with the initial delay setting of 16 in low-frequency mode (when delay_buffer_mode option is set to low), or 32 in high-frequency mode (when delay_buffer_mode is set high). This input defaults to GND.

Create a dll_dqsupdate port (Optional Ports) This is an update-enable signal for the delay-setting latches in the DQS pins. This signal can only feed the dqsupdateen port of the ALTDQ_DQS megafunction. To use this signal, the DQS delay chain must have its dqs_ctrl_latches_enable parameter set to true.


Options Description


Getting Started

Page 5 of the ALTDLL MegaWizard Plug-In Manager lists the simulation model files needed to simulate the generated design files (Figure 2–5). On this page, you can enable the Quartus II software to generate a synthesis area and timing estimation netlist for use by third-party tools.

Figure 2–5. MegaWizard Plug-In Manager – [page 5 of 6]



Page 6 of the ALTDLL MegaWizard Plug-In Manager displays a list of the types of files to be generated. The automatically generated Variation file contains wrapper code in the language you specified on page 2a. On this page, you can specify additional types of files to be generated. Choose from the following file types:

■ Quartus II IP file (<function name>.qip)■ Instantiation template file (<function name>.v)■ Verilog HDL black-box file (<function name>_bb.v)■ AHDL Include file (<function name>.inc)■ VHDL component declaration file <function name>.cmp)■ Quartus II symbol file(<function name>.bsf)

If you selected Generate netlist on page 5, the file for that netlist is also available. A gray checkmark indicates a file that is automatically generated, and a green checkmark indicates an optional file (Figure 2–6).

Figure 2–6. MegaWizard Plug-In Manager – ALTDLL [Summary]


Getting Started

Clear-Box Generator Customization for the ALTDQ_DQS Megafunction

In the Quartus II software version 8.0, the ALTDQ_DQS megafunction is not available in the MegaWizard Plug-In Manager. It is supported only in later versions of the Quartus II software through the MegaWizard Plug-In Manager.

To access the ALTDQ_DQS megafunction, you must use the Clear-Box Generator, a command-line executable. The Clear-Box Generator creates or modifies design files that contain custom megafunction variations, which can then be instantiated in a design file. The Clear-Box Generator allows you to specify options for the ALTDQ_DQS megafunction.

Run the Clear-Box Generator by using the following procedure:

1. Start the command-prompt in your operating system. For the Windows XP operating system, click Start, point to All Programs, Accessories, and click Command Prompt.

1 Alternatively, you can click Start, click Run, type CMD in the Open field, and click OK.

2. Go to the directory where the Clear-Box executable is stored:

<quartusii_install_dir>\quartus\bin\

3. The executable name is clearbox.exe. To use the executable, type the following command:

clearbox altdq_dqs.dll –f *.txt

where *.txt is a text file containing the ports and parameters that you want to generate (Figure 2–7).

Figure 2–7. Accessing the Clear-Box Generator


Clear-Box Generator Options for ALTDQ_DQS Megafunction

Clear-Box Generator Options for ALTDQ_DQS Megafunction

This section describes the options available when you generate design files for the ALTDQ_DQS megafunction with the Clear-Box Generator.

To find out the ports and parameters that are available for this megafunction, type the following command at the command prompt of your operating system: clearbox altdq_dqs.dll -h

Figure 2–8 shows a sample listing of the available ports and parameters for the ALTDQ_DQS megafunction.

Figure 2–8. Available Ports and Parameters for the ALTDQ_DQS Megafunction


Getting Started

Refer to Chapter 3, Specifications of this user guide for detailed descriptions of the available ports and parameters in this megafunction.

To efficiently generate output files for the ALTDQ_DQS megafunction, Altera recommends that you use a text file to pass the required ports and parameters to the Clear-Box Generator. This method promotes reusability and provides an easier way to customize the megafunction. Figure 2–9 shows a sample text file used for the Clear-Box Generator.

Figure 2–9. Sample Text File for Clear-Box Generator

With the text file, you can generate output files using the following command:

clearbox altdq_dqs.dll –f sample_param_test.txt

After the output files are generated, you can instantiate the megafunction module into either a HDL file or a block diagram file in the Quartus II software.

To know the resource usage for a particular configuration in the ALTDQ_DQS megafunction, type the following command.

clearbox altdq_dqs.dll –f sample_param_test.txt –resc_count

Instantiating Megafunctions in HDL Code or Schematic Designs

When you use the MegaWizard Plug-In Manager to customize and parameterize a megafunction, it creates a set of output files that allows you to instantiate the customized function in your design. Depending on the language you choose in the MegaWizard Plug-In Manager, the wizard instantiates the megafunction with the correct parameter values and generates a megafunction variation file (wrapper file) in Verilog HDL (.v), VHDL (.vhd), or AHDL (.tdf), along with other supporting files.


Instantiating Megafunctions in HDL Code or Schematic Designs

The MegaWizard Plug-In Manager provides options to create the following files:

■ A sample instantiation template for the language of the variation file (_inst.v, _inst.vhd, or _inst.tdf)

■ Component Declaration File (.cmp) that can be used in VHDL Design Files

■ ADHL Include File (.inc) that can be used in Text Design Files (.tdf)■ Quartus II Block Symbol File (.bsf) that can be used in schematic

designs■ Verilog HDL module declaration file that can be used when

instantiating the megafunction as a black box in a third-party synthesis tool (_bb.v)

For more information about the wizard-generated files, refer to Quartus II Help or to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.

Generating a Netlist for EDA Tool Use

If you use a third-party EDA synthesis tool, you can instantiate the megafunction variation file as a black box for synthesis. Use the VHDL component declaration or Verilog HDL module declaration black box file to define the function in your synthesis tool, and then include the megafunction variation file in your Quartus II project.

If you enable the option to generate a synthesis area and timing estimation netlist in the MegaWizard Plug-In Manager, the wizard generates an additional netlist file (_syn.v). The netlist file is a representation of the customized logic used in the Quartus II software. The file provides the connectivity of the architectural elements in the megafunction but may not represent true functionality. This information enables certain third-party synthesis tools to better report area and timing estimates. In addition, synthesis tools can use the timing information to focus timing-driven optimizations and improve the quality of results.

For more information about using megafunctions in your third-party synthesis tool, refer to the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.

Using the Port and Parameter Definitions

Instead of using the MegaWizard Plug-In Manager, you can instantiate the megafunction directly in your Verilog HDL, VHDL, or AHDL code by calling the megafunction and setting its parameters as you would any other module, component, or subdesign.


http://www.altera.com/literature/hb/qts/qts_qii51007.pdf


Getting Started

1 Altera strongly recommends that you use the MegaWizard Plug-In Manager for complex megafunctions. The MegaWizard Plug-In Manager ensures that you set all megafunction parameters properly.

For a list of the megafunction ports and parameters, refer to Chapter 3, Specifications.

Identifying a Megafunction after Compilation

During compilation with the Quartus II software, analysis and elaboration are performed to build the structure of your design. To locate your megafunction in the Project Navigator window, expand the compilation hierarchy and find the megafunction by its name.

To search for node names within the megafunction (using the Node Finder), click Browse in the Look in box and select the megafunction in the Hierarchy box.

Simulation The Quartus II Simulator provides an easy-to-use, integrated solution for performing simulations. The following sections describe the simulation options.

Quartus II Simulation

With the Quartus II Simulator, you can perform two types of simulations: functional and timing. A functional simulation enables you to verify the logical operation of your design without taking into consideration the timing delays in the FPGA. This simulation is performed using only your RTL code. When performing a functional simulation, add only signals that exist before synthesis. You can find these signals with the Registers: Pre-Synthesis, Design Entry, or Pin filters in the Node Finder. The top-level ports of megafunctions are found using these three filters.

In contrast, the timing simulation in the Quartus II software verifies the operation of your design with annotated timing information. This simulation is performed using the post place-and-route netlist. When performing a timing simulation, add only signals that exist after place-and-route. These signals are found with the post-compilation filter of the Node Finder. During synthesis and place-and-route, the names of RTL signals change. Therefore, it may be difficult to find signals from your megafunction instantiation in the post-compilation filter.

To preserve the names of your signals during the synthesis and place-and-route stages, use the synthesis attributes keep or preserve. These are Verilog and VHDL synthesis attributes that direct analysis and


Design Example: Using DLL and DQ/DQS Circuitry in Stratix III Devices

synthesis to keep a particular wire, register, or node intact. Use these synthesis attributes to keep a combinational logic node so you can observe the node during simulation.

f For more information about these attributes, refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.

EDA Tool Simulation

The Quartus II Handbook chapters describe how to perform functional and gate-level timing simulations that include the megafunctions, with details about the files that are needed and the directories where the files are located.

Depending on which simulation tool you are using, refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook.


This section presents a design example that uses the DLL and DQ/DQS circuitry for external memory interfaces in Stratix III devices. The memory interface is running at 333.333 MHz with 8-bit bidirectional DQ pins, a 1-bit output DQ pin, and a 1-bit differential DQS pin.

Design Files

The example design files are available in the User Guides section on the Literature page of the Altera® website (www.altera.com).

Procedure

In this example, the following tasks are performed:

■ “Generate the ALTDLL Instantiation” on page 2–16■ “Generate the ALTDQ_DQS Instance” on page 2–18

Generate the ALTDLL Instantiation

To generate the ALTDLL megafunction, perform the following steps:

1. Open the altdll_altdq_dqs_DesignExample_ex1.zip project and extract the altdll_altdq_dqs.qar file.

2. In the Quartus II software, open the altdll_altdq_dqs.qar file and restore the archived file into your working directory.






Getting Started

3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the MegaWizard Plug-In Manager appears.

4. Select Create a new custom megafunction variation.

5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.

6. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 2–3. Click Next to advance from one page to the next.

Table 2–3. Configuration Settings (Part 1 of 2)

MegaWizard Plug-In Manager Page MegaWizard Plug-In Manager Configuration Setting Value

2a Select a megafunction ALTDLL

Which device family will you be using? Stratix III

Which type of output file do you want to create? Verilog HDL

What name do you want for the output file? dll_inst

3 Currently selected family Stratix III

Match project/default Selected

Turn on jtter reduction Not selected

What is the chain delay length? 10

What is the delay buffer mode? High

What is the input frequency? 333 MHz

4 (DLL Offset Control A)

Instantiate DLL offset control Not selected

Use DLL offset Not selected

DLL static offset Not selected

(DLL Offset Control B)

Instantiate DLL offset control Not selected

Use DLL offset Not selected

DLL static offset Not selected

(Optional Ports)

Create a dll_aload port Not selected

Create a dll_dqsupdate port Not selected

5 Generate netlist Not selected



7. Click Finish.

1 If the Quartus II IP Files dialog box appears with an option to add the Quartus II IP file (.qip) to your project, click Yes.

The ALTDLL module is now built.

8. Browse to your working directory and open the input.txt file.

9. Change the value of the CBX_OUTPUT_DIRECTORY parameter to the path of your working directory.

10. Save the file.

11. Copy the input.txt file to the <quartusii_install_dir>\quartus\bin\ directory.

Generate the ALTDQ_DQS Instance

To generate the ALTDQ_DQS instance, perform the following steps:

1. Start up the command-prompt in your operating system.

2. Change to the directory where the Clear-Box executable is stored:

<quartusii_install_dir>\quartus\bin\

3. Run the following command to generate the dq_dqs_inst.v file in your working directory.

clearbox altdq_dqs.dll –f input.txt

6 Variation file Selected

Quartus II IP file Selected

Instantiation template file Selected

Verilog HDL black-box file Selected

AHDL include file Selected

VHDL component declaration file Selected

Quartus II symbol file Selected

Table 2–3. Configuration Settings (Part 2 of 2)

MegaWizard Plug-In Manager Page MegaWizard Plug-In Manager Configuration Setting Value


Getting Started

4. In the Quartus II software, on the Project menu, click Add/Remove Files in Project.

5. In the Category list, select Files.

6. Next to the File name box, click the icon to browse to your working directory. Select the dll_inst.v file and click Open.

7. The file name that you just selected appears in the File name box. Click Add to add the file to your project.

8. Perform steps 6 and 7 for both the dq_dqs_inst.v and test_dq_dqs.bdf files.

9. Click OK.

10. On the File menu, click Save.

11. On the Processing menu, click Start Compilation to compile the design. After compilation, you can view how the design is implemented using the RTL Viewer. You can also view the resource usage in the Compilation Reports.

Figure 2–10 shows a block diagram of the design example, which consists of six blocks.


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Figure 2–10. Block Diagram of Design Example

Getting Started

Table 2–4 provides the description for each block in the design example.

Functional Simulation in the ModelSim-Altera Simulator

Simulate the design in the ModelSim®-Altera software to generate a waveform display of the device behavior.

Table 2–4. Blocks in Design Example

Block Name Description

pll_inst:inst1 This block represents the Stratix III PLL. Its settings are as follows:inclk = 200 MHzc0 = 3000 ps, 50% duty cyclec1 = 3000 ps, 50% duty cyclec2 = 3000 ps, 50% duty cyclec3 = 6000 ps, 50% duty cycle

dll_inst:inst5 This block represents the DLL circuitry used during a read from the external memory and is clocked by the PLL. Its settings are as follows:delay chain length = 10 delay buffer mode = Highinput frequency = 333 MHz jitter reduction = False

dq_dqs_inst:inst This block represents the DQ and DQS circuitry, which is used to interface with the external memory. The settings are specified in the input.txt file. The block is customized for a half-rate operation and represents the interface between the FPGA core and the I/O buffers that are connected to the external memory pins.

dqs_iobuf_inst:inst2 This block represents the bidirectional I/O buffer, which is used as the DQS strobe/clock signal for interfacing with the external memory. This block is in differential mode and is 1 bit wide. It is connected to the dq_dqs_inst block.

bidir_dq_iobuf_inst:inst3 This block represents the bidirectional I/O buffer, which is used as the DQ data signals for interfacing with the external memory. This block is 8 bits wide. It is connected to the dq_dqs_inst block.

output_dq_iobuf_inst:inst4 This block represents the output I/O buffer, which is used as the DQ data signals for interfacing with the external memory. This block is 1 bit wide. It is connected to the dq_dqs_inst block.



You should be familiar with the ModelSim-Altera software before trying out the design example. If you are unfamiliar with the ModelSim-Altera software, refer to the support page for software products on the Altera website (www.altera.com). On the support page, there are links to such topics as installation, usage, and troubleshooting.

Set up and simulate the design in the ModelSim-Altera software by performing the following steps:

1. Unzip the altdll_altdq_dqs_ex1_msim.zip file to any working directory on your PC.

2. Start the ModelSim-Altera software.

3. On the File menu, click Change Directory.

4. Select the folder in which you unzipped the files.

5. Click OK.

6. On the Tools menu, click Execute Macro.

7. Select the altdll_altdq_dqs_ex1_msim.do file and click Open. This is a script file for the ModelSim-Altera software to automate all the necessary settings for the simulation.

8. Verify the results shown in the Wave window.

You can rearrange signals, remove signals, and add signals, change the radix by modifying the script in the altdll_altdq_dqs_ex1_msim.do file.

Understanding the Simulation Results

The simulation begins when the PLL is locked, as indicated by the assertion of the locked signal at 225,000 ps (refer to Figure 2–11). At this point, the PLL input frequency, as indicated by the inclk0 signal, is 200 MHz.



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Figure 2–11. Data Transfer from FPGA Core to Bidirectional DQ Pin with No Delay Chains Activated


The simulation has four output ports: c0, c1, c2, and c3. The c0, c1, and c2 ports generate a 333.333-MHz clock output; the c3 port generates a 166.666-MHz clock output.

1 This design example uses the half-rate option, which means that the FPGA core sends out and receives data from the external memory interface at a half-rate of 166.666 MHz. The pin that interfaces with the memory toggles at 333.333 MHz. However, as this pin is also toggled by a DDIO_OUT signal, the data throughput is 666.666 Mbps.

For half-rate interfaces, every I/O pin—whether bidirectional, input, or output—corresponds to four data paths in the FPGA core and two output-enable (OE) paths. This design example has the following pins:

■ An 8-bit bidirectional DQ pins■ A 1-bit bidirectional DQS pin (differential)■ A 1-bit DQ output pin

The output path from the FPGA core to the bidirectional DQ pin is represented by a 32-bit input, bidir_dq_hr_output_data_in[31:0]. The input path from the bidirectional pin to the FPGA core is represented by a 32-bit output, bidir_dq_hr_input_data_out[31:0]. The OE path from the FPGA core to the bidirectional buffer, bidir_dq_hr_oe_in[15:0], is 16 bits wide and set to active-low.

The output path from the FPGA core to the bidirectional DQS pin is represented by a 4-bit input, dqs_hr_output_data_in[3:0]. The OE path is 2 bits wide from the FPGA core to the bidirectional buffer, dqs_hr_oe_in [1:0]. The input path of the DQS pin goes through a specialized circuitry to clock the 8-bit bidirectional DQ pin input paths.

For the DQ output pin, the output path in the FPGA core to the bidirectional DQ pin is represented by a 4-bit input, output_dq_hr_output_data_in [3:0]. The OE path is 2 bits wide from the FPGA core to the bidirectional buffer, output_dq_hr_oe_in[1:0].

1 In the first part of the simulation, only output paths are used; therefore, bidir_dq_hr_oe_in[15:0] = 16’b0 and dqs_hr_oe_in [1:0] = 2’b0.

For bidir_dq_hr_output_data_in[31:0], each bit is toggled with a 10-MHz data signal from 100 ns to 300 ns.


Getting Started

This behavior is represented in the waveform in groups of 4-bit signals (for example, bidir_dq_hr_output_data_in[3:0]), as the four input paths are connected to the bidir_dq_io[0] pin.

The bidir_dq_hr_output_data_in[3] and bidir_dq_hr_output_data_in[2] signals go through the DDIO_OUT port, which is clocked at 166.666 MHz by the c3 PLL clock output. At the same time, the bidir_dq_hr_output_data_in[1] and bidir_dq_hr_output_data_in[0] signals go through another DDIO_OUT port, which is clocked at 166.666 MHz by the c3 PLL clock output. Both outputs (bidir_dq_0_output_hr_ddio_out_high_inst/dataout and bidir_dq_0_output_hr_ddio_out_low_inst/dataout) of the previous DDIO_OUT ports are channeled into another DDIO_OUT port, which is clocked at 333.333 MHz by the c1 PLL clock output. The output bidir_dq_0_output_ddio_out_inst/dataout is then connected to output_delay_chain_1. After that, the output bidir_dq_0_output_delay_chain1_inst/dataout is connected to output_delay_chain_2, and the output bidir_dq_0_output_delay_chain2_inst/dataout is connected to the bidir_dq_io[0] pin.

The same data is propagated through the other inputs of bidir_dq_hr_output_data_in[31:4] , which causes the bidir_dq_io[7:1] pins to toggle in the same manner.

1 The throughput of data going out on each pin to the external memory is 666.666 Mbps.

1 The output delay chains are disabled.

The dqs_hr_output_data_in[3:0], dqs_hr_output_data_in[3] and dqs_hr_output_data_in[2] signals are toggled with a constant value of 1’b1. After that, the dqs_hr_output_data_in[1] and dqs_hr_output_data_in[0] signals are toggled with a constant value of 1’b0. The signals are toggled at a constant rate to generate the necessary DQS write strobe/clock signals, which are sent together with the DQ write data to the external memory.

As the throughput of the data is sent at 666.666 Mbps, the DQS write strobe/clock signal is a 333.333-MHz DDR clock signal. To obtain such a signal, the dqs_hr_output_data_in[3] and dqs_hr_output_data_in[2] signals go through a DDIO_OUT port, which is clocked at 166.666 MHz by the c3 PLL clock output. At the same time, the dqs_hr_output_data_in[1] and dqs_hr_output_data_in[0] signals go through another DDIO_OUT



port, which is clocked at 166.666 MHz by the c3 PLL clock output. Then, both outputs (dqs_output_hr_ddio_out_high_inst/dataout and dqs_output_hr_ddio_out_low_inst/dataout) of the previous DDIO_OUT ports are channeled into another DDIO_OUT port, which is clocked at 333.333 MHz by the c1 PLL clock output. The output dqs_output_ddio_out_inst/dataout is then connected to output_delay_chain_1. The output dqs_output_delay_chain1_inst/dataout is connected to output_delay_chain_2. Next, the output dqs_output_delay_chain2_inst/dataout is connected to the dqs_io pin, which acts as a 333.333-MHz DQS write strobe/clock signal.

Figures 2–12 to 2–15 show the same write sequences to the external memory, but with different delay chain values on the two output delay chains. You can get the delay chain values by analyzing the timing paths of the following signals in each figure:

■ bidir_dq_0_output_hr_ddio_out_high_inst/dataout■ bidir_dq_0_output_hr_ddio_out_low_inst/dataout■ bidir_dq_0_output_ddio_out_inst/dataout■ bidir_dq_0_output_delay_chain1_inst/dataout■ bidir_dq_0_output_delay_chain2_inst/dataout■ bidir_dq_io[0]

f For details about dynamically changing the delay chain values, refer to the I/O Buffer (ALTIO) Megafunction User Guide.

Figures 2–16 and 2–17 show the read process from the external memory, but with different delay chain values on the input delay chains.



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Figure 2–12. Data Transfer from FPGA Core to Bidirectional DQ Pin with 50-ps Delay Chain Activated

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Figure 2–16. Data Transfer from Bidirectional DQ Pin to FPGA Core with 50-ps Delay Chain Activated

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Figure 2–17. Data Transfer from Bidirectional DQ Pin to FPGA Core with 750-ps Delay Chain Activated

Getting Started

In Figure 2–16, only the input paths are used; therefore, bidir_dq_hr_oe_in[15:0] = 16’b1 and dqs_hr_oe_in[1:0] = 2’b1 from 5 µs onwards.

Each bit in the bidir_dq_io[7:0] pin is toggled with a 10-MHz data signal from 5.25 µs to 5.45 µs. The pin behavior is represented in the waveform in groups of 4-bit signals because the bidir_dq_io[0] input is connected to the bidir_dq_hr_input_data_out[3:0] outputs.

1 The interface to the external memory has a throughput of 666.666 Mbps during the read process.

Initially, the bidir_dq_io[0] pin is connected to the input delay chain. Then, the output bidir_dq_0_input_delay_chain_inst/dataout of the delay chain is connected to the input of the DDIO_IN port, which is clocked by a specialized DQS circuitry that uses the DLL.

Next, the outputs (bidir_dq_0_ddio_in_inst/regouthi and bidir_dq_0_ddio_in_inst/regoutlo) of the previous DDIO_IN ports are channeled to two input phase alignment (IPA) blocks, respectively. These IPA blocks are clocked at 333.333 MHz by the c2 clock output of the PLL. The outputs of the two IPAs, bidir_dq_0_ipa_high_inst/dataout and bidir_dq_0_ipa_low_inst/dataout, are channeled to a half-rate input block, which is clocked by the IO_CLOCK_DIVIDER blocks. The output bidir_dq_0_half_rate_input_inst/dataout[3:0] of this block is then connected to the bidir_dq_hr_input_data_out[3:0] outputs.

The same data is propagated through the other bidirectional pins of bidir_dq_io[7:1], which causes the bidir_dq_hr_input_data_out[31:4] outputs to toggle in the same manner in the FPGA core.

1 The throughput of data in the output ports are at a half-rate of 166.666 MHz.

1 The input delay chains are enabled.


Conclusion

You can get the delay chain values by analyzing the timing paths of the following signals in Figure 2–16 on page 2–31 and Figure 2–17 on page 2–32:

■ bidir_dq_io[0]■ bidir_dq_0_input_delay_chain_inst/dataout■ bidir_dq_0_ddio_in_inst/regouthi■ bidir_dq_0_ddio_in_inst/regoutlo

Conclusion The Quartus II software provides the ALTDLL and ALTDQ_DQS parameterizable megafunctions to create custom external memory interfaces to transfer data between the external memory and user logic. These megafunctions are performance-optimized for Altera devices and therefore, provide more efficient logic synthesis and device implementation, because they automate the coding process and save valuable design time. Altera recommends using these functions during design implementation so you can consistently meet your design goals.


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Chapter 3. Specifications

Ports and Parameters

This chapter describes the ports and parameters of the ALTDLL and ALTDQ_DQS megafunctions. These ports and parameters are available to customize the ALTDLL and ALTDQ_DQS megafunctions according to your application.

The parameter details are only relevant if you bypass the MegaWizard® Plug-In Manager interface and use the megafunction as a directly parameterized instantiation in your design. The details of these parameters are hidden if you use the MegaWizard Plug-In Manager interface.

ALTDLL Megafunction

Tables 3–1 to 3–3 show the ports and parameters for the ALTDLL megafunction. Tables 3–4 to 3–6 show the ports and parameters for the ALTDQ_DQS megafunction. Table 3–7 shows the offset usage for the ALTDLL megafunction.

Table 3–1 lists the input ports for the ALTDLL megafunction.

Table 3–1. ALTDLL Megafunction Input Ports (Part 1 of 2)

Port Name Required Description Comments

dll_clk Yes DLL reference clock This is the reference clock that matches the frequency of the DQS clock used to determine the delay for the phase shift. This input must be fed by an input pin or a PLL output. This input defaults to GND. This input must match the polarity of its source and cannot be inverted.

dll_aload No Asynchronous load signal for the delay-locked loop (DLL) counter

When dll_aload is HIGH, the counter is asynchronously loaded with the initial delay setting of 16 in low-frequency mode (when parameter DELAY_BUFFER_MODE is set to LOW), or 32 in high-frequency mode (when parameter DELAY_BUFFER_MODE is set to HIGH). This input defaults to GND.

ential—Internal Use Only 3–1ALTDLL and ALTDQ_DQS Megafunctions User Guide

ALTDLL Megafunction

dll_offset_ctrl_a_offset[5..0]

No Offset input setting for DLL_OFFSET_CTRL_A block

This is a Gray-coded offset added or subtracted from the current value of the DLL's delay setting to get the dll_offset_ctrl_a_offsetctrlout result. This input is ignored if the DLL_OFFSET_CTRL_A_USE_OFFSET parameter is set to FALSE. The offset is limited to a minimum value of 0 and a maximum value of 63 in low-frequency mode, and a maximum value of 31 in high-frequency mode. This input defaults to 0.

dll_offset_ctrl_a_addnsub

No Addition/subtraction control port for DLL_OFFSET_CTRL_A block

This port controls whether the delay-offset setting A is added or subtracted. This input is ignored if the DLL_OFFSET_CTRL_A_USE_OFFSET parameter is set to FALSE. If the input is VCC, the offset is added; if it is GND, the offset is subtracted. This input defaults to VCC.

dll_offset_ctrl_b_offset[5..0]

No Offset input setting for DLL_OFFSET_CTRL_B block

This is a Gray-coded offset added or subtracted from the current value of the DLL's delay setting to get the dll_offset_ctrl_b_offsetctrlout result. This input is ignored if the DLL_OFFSET_CTRL_B_USE_OFFSET parameter is set to FALSE. The offset is limited to a minimum value of 0 and a maximum value of 63 in low-frequency mode, and a maximum value of 31 in high-frequency mode.This input defaults to 0.

dll_offset_ctrl_b_addnsub

No Addition/subtraction control port for DLL_OFFSET_CTRL_B block

This port controls whether the delay-offset setting B is added or subtracted. This input is ignored is the DLL_OFFSET_CTRL_B_USE_OFFSET parameter is set to FALSE. If the input is VCC, the offset is added; if it is GND, the offset is subtracted. This input defaults to VCC.

Table 3–1. ALTDLL Megafunction Input Ports (Part 2 of 2)



Specifications

Table 3–2 lists the output ports of the ALTDLL megafunction.

Table 3–2. ALTDLL Megafunction Output Ports


dll_delayctrlout[5..0] Yes DLL's delay setting output

This is a 1-cycle-delayed value of the current delay chain setting of the DLL. This signal is Gray-coded to minimize jitter due to toggling.This signal can feed the dll_delayctrlin input port of the ALTDQ_DQS megafunction or the core logic. This output is available for the SignalTap® II Embedded Logic Analyzer.

dll_dqsupdate No Update-enable signal This is an update-enable signal for the delay-setting latches of the DQS pins. This signal can feed the dqsupdateen input port of the ALTDQ_DQS megafunction. This output is not available for the SignalTap II Embedded Logic Analyzer.

dll_offset_ctrl_a_offsetctrlout[5..0]

No The offsetctrlout output setting for DLL_OFFSET_CTRL_A block

This is a registered Gray-coded value of the delay-offset setting A. This output can be adjusted based on the value of the dll_offset_ctrl_a_use_offset parameter. This signal can feed the offsetctrlin input port of the ALTDQ_DQS megafunction. This signal is not available for the SignalTap II Embedded Logic Analyzer.

dll_offset_ctrl_b_offsetctrlout[5..0]

No The offsetctrlout output setting for DLL_OFFSET_CTRL_B block

This is a registered Gray-coded value of the delay-offset setting B. This output can be adjusted based on the value of the dll_offset_ctrl_b_use_offset parameter. This signal can feed the offsetctrlin input port of the ALTDQ_DQS megafunction. This signal is not available for SignalTap II Embedded Logic Analyzer.


ALTDLL Megafunction

Table 3–3 lists the parameters for the ALTDLL megafunction.

Table 3–3. ALTDLL Megafunction Parameters (Part 1 of 3)

Parameter Name Type Required Description

DELAY_BUFFER_MODE String No Determines whether the DLL delay buffers are working in low-frequency mode or high-frequency mode. Available values are LOW and HIGH. The default value is LOW.

DELAY_CHAIN_LENGTH Integer No This parameter represents the number of delay buffers in the delay loop. The available values are 6, 8, 10, 12, 16. This parameter defaults to 12. For DLL frequency range specifications, refer to the DC & Switching Characteristics of Stratix III Devices chapter in the Stratix III Device Handbook.For DLL frequency modes, refer to the External Memory Interfaces in Stratix III Devices chapter in the Stratix III Device Handbook.

DLL_OFFSET_CTRL_A_STATIC_OFFSET

String No This is a Gray-coded signed integer expressed as a string with a range from –63 to 63. If the DLL_OFFSET_CTRL_A_USE_OFFSET parameter is set to FALSE, the value is added to the DLL delay-setting value and appears as output on the dll_offset_ctrl_a_offsetctrlout[5..0] output bus. If the DLL_OFFSET_CTRL_A_USE_OFFSET parameter is set to TRUE, this value is ignored. The default value is 0.

DLL_OFFSET_CTRL_A_USE_OFFSET

String No Available values are TRUE and FALSE. It determines the output of the dll_offset_ctrl_a_offsetctrlout [5..0] output bus. If set to TRUE, then depending on whether the dll_offset_ctrl_a_addnsub input is asserted or not, the phase offset specified on the dll_offset_ctrl_a_offset[5..0] input bus is added or subtracted from the DLL delay setting output to get the dll_offset_ctrl_a_offsetctrlout[5..0] output. If set to FALSE, the phase offset specified by the DLL delay setting to get the dll_offset_ctrl_a_offsetctrlout[5..0] output. If omitted, the default is FALSE.






Specifications

DLL_OFFSET_CTRL_B_STATIC_OFFSET

String No This is a Gray-coded signed integer expressed as a string with a range from –63 to 63. If the DLL_OFFSET_CTRL_B_USE_OFFSET parameter is set to FALSE, the value is added to the DLL delay-setting value and appears as output on the dll_offset_ctrl_a_offsetctrlout[5..0] output bus. If the DLL_OFFSET_CTRL_B_USE_OFFSET parameter is set to TRUE, this value is ignored. The default value is 0.

DLL_OFFSET_CTRL_B_USE_OFFSET

String No Available values are TRUE and FALSE. It determines the output of the dll_offset_ctrl_b_offsetctrlout[5..0] output bus. If set to TRUE, then depending on whether the dll_offset_ctrl_b_addnsub input is asserted or not, the phase offset specified on the dll_offset_ctrl_b_offset[5..0] input bus is added or subtracted from the DLL delay setting output to get the dll_offset_ctrl_b_offsetctrlout[5..0] output. If set to FALSE, the phase offset specified by the DLL delay setting to get the dll_offset_ctrl_b_offsetctrlout[5..0] output. If omitted, the default is FALSE

INPUT_FREQUENCY String Yes This is the frequency of the clock connected to the clk input port. Check this parameter value to ensure that it falls within a valid range. This field is required and defaults to 0.You can specify a duration by placing a time unit after the value (e.g., 2.5 ns). The value is in floating-point format with no decimal point limit.

JITTER_REDUCTION String No Available values are TRUE and FALSE. If set to TRUE, the jitter reduction circuit is enabled on the dll_delayctrlout[5..0], and dll_offset_ctrl_a_offsetctrlout[5..0] or dll_offset_ctrl_b_offsetctrlout[5..0] outputs and the DLL may require up to 1024 clock cycles to lock. If set to FALSE, the jitter reduction circuit is disabled and the DLL only requires up to 256 clock cycles to lock. If omitted, the default is FALSE.




ALTDQ_DQS Megafunction


Table 3–4 lists the input ports for the ALTDQ_DQS megafunction.

USE_DLL_OFFSET_CTRL_A

String No Specifies whether to instantiate DLL_OFFSET_CTRL_A block. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DLL_OFFSET_CTRL_B

String No Specifies whether to instantiate DLL_OFFSET_CTRL_B block. Values are TRUE and FALSE. If omitted, the default is FALSE.



Table 3–4. ALTDQ_DQS Megafunction Input Ports (Part 1 of 8)

Port Name

Requ

ired

Description Comments

config_clk No Clock signal for configuration shift register

This input connects to the clk port of the DQS_CONFIG and IO_CONFIG blocks. This input must match the polarity of its source and cannot be inverted. This input defaults to GND.

config_datain No Data input shifted into the configuration shift register

This input connects to the datain port of the DQS_CONFIG and IO_CONFIG blocks. This input must match the polarity of its source and cannot be inverted. This input defaults to GND.

config_update No Series to parallel update signal for the configuration shift register

This signal loads the bits in the shift registers to the configuration registers of the DQS_CONFIG and IO_CONFIG blocks. This input must match the polarity of its source and cannot be inverted. This input defaults to GND.

core_delayctrlin[5..0] No Gray-coded delay chain setting for the DQS read path

This input connects to the delayctrlin port of the DQS_DELAY_CHAIN block if the value of the DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE parameter is CORE. This input can only be fed by the core logic. This input defaults to GND.


Specifications

dll_delayctrlin[] No Gray-coded delay chain setting for the DQS read path

This input connects to the delayctrlin port of the DQS_DELAY_CHAIN block if the value of the DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE parameter is DLL. It also connects to the delayctrlin port of the IO_CLOCK_DIVIDER, DQS_ENABLE, and INPUT_PHASE_ALIGNMENT blocks. This input can be fed by only the delayctrlout output of a DLL and must match the polarity of its source and cannot be inverted. This input defaults to GND.

dq_input_reg_clk No Clock input for DQ input register

This input connects to the clk port of the INPUT_FF and DDIO_IN blocks for the BIDIR_DQ and INPUT_DQ I/O pins. This input defaults to GND.

dq_input_reg_clkena

No Clock-enable input for DQ input register

This input connects to the ena port of the INPUT_FF and DDIO_IN blocks for the BIDIR_DQ and INPUT_DQ I/O pins.This input defaults to GND.

dq_ipa_clk No Clock input for DQ INPUT_PHASE_ALIGNMENT block

This input connects to the clk port of the INPUT_PHASE_ALIGNMENT blocks for the BIDIR_DQ and INPUT_DQ I/O pins. This input defaults to GND.

dqs_areset No Asynchronous-reset port for the DQS I/O pin

This input defaults to GND.

dqs_config_ena No Clock-enable signal for DQS_CONFIG block

This input must match the polarity of its source and cannot be inverted.This input defaults to VCC.

dqs_enable_ctrl_clk

No Clock input for DQS_ENABLE_CTRL block

This input must match the polarity of its source and cannot be inverted.This input defaults to VCC.

dqs_enable_ctrl_hr_datainhi

No Half-rate input signal (high) for enabling or disabling the DQS_ENABLE block

—

dqs_enable_ctrl_hr_datainlo

No Half-rate input signal (low) for enabling or disabling the DQS_ENABLE block

—


Port Name

Requ

ired




dqs_enable_ctrl_in No Full-rate input signal for enabling or disabling the DQS_ENABLE block

This input defaults to VCC.

dqs_enable_in No Input signal for enabling or disabling the output of the DQS_DELAY_CHAIN block

This input must match the polarity of its source and cannot be inverted. When the value of this input is VCC, the DQS_ENABLE block becomes transparent to the output of the DQS_DELAY_CHAIN block. When the value of this input is GND, the DQS_ENABLE grounds the output of the DQS_DELAY_CHAIN block on its next falling edge.This input defaults to GND.

dqs_hr_oct_in[] No Half-rate input signal to the dynamic termination control path of the DQS I/O pin


dqs_hr_oe_in[] No Half-rate input signal to the output-enable path of the DQS I/O pin


dqs_hr_output_data_in[] No Half-rate input signal to the output path of the DQS I/O pin


dqs_input_data_in No DQS input signal —

dqs_io_config_ena No Clock-enable signal for IO_CONFIG block of the DQS I/O pin

This input must match the polarity of its source and cannot be inverted. This input defaults to VCC.

dqs_oct_in No Full-rate input signal to the dynamic termination control path of the DQS I/O pin


dqs_oe_in No Full-rate input signal to the output-enable path of the DQS I/O pin


dqs_output_data_in No Full-rate input signal to the output path of the DQS I/O pin

This port is a full-rate input to the output path of the DQS I/O pin when the DQS_OUTPUT_REG_MODE is set to FF or NONE. This input defaults to GND.

dqs_output_data_in_high No Full-rate input signal to the output path of the DQS I/O pin

This port is a full-rate input to the output path of the DQS I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO. This input defaults to GND.


Port Name

Requ

ired



Specifications

dqs_output_data_in_low

No Full-rate input signal to the output path of the DQS I/O pin

This port is a full-rate input to the output path of the DQS I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO.This input defaults to GND.

dqs_output_reg_clk No Clock input for the DQS output and output-enable registers


dqs_output_reg_clkena No Clock-enable input for the DQS output and output-enable registers

This input defaults to VCC.

dqs_sreset No Synchronous reset port for the DQS I/O pin


dqsn_areset No Asynchronous reset port for the DQSn I/O pin


dqsn_hr_oct_in[] No Half-rate input signal to the dynamic termination control path of the DQSn I/O pin


dqsn_hr_oe_in[] No Half-rate input signals to the output-enable path of the DQSn I/O pin

—

dqsn_hr_output_data_in[]

No Half-rate input signal to the output path of the DQSn I/O pin


dqsn_input_data_in No Data input port for the incoming DQSn signal


dqsn_io_config_ena No Clock-enable signal for IO_CONFIG block of the DQS I/O pin

This input must match the polarity of its source and cannot be inverted.The input defaults to VCC.

dqsn_oct_in No Full-rate input signal to the dynamic termination control path of the DQSn I/O pin


dqsn_oe_in No Full-rate input signal to the output-enable path of the DQSn I/O pin


dqsn_output_data_in No Full-rate input signal to the output path of the DQSn I/O pin

This port is a full-rate input to the output path of the DQSn I/O pin when the DQS_OUTPUT_REG_MODE is set to FF or NONE. The input defaults to GND.


Port Name

Requ

ired




dqsn_output_data_in_high

No Full-rate input signal to the output path of the DQSn I/O pin

This port is a full-rate input to the output path of the DQSn I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO. The input defaults to GND.

dqsn_output_data_in_low

No Full-rate input signal to the output path of the DQSn I/O pin

This port is a full-rate input to the output path of the DQSn I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO. The input defaults to GND.

dqsn_sreset No Synchronous reset port for the DQSn I/O


dqsupdateen No Enable signal for the delayctrlin and offsetctrlin latches in the DQS_DELAY_CHAIN block

The dqsupdateen port can be fed by the dqsupdate output of a DLL or the core. The dqsupdateen port does not need to match the polarity of its source and can be inverted except when it is fed by the dqsupdate output of a DLL.

input_dq_areset[] No Asynchronous reset for the INPUT_DQ I/O pin


input_dq_input_data_in[]

No Input signal to the INPUT_DQ data path


input_dq_io_config_ena[]

No Clock-enable signal for the IO_CONFIG block of the INPUT_DQ I/O pin

This input must match the polarity of its source and cannot be inverted. The input defaults to VCC.

input_dq_sreset[] No Synchronous reset for the INPUT_DQ I/O pin


io_clock_divider_clk No Clock input for the IO_CLOCK_DIVIDER block

This input is required when the parameter IO_CLOCK_DIVIDER_CLK_SOURCE is set to CORE. This input does not need to match the polarity of its source and can be inverted. The input defaults to GND.

io_clock_divider_masterin

No Input signal used for chaining the IO_CLOCK_DIVIDER blocks

This input must be connected to the io_clock_divider_slaveout output of the ALTDQ_DQS instance to which the current instance is being chained.

oct_reg_clk No Clock input for the OCT registers



Port Name

Requ

ired



Specifications

offsetctrlin[] No Gray-coded fine-tune delay chain setting for the DQS read path

This input can only be fed by the offsetctrlout output of a DLL_OFFSET_CTRL block. This input must match the polarity of its source and cannot be inverted. This input defaults to GND.

output_dq_areset[] No Asynchronous reset for the OUTPUT_DQ I/O pin


output_dq_hr_oct_in[]

No Half-rate input signal to the dynamic termination control path of the OUTPUT_DQ I/O pin


output_dq_hr_oe_in[] No Half-rate input signal to the output-enable path of the OUTPUT_DQ I/O pin


output_dq_hr_output_data_in[]

No Half-rate input signal to the output path of the OUTPUT_DQ I/O pin


output_dq_io_config_ena[]

No Clock-enable signal for IO_CONFIG block of the OUTPUT_DQ I/O pin

Input port [no-1..0] wide. The output_dq_io_config_ena port must match the polarity of its source and cannot be inverted. The output_dq_io_config_ena port is available for the DQS_CONFIG and IO_CONFIG blocks. If omitted, the default value is VCC.

output_dq_oct_in[] No Full-rate input signal to the dynamic termination control path of the OUTPUT_DQ I/O pin


output_dq_oe_in[] No Full-rate input signal to the output-enable path of the OUTPUT_DQ I/O pin


output_dq_output_data_in[]

No Full-rate input signal to the output path of the OUTPUT_DQ I/O pin

This port is a full-rate input to the output path of the OUTPUT_DQ I/O pin when the DQS_OUTPUT_REG_MODE is set to FF or NONE.

output_dq_output_data_in_high[]


This port is a full-rate input to the output path of the OUTPUT_DQ I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO. This input defaults to GND.


Port Name

Requ

ired




output_dq_output_data_in_low


This port is a full-rate input to the output path of the OUTPUT_DQ I/O pin when the DQS_OUTPUT_REG_MODE is set to DDIO. This input defaults to GND.

output_dq_sreset[] No Synchronous reset for OUTPUT_DQ I/O pin


dqs_hr_output_reg_clk

No Clock port for the half-rateDQS output register


hr_oct_reg_clk No Clock port for the half-rate OCT register


dq_output_reg_clk No Clock port for the BIDIR_DQ and OUTPUT_DQ output register


bidir_dq_areset[] No Asynchronous reset for the BIDIR_DQ I/O pin


bidir_dq_hr_oct_in[] No Half-rate input signal to the dynamic termination control path of the BIDIR_DQ I/O pin

—

bidir_dq_hr_oe_in[] No Half-rate input signal to the output-enable path of the BIDIR_DQ I/O pin

—

bidir_dq_hr_output_data_in[]

No Half-rate input signal to the output path of the BIDIR_DQ I/O pin

—

bidir_dq_input_data_in[]

No Input signal to the input path of the BIDIR_DQ I/O pin

—

bidir_dq_io_config_ena[]

No Clock-enable signal for the IO_CONFIG block of the BIDIR_DQ I/O pin

This input defaults to VCC. This input must match the polarity of its source and cannot be inverted.

bidir_dq_oct_in[] No Full-rate input signal to the dynamic termination control path of the BIDIR_DQ I/O pin


bidir_dq_oe_in[] No Full-rate input signal to the output-enable path of the BIDIR_DQ I/O pin.



Port Name

Requ

ired



Specifications

bidir_dq_output_data_in[]

No Full-rate input signal to the output path of the BIDIR_DQ I/O pin

This input defaults to GND. This port is a full-rate input to the output path of the BIDIR_DQ I/O pin when the DQS_OUTPUT_REG_MODE parameter is set to FF or NONE.

bidir_dq_output_data_in_high[]

No Full-rate input signal to the output path of the BIDIR_DQ I/O pin

This input defaults to GND. This port is a full-rate input to the output path of the BIDIR_DQ I/O pin when the DQS_OUTPUT_REG_MODE parameter is set to DDIO.

bidir_dq_output_data_in_low[]

No Full-rate input signal to the output path of the BIDIR_DQ I/O pin.

This input defaults to GND. This port is a full-rate input to the output path of the BIDIR_DQ I/O pin when the DQS_OUTPUT_REG_MODE parameter is set to DDIO.

bidir_dq_sreset[] No Synchronous reset for the BIDIR_DQ I/O pin



Port Name

Requ

ired




Table 3–5 lists the output ports of the ALTDQ_DQS megafunction.

Table 3–5. ALTDQ_DQS Megafunction Output Ports (Part 1 of 2)

Port Name Required Description

dqs_bus_out No Delayed output signal from the input path of the DQS I/O pin.

dqs_oe_out No Output signal from the output-enable path of the DQS I/O pin.

dqs_output_data_out No Output signal from the output path of the DQS I/O pin.

dqsn_bus_out No Delayed output signal from the input path of the DQSn I/O pin.

dqsn_input_data_out No Output signal from the input path of the DQSn I/O pin.

dqsn_oct_out No Output signal from the dynamic termination control path of the DQSn I/O pin.

dqsn_oe_out No Output signal from the output-enable path of the DQSn I/O pin.

dqsn_output_data_out No Output signal from the output path of the DQSn I/O pin.

input_dq_hr_input_data_out[]

No Half-rate output signal from the input path of the INPUT_DQ I/O pin.

input_dq_input_data_out[]

No Full-rate output signal from the input path of the INPUT_DQ I/O pins when the DQ_INPUT_REG_MODE parameter is set to NONE or FF.

input_dq_input_data_out_high[]

No Full-rate output signal from the input path of the INPUT_DQ I/O pins when the DQ_INPUT_REG_MODE parameter is set to DDIO.

input_dq_input_data_out_low[]

No Full-rate output signal from the input path of the INPUT_DQ I/O pins when the DQ_INPUT_REG_MODE parameter is set to DDIO.

io_clock_divider_clkout[]

No Output of the IO_CLOCK_DIVIDER blocks.

io_clock_divider_slaveout

No Output signal used for chaining the IO_CLOCK_DIVIDER blocks.This output must be connected to the io_clock_divider_masterin input of the ALTDQ_DQS instance to which the current instance is being chained.

output_dq_oct_out[] No Output signal from the dynamic termination control path of the OUTPUT_DQ I/O pins.

output_dq_output_data_out[]

No Output signal from the output path of the OUTPUT_DQ I/O pins.

dqs_oct_out No Output signal from the dynamic termination control path of the DQS I/O pins.

output_dq_oe_out[] No Output signal from the output-enable path of the OUTPUT_DQ I/O pins.

bidir_dq_hr_input_data_out[]

No Half-rate output signal from the input path of the BIDIR_DQ I/O pin.

bidir_dq_input_data_out[]

No Full-rate output signal from the input path of the BIDIR_DQ I/O pin when the DQ_INPUT_REG_MODE parameter is set to NONE or FF.


Specifications

bidir_dq_input_data_out_high[]

No Full-rate output signal from the input path of the BIDIR_DQ I/O pin when the DQ_INPUT_REG_MODE parameter is set to DDIO.

bidir_dq_input_data_out_low[]

No Full-rate output signal from the input path of the BIDIR_DQ I/O pin when the DQ_INPUT_REG_MODE parameter is set to DDIO.

bidir_dq_oct_out[] No Output signal from the dynamic termination control path of the BIDIR_DQ I/O pin.

bidir_dq_oe_out[] No Output signal from the output-enable path of the BIDIR_DQ I/O pin.

bidir_dq_output_data_out[]

No Output signal from the output path of the BIDIR_DQ I/O pin.

Table 3–5. ALTDQ_DQS Megafunction Output Ports (Part 2 of 2)

Port Name Required Description



Table 3–6 lists the parameters for the ALTDQ_DQS megafunction.

Table 3–6. ALTDQ_DQS Megafunction Parameters (Part 1 of 8)


DELAY_BUFFER_MODE

String No Specifies whether the variable delay buffers are working in low-frequency mode, or in high-frequency mode. Values are LOW and HIGH. If omitted, the default is LOW.

DELAY_DQS_ENABLE_BY_HALF_CYCLE

String No Specifies whether the output of the DQS_ENABLE_CTRL block is delayed by a half-cycle. Values are TRUE and FALSE. If omitted, the default value is FALSE.

DQ_HALF_RATE_USE_DATAOUTBYPASS

String No Specifies whether the dataout[2..3] outputs of the HALF_RATE_INPUT block can be dynamically set to use the directin input. Values are TRUE and FALSE. If omitted, the default value is FALSE.

DQ_INPUT_REG_ASYNC_MODE

String No Specifies the effect of the input_dq_areset and bidir_dq_areset inputs on the registers in the input path of the INPUT_DQ and BIDIR_DQ I/O pins. Values are NONE, CLEAR, and PRESET. If omitted, the default value is NONE.

DQ_INPUT_REG_CLK_SOURCE

String No Specifies whether the input registers in the INPUT_DQ and BIDIR_DQ I/O pins should be clocked from the core or the dqs_bus port.Values are DQS_BUS and CORE. If omitted, the default value is DQS_BUS.

DQ_INPUT_REG_MODE

String No Values are NONE, FF, and DDIO. If omitted, the default value is NONE.

DQ_INPUT_REG_POWER_UP

String No Specifies the power-up values for the registers in the input path of the INPUT_DQ and BIDIR_DQ I/O pins. Values are LOW and HIGH. If omitted, the default value is LOW.

DQ_INPUT_REG_SYNC_MODE

String No Specifies the effect of the input_dq_sreset and bidir_dq_sreset inputs on the registers in the input path of the INPUT_DQ and BIDIR_DQ I/Os blocks. Values are NONE, CLEAR, and PRESET. If omitted, the default value is NONE.

DQ_INPUT_REG_USE_CLKN

String No Specifies whether the DDIO_IN block on the input path of the INPUT_DQ and BIDIR_DQ I/O pins should be clocked by complementary clocks (dqs_bus and dqsn_bus). Values are TRUE and FALSE. If omitted, the default value is FALSE.


Specifications

DQ_IPA_ADD_INPUT_CYCLE_DELAY

String No Specifies whether to add a 1-cycle delay to the input path for the <IO>_IPA_HIGH and <IO>_IPA_LOW blocks. Values are TRUE, FALSE, and DYNAMIC. If omitted, the default value is FALSE.When set to TRUE, a 1-cycle delay is added to the input path. When set to FALSE, no delay is added. When set to DYNAMIC, the delay can be dynamically controlled with the configuration shift registers.

DQ_IPA_ADD_PHASE_TRANSFER_REG

String No Specifies whether to add a negative edge-triggered register in the data path for the <IO>_IPA_HIGH and <IO>_IPA_LOW blocks.Values are TRUE, FALSE, and DYNAMIC. If omitted, the default value is FALSE. When set to TRUE, a negative edge-triggered register is added in the data path for the clock phase transfer. When set to FALSE, no register is added. When set to DYNAMIC, this can be dynamically controlled through the configuration shift registers. The negative-edge register can be used to guarantee the set-up and hold time for a phase transfer.

DQ_IPA_BYPASS_OUTPUT_REGISTER

String No Specifies whether to bypass the output register for the <IO>_IPA_HIGH and <IO>_IPA_LOW blocks. Values are TRUE and FALSE. If omitted, the default is FALSE.

DQ_IPA_INVERT_PHASE

String No Specifies whether to invert the phase output for the <IO>_IPA_HIGH and <IO>_IPA_LOW blocks. Values are TRUE, FALSE, and DYNAMIC. If omitted, the default is FALSE. When set to TRUE, the phase output is inverted. When set to FALSE, the phase output is not inverted. When set to DYNAMIC, the phase output can be dynamically controlled with the configuration shift registers. An inverter can be used to increase the number of available phases.

DQ_IPA_PHASE_SETTING

Integer No Specifies the phase shift implemented by the delay chain for the <IO>_IPA_HIGH and <IO>_IPA_LOW blocks when the USE_DQ_IPA_PHASECTRLIN parameter is set to FALSE.Values are 0 to 7. If omitted, the default is 0.

DQ_OE_REG_ASYNC_MODE

String No Specifies the effects of the output_dq_areset and bidir_dq_areset inputs on the registers in the output-enable path of the OUTPUT_DQ and BIDIR_DQ I/O pins.Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQ_OE_REG_MODE String No Values are NONE, FF, and DDIO. If omitted, the default is NONE.

DQ_OE_REG_POWER_UP

String No Specifies the power-up values for the registers in the output-enable path of the OUTPUT_DQ and BIDIR_DQ I/O pins. Values are HIGH and LOW. If omitted, the default is LOW.





DQ_OE_REG_SYNC_MODE

String No Specifies the effect of the output_dq_sreset and bidir_dq_sreset inputs on the registers in the output-enable path of the OUTPUT_DQ and BIDIR_DQ I/O pins.Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQ_OUTPUT_REG_ASYNC_MODE

String No Specifies the effect of the output_dq_areset and bidir_dq_areset inputs on the registers in the output path of the OUTPUT_DQ and BIDIR_DQ I/O pins.Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQ_OUTPUT_REG_MODE

String No Values are NONE, FF, and DDIO. If omitted, the default is NONE.

DQ_OUTPUT_REG_POWER_UP

String No Specifies the power-up values for the registers in the output path of the OUTPUT_DQ and BIDIR_DQ I/O pins. Values are HIGH and LOW. If omitted, the default is LOW.

DQ_OUTPUT_REG_SYNC_MODE

String No Specifies the effect of the output_dq_sreset and bidir_dq_sreset inputs on the registers in the output path of the OUTPUT_DQ and BIDIR_DQ I/O pins.Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQS_CTRL_LATCHES_ENABLE

String No Specifies whether the delayctrlin and offsetctrlin input ports are latched for the DQS_DELAY_CHAIN block. Values are TRUE and FALSE. If omitted, the default is FALSE.

DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE

String No Specifies whether the DQS_DELAY_CHAIN block is fed by the dll_delayctrlin input port or the core_delayctrlin input port. Values are CORE and DLL. If omitted, the default is DLL.

DQS_DELAY_CHAIN_PHASE_SETTING

Integer No Specifies the number of DQS delay buffers used in the DQS_DELAY_CHAIN block when the parameter USE_DQS_DELAY_CHAIN_PHASECTRLIN is set to FALSE.

DQS_DQSN_MODE String No Specifies the DQS and DQSn I/O instantiation mode. Values are NONE, DIFFERENTIAL, and COMPLEMENTARY. If omitted, the default is NONE. When set to DIFFERENTIAL, the DQS and DQSn I/O pins are instantiated as a differential pair. When set to COMPLEMENTARY, the DQS and DQSn I/O pins are instantiated as a complementary pair. When set to NONE, only a DQS I/O pin is instantiated.




Specifications

DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REG

String No Specifies whether the negative edge-triggered register is added. Values are TRUE, FALSE, and DYNAMIC. If omitted, the default is FALSE. When set to TRUE, a negative edge-triggered register is added in the data path for the clock-phase transfer. When set to FALSE, no register is added. When set to DYNAMIC, this signal can be dynamically controlled through the configuration shift registers. The negative-edge register can be used to guarantee the set-up and hold time for a phase transfer.

DQS_ENABLE_CTRL_INVERT_PHASE

String No Specifies whether to invert the phase output for theDQS_ENABLE_CTRL block. Values are TRUE, FALSE, and DYNAMIC. If omitted, the default is FALSE.When set to TRUE, the phase output is inverted. When set to FALSE, the phase output is not inverted. When set to DYNAMIC, the phase output can be dynamically controlled with the configuration shift registers.The inverter can be used to increase the number of available phases.

DQS_ENABLE_CTRL_PHASE_SETTING

Integer No Specifies the phase shift implemented by the delay chain for theDQS_ENABLE_CTRL block when the parameter USE_DQS_ENABLE_CTRL_PHASECTRLIN is set to FALSE. The available values are from 0 to 7. The default value is 0.

DQS_INPUT_FREQUENCY

String No Specifies the DQS clock input frequency for the DQS_DELAY_CHAIN block. Check this parameter value to ensure that it falls within the valid range. You can specify a duration by placing a time unit after the value (e.g. 2.5 ns). The value is in floating-point format with no decimal point limit. The settings in the DLL block must match the settings in the DQS_DELAY_CHAIN block. The default value is 0.

DQS_OE_REG_ASYNC_MODE

String No Specifies the effect of the dqs_areset inputs on the registers in the output-enable path of the DQS I/O pin. Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQS_OE_REG_MODE String No Values are NONE, FF, and DDIO. If omitted, the default is NONE.

DQS_OE_REG_POWER_UP

String No Specifies the power-up values for the registers in the output-enable path of the DQS I/O pin. Values are HIGH and LOW. If omitted, the default is LOW.

DQS_OE_REG_SYNC_MODE

String No Specifies the effect of the dqs_sreset input on the registers in the output-enable path of the DQS I/O pin. Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQS_OFFSETCTRL_ENABLE

String No Specifies whether the offsetctrlin input port is used for the DQS_DELAY_CHAIN block. Values are TRUE and FALSE. If omitted, the default is FALSE.





DQS_OUTPUT_REG_ASYNC_MODE

String No Specifies the effect of the dqs_areset input on the registers in the output path of the DQS I/O pin. Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQS_OUTPUT_REG_MODE

String No Values are NONE, FF, and DDIO. If omitted, the default is NONE.

DQS_OUTPUT_REG_POWER_UP

String No Specifies the power-up values for the registers in the output path of the DQS I/O pin. Values are HIGH and LOW. If omitted, the default is LOW.

DQS_OUTPUT_REG_SYNC_MODE

String No Specifies the effect of the dqs_sreset input on the registers in the output path of the DQS I/O pin. Values are NONE, CLEAR, and PRESET. If omitted, the default is NONE.

DQS_PHASE_SHIFT Integer No Specifies the phase shift between the delayed DQS signal and the DQS input signal in units of hundreds of degrees. Values are 0 to 36000. If omitted, the default is 0.

IO_CLOCK_DIVIDER_CLK_SOURCE

String No Specifies whether the clk input of the IO_CLOCK_DIVIDER block is fed from the CORE, DQS_BUS, or INVERTED_DQS_BUS.Values are CORE, DQS_BUS, and INVERTED_DQS_BUS. If omitted, the default is CORE.

IO_CLOCK_DIVIDER_INVERT_PHASE

String No Specifies whether to invert the phase output for the IO_CLOCK_DIVIDER block.Values are TRUE, FALSE, and DYNAMIC. If omitted, the default is FALSE. When set to TRUE, the phase output is inverted. When set to FALSE, the phase output is not inverted. When set to DYNAMIC, the phase output can be dynamically controlled with the configuration shift registers.The inverter can be used to increase the number of available phases.

IO_CLOCK_DIVIDER_PHASE_SETTING

Integer No Specifies the phase shift implemented by the delay chain for the IO_CLOCK_DIVIDER block when the parameter USE_IO_CLOCK_DIVIDER_PHASECTRLIN is set to FALSE.Values are 0 to 7. If omitted, the default is 0.

LEVEL_DQS_ENABLE

String No Specifies whether the LEVEL_DQS_ENABLE parameter is enabled for the DQS_ENABLE_CTRL block.Values are TRUE and FALSE. If omitted, the default is FALSE.

NUMBER_OF_BIDIR_DQ

Integer No Specifies the number of bidirectional DQ I/O pins (nb). Values are 0 to 48. If omitted, the default is 0.

NUMBER_OF_CLK_DIVIDER

Integer No Values are 0 to 8. If omitted, the default is 0.




Specifications

NUMBER_OF_INPUT_DQ

Integer No Specifies the number of input-only DQ I/O pins (ni). Values are 0 to 48. If omitted, the default is 0.

NUMBER_OF_OUTPUT_DQ

Integer No Specifies the number of output-only DQ I/O pins (no). Values are 0 to 48. If omitted, the default is 0.

OCT_REG_MODE String No Values are NONE, FF, and DDIO. If omitted, the default is NONE.

USE_DQ_INPUT_DELAY_CHAIN

String No Specifies whether to instantiate the INPUT_DELAY_CHAIN block on the input path for the BIDIR_DQ and INPUT_DQ I/O pins. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_IPA String No Specifies whether to instantiate the INPUT_PHASE_ALIGNMENT block on the input path for the BIDIR_DQ and INPUT_DQ I/O pins. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_IPA_PHASECTRLIN

String No Specifies whether the phase shift implemented by the delay chain for the INPUT_PHASE_ALIGNMENT blocks is dynamically controlled by configuration shift registers. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_OE_DELAY_CHAIN1

String No Specifies whether to instantiate the OE_DELAY_CHAIN1 block on the output-enable path for BIDIR_DQ and OUTPUT_DQ I/O pins.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_OE_DELAY_CHAIN2


USE_DQ_OE_PATH String No Specifies whether to instantiate the output-enable path for the OUTPUT_DQ I/O pins. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_OUTPUT_DELAY_CHAIN1

String No Specifies whether to instantiate the OE_DELAY_CHAIN1 block on the output path for BIDIR_DQ and OUTPUT_DQ I/O pins.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQ_OUTPUT_DELAY_CHAIN2


USE_DQS String No Specifies whether to instantiate the DQS I/Os. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_DELAY_CHAIN

String No Specifies whether to instantiate the DQS_DELAY_CHAIN block. Values are TRUE and FALSE. If omitted, the default is FALSE.





USE_DQS_DELAY_CHAIN_PHASECTRLIN

String No Specifies whether the phase shift implemented by the delay chain for the DQS_DELAY_CHAIN block is dynamically controlled by configuration shift registers.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_ENABLE String No Specifies whether to instantiate the DQS_ENABLE block. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_ENABLE_CTRL

String No Specifies whether to instantiate the DQS_ENABLE_CTRL block. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_ENABLE_CTRL_PHASECTRLIN

String No Specifies whether the phase shift implemented by the delay chain for the DQS_ENABLE_CTRL block is dynamically controlled by configuration shift registers.Values are TRUE and FALSE. If omitted, the default is TRUE.

USE_DQS_INPUT_DELAY_CHAIN

String No Specifies whether to instantiate the DQS_INPUT_DELAY_CHAIN (D1) block.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_INPUT_PATH

String No Specifies whether to instantiate the DQS input path. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OE_DELAY_CHAIN1

String No Specifies whether to instantiate the DQS_OE_DELAY_CHAIN1 (D5) block. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OE_DELAY_CHAIN2

String No Specifies whether to instantiate the DQS_OE_DELAY_CHAIN2 (D6) block.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OE_PATH String No Specifies whether to instantiate the DQS output-enable path.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OUTPUT_DELAY_CHAIN1

String No Specifies whether to instantiate the DQS_OUTPUT_DELAY_CHAIN1 (D5) block.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OUTPUT_DELAY_CHAIN2

String No Specifies whether to instantiate the DQS_OUTPUT_DELAY_CHAIN2 (D6) block.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQS_OUTPUT_PATH

String No Specifies whether to instantiate the DQS output path. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQSBUSOUT_DELAY_CHAIN

String No Specifies whether to instantiate the DQSBUSOUT_DELAY_CHAIN block. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_DQSENABLE_DELAY_CHAIN

String No Specifies whether to instantiate the DQSENABLE_DELAY_CHAIN block. Values are TRUE and FALSE. If omitted, the default is FALSE.




Specifications

USE_DYNAMIC_OCT String No Specifies whether to instantiate dynamic on-chip termination (OCT) components. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_HALF_RATE String No Specifies whether to instantiate the half-rate components. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_IO_CLOCK_DIVIDER_MASTERIN

String No Specifies whether the ALTDQ_DQS instance is going to be chained (as a slave) to another instance. Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_IO_CLOCK_DIVIDER_PHASECTRLIN

String No Specifies whether the phase shift implemented by the delay chain for the IO_CLOCK_DIVIDER block is dynamically controlled by configuration shift registers.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_OCT_DELAY_CHAIN1

String No Specifies whether to instantiate the <IO>_OCT_DELAY_CHAIN1 (D5 OCT) block.Values are TRUE and FALSE. If omitted, the default is FALSE.

USE_OCT_DELAY_CHAIN2

String No Specifies whether to instantiate the <IO>_OCT_DELAY_CHAIN2 (D6 OCT) block.Values are TRUE and FALSE. If omitted, the default is FALSE.





Table 3–7 shows the offset usage for the ALTDLL megafunction. It shows how the dll_offset_ctrl_a_offset[5..0]and dll_offset_ctrl_b_offset[5..0] inputs are used with the dll_offset_ctrl_a_addnsub and dll_offset_ctrl_b_addnsub inputs, respectively, when the DLL_OFFSET_CTRL_A_USE_OFFSET and DLL_OFFSET_CTRL_B_USE_OFFSET parameters are set to TRUE.

Table 3–7. ALTDLL Offset Usage Example

dll_offset_ctrl_a_addnsub/dll_offset_ctrl_b_addnsub

dll_offset_ctrl_a_offset[5..0]/dll_offset_ctrl_b_offset[5..0]

dll_offset_ctrl_a_offsetctrlout/dll_offset_ctrl_b_offsetctrlout

1 0x06 offsetdelayctrlin[5..0] of each phase offset block + 4




1 0x00 offsetdelayctrlin[5..0] of each phase offset block

0 0x20 offsetdelayctrlin[5..0] of each phase offset blocks – 1

0 0x21 offsetdelayctrlin[5..0] of respective phase offset blocks – 2





Altera Corporation July 2008

Additional Information

Revision History The following table shows the revision history for this user guide.

Referenced Documents

This user guide references the following documents:

■ I/O Buffer (ALTIOBIF) Megafunction User Guide■ AN 433: Constraining and Analyzing Source-Synchronous Interfaces■ DC & Switching Characteristics of Stratix III Devices chapter in

volume 2 of the Stratix III Device Handbook■ External Memory Interfaces in Stratix III Devices chapter in volume 1 of

the Stratix III Device Handbook■ External Memory Interfaces in Stratix IV Devices chapter in volume 1 of

the Stratix IV Device Handbook.■ I/O Buffer (ALTIO) Megafunction User Guide■ Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II

Handbook■ Recommended HDL Coding Styles chapter in volume 1 of the Quartus II

Handbook■ Timing Analysis section in volume 3 of the Quartus II Handbook ■ Simulation section in volume 3 of the Quartus II Handbook■ Synthesis section in volume 1 of the Quartus II Handbook

Date and Document Version Changes Made Summary of Changes

July 2008v1.0

Initial release. —

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