Alireza Haghdoost 1 Hossein Asadi 1 Amirali Baniasadi 2

Alireza Haghdoost1 Hossein Asadi1 Amirali Baniasadi2

1Sharif University of Technology, Tehran, Iran2University of Victoria, Canada

[email protected] [email protected] [email protected]

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System-Level Vulnerability Estimation for Data Caches

PRDC 2010, Dec. 15System-Level Vulnerability Estimation for Data Caches Slide

Goal: Improving accuracy of previously suggested vulnerability factor

Motivation: Read frequency and components error masking

(previously ignored, significantly affect the accuracy )

Our Solution: SVF : System-level vulnerability factor

Key ResultVulnerability estimation accuracy in cache (40%)

This Work: Accurate Vulnerability Modeling for Cache Memory

2

3PRDC 2010, Dec. 15System-Level Vulnerability Estimation for Data Caches Slide

Why Reliability Analysis for Cache ?

• Error rate is expected to increase in cache o 92% of system reboots are initiated by soft-error

occurring in cache [Shazli08]

o Soft-error sources: α particles and neutrons strike • Reliability aware design is necessary

o Having cost-effective design • Accurate vulnerability analysis • Need early design phase vulnerability estimation


Failure in Time

Reliability is quantified by Failure in Time (FIT)

FIT = Raw_FITrate x (TVF x AVF)

• Raw_FITrate = Raw failure rate of devices and circuits

• TVF = Timing Vulnerability Factor

• AVF = Architectural Vulnerability Factor o AVFBP = %0o AVFPC = %100o Other components, AVFcache= ?

(Our focus)


Life Time Analysis

• Typical cache block access

VulBlk = (t2-t1)AVFBlk = (t2-t1)/t3

AVFcache= AVFblk_i /number_blks

VulnerableFill Read Evict

Timet1 t2 t3

Blk


Life Time Analysis

• Advantages:o Early design vulnerability estimationo Less detailed model and single pass simulation

• Disadvantages:o Overestimates AVF

• Up to 260% discrepancy with Fault injection [Wang07]

o Overlooking read frequency & error masking

6


Read Frequency

VulBlk1= t4 - t1

VulBlk1= (t2-t1) + (t3-t2) + (t4-t3)= t4 - t1

AVFBlk1 = AVFBlk2 = (t4-t1)/t5

Vul.

Fill Read1 Evict

t1 t2 t3

Timet4 t5

Blk1

Vul.

Fill Read1 Evict

t1 t2 t3

TimeVul. Vul.

Read2 Read3

Blk2

t4 t5


Error Masking

• Lifetime analysis: VulBlk= (t2-t1)

• Accurate analysis: VulBlk = 0

AND

From Read1

0

0

Fill Read Evict

Timet1 t2 t3

P(Masking)=1

Blki

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Our Solution: SVF

• SVF considers read frequency & error masking • SVF: Percentage of errors that occur in a

component and propagate to system outputs• SVF uses the following:

o P(masking) = IOM o P(propagation) = 1 – IOM


SVF Analysis

SVi =

SVcache= SVi

SVFcache = SVcache / (total_exec).(cache_sizebyte)

Fill Read1 Read2

Timet0 t1 t2 t3

Evict

+ (t1-t0) .IOMcpu.(1-IOMCpu) + (t2-t1).(1-IOMcpu)(t1-t0).(1-IOMcpu)

Byte ith


Detailed SV Analysis

• Erroneous data in cache result failure:o Written-back to main memoryo Read by CPU

• SV different cases :o Case 1 : Clean byte o Case 2 : Dirty byte without writeo Case 3 : Dirty byte with write


SV Scenario on Clean Byte

• Case 1 : Clean byte

SV(F:Rn)= tn.(1-IOMcpu) + SV(F:Rn-1).IOMcpu

Fill Read1 Read2

Timet0 t1 t2 tn

Evict

Byte ith . . .

Readn

tev


SV Different Scenarios

• Case 2 : Dirty byte without write

SV(F:Rn)= twrite-back

Fill Read1 Read2

t0 t1 t2 tn

Write-Back

Byte ith . . .

Readn

twrite-back


SV different scenarios

• Case 3: Dirty block with write

SV(F:Rn)= SV(F:W1)+…+SV(Wk-1:Wk)+ (twrite-back-twk)

Fill Read1 Read2

t0 tr1 tr2 twk

Write-Back

Byte ith . . .

writek

twrite-back

write1

tw1


Methodology

• sim-alpha simulatoro F.I running in functional simulation mode o SVF calculation running in detailed simulation mode

• SPEC2000 benchmarks• Processor configuration

FUs : 4 iALUs, 4 iMultiplier/divider , 1 fpALUs, 1 fpMultiplier/dividerLSQ / RUU / ROB size : 32 / 32 / 32 Instructions

DL1/IL1 : 4-way , 64KB, 3 cycle / 2-way, 64KB, 1 cycle

64 B cache line + 100 cycle Memory access


IOMcpu Estimation

• Fault injection on load instructionso F.I= Fault injection point

• Observe propagation on store instructionso O.P= Observation point

• IOM = #Correct /# Total L2 Cache

DL1 Cache IL1 Cache

Processor Core

F.I O.P


IOMcpu Sensitivity: Number of Runs

gzip crafty mcf applu ammp Average0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8100 runs 400 runs

IOM


Vulnerability Factors for Write-back Data Cache

gzip crafty mcf applu ammp Average0%

10%20%30%40%50%60%70%80%90%

100%SVF AVF

VF


Vulnerability Factors for Write-Through Data Cache


5%

10%

15%

20%SVF AVF

VF


SVFcache Accuracy Improvement vs AVF


10%20%30%40%50%60%70%80%90%

100%WB WT

Accu

racy


Summary

• System-level vulnerability modeling techniqueo Investigates read frequency & erorr masking

• Our resulto Large AVF-SVF discrepancy in storage components

with long storing times. • WT cache

– 40% improved accuracy

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Questions


Backup Slide 1

• F.I Simulation Time for IOMcpu experiments

gzip

vprcra

fty

gcc-166

mcf

parser

bziptw

olfapplu

mesaga

lgel

equakeammp

fma3d

AVG0

5

10

15

20

25

30

100 Runs200 Runs400 Runs

Sim

ula

tion

Tim

e (h

)


Backup Slide 2

• Relax IOM probability for each read access to IOM for total reads

• Reference model is AVF • Validation model based on Fault injection is

under development• TVF cache is 50%• TVF = Timing Vulnerability Factor

oTVFlatch= %50oTVFSRAM=%100


Backup slide 3

SVi = (t1-t0)(1-IOMcpu) +(t2-t1)(1-IOMcpu) +(t3-t2)(1-IOMcpu)

+ (t1-t0)IOMcpu(1-IOMcpu)+(t2-t1)IOMcpu(1-IOMcpu) + (t1-t0)IOM2

cpu(1-IOMcpu)

SVcache = SVi

SVFcache= SVcache/(TT×M)

Fill Read1 Read2 Read3

Timet0 t1 t2 t3 t4

Evict


Backup Slide 4

• SVF for Instruction Scheduler ?SVFIS =

L2 Cache

L1 Data Cache

FP Unit

Instruction Front-End

Integer Unit

Instruction Scheduler

IOMIU

(1-IOMIU)CVFIS x ?

Alireza Haghdoost 1 Hossein Asadi 1 Amirali Baniasadi 2

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