ALICE High Level Trigger
description
Transcript of ALICE High Level Trigger
Torsten Alt - KIP Heidelberg IRTG 28/02/2007 1
ALICE High Level Trigger
TheALICE
High-Level-Trigger
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Overview
The ALICE High-Level-Trigger:• dataflow in the ALICE experiment• trigger systems : L0, L1, L2• TPC – largest datasource• High-Level-Trigger: Tasks & Implementation
The HLT ReadOut-Receiver-Card (H-RORC):• Tasks & Requirements• Implementation
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The ALICE detectorITS : Inner Tracking System TPC : Time Projection Chamber
TRD : Transition Radiation Detector
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Trigger• L0 - 1.2µs : event occured• L1 – 6.5µs : start sampling in the Front-End-Electronics• L2 – 88µs : readout data from the Front-End-Electronics data buffer
L0, L1, L2 look for „valid“ events and trigger the readout!
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High-Level-Trigger : HLTNeeds for a High-Level-Trigger:
• the sub-detectors produce more data than a permanent tape storage system can handle
• Online analysis allows to trigger for rare events i.e. jets
• Events can be „tagged“ to prepare them for later offline analysis
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HLT - Dataflow
TPC DiMuonTRD ITS
HLT
Permanent Storage
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HLT - Dataflow
TPC DiMuonTRD ITS
HLT
Permanent Storage
IN: 16 GB/s
OUT: < 1,2 GB/s
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Picture of the ALICE TPCSector
P.Glaessel – will be replaced by ITS later
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Event in the STAR TPC
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TPC Read-Out Electronics
OROC
IROCrow
pad
• 2 x 18 sectors ( Side A & C)• 6 readout partitions (patch) per sector : 216 patches• ~ 26 rows per patch• ~ 90 pads per row• = 557,568 pads
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HLT Infrastructure for one TPC sector
TPC sector
TR
TDS
Front-End Processors
second sector
HLT - clusterFEP
CFRPH-RORC
BDW
RPH-RORC
BDW
FEP
H-RORC
BDW
H-RORC
BDW
FEP
H-RORC
BDW
CFRPH-RORC
BDW
CF
CFRP
CFRP
CFRP
DAQ
HLT
Online
Display
reconstrcution data flow
display data flow
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Tracking in the HLTRaw Data(Ordering, Zero Suppression)
Cluster Finding(in readout partition)
Tracking(Conformal-Mapping / Track
Follower)
- Data amount+ Computing amount
Can be done in the FPGA
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Clusterfinding 1
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Clusterfinding 2
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HLT in the pit – Counting Room 2 &3
CR 2 & 3 : HLT
ALICEBeampipe
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The HLT Cluster
First Stage :
• Installation will take place from 28.2 to 7.3.
• 80 server with 2 x DualCore Opteron
• Each server will be equipped with 2 RORCs
• Each server will be equipped with a remote control system : CHARM
• 216 incoming DDLs for the TPC • 10 outgoing DDLs to the DAQ
HLT Prototype at KIP
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The H-RORC
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H-RORC Block diagramm
XILINXVIRTEX4
LX40
DDR-SD
DDR-SD
DDR-SD
DDR-SD
TAGNET
USER-FLASH
CFG-FLASH
PLATFORMPROM
XC95144CPLD
CM
C-C
onnector
CM
C-C
onnector
Power 1V2
Power 2V5
Power 1V8
TAGNET
RS-232
ETH-PHY
PCI-66/64 PCI-Power 3V3
Memory Configuration
Serial links
LVDS links
PO
WE
RC
MC
-J11/J22
OSC
OSC
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H-RORC Overview
• H-RORC : HLT Read-Out Receiver Card
• Tasks:– Receiving of the raw detector data– Injecting the data into the main memory of the hosts of the HLT
framework– Online processing of the data in hardware– Sending processed data out of the HLT– Serve as a developing platform for new designs
• Requirements : - Flexible and modulare architecure - Possibility to upgrade to larger FPGAs - Safe update of the firmware
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Clusterfinding in the FPGA 1
370
380
390
400
1015
2025
3035
amp
litu
de
0
50
100
150
• Each datapoint is represented by 4-dimensional vector
(row, pad, time, charge)• Processing can by done for each
row independently: Clusterfinding is a parallel
process • Clusterfinder operates on (pad, time, charge)• Main operations: add, multiply,
compare, store• Main operations can be done in
parallel
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Clusterfinding in the FPGA 2
• 1.stage: CF-DECODER
CF calculate the weighted time, the sequential charge and the
total charge.
• 2.stage: CF-MERGER
The values are compared and merged if they correspond
• 3.stage: DATA-MERGER
The clusters are written to a memory
Pad
Tim
e
Add & Multiply Compare & Add Store
DecoderRAW Merger Data-MergerClusterfinder
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Secure Configuration
XILINXVIRTEX4
LX40
DDR-SD
DDR-SD
DDR-SD
DDR-SD
TAGNET
USER-FLASH
CFG-FLASH
PLATFORMPROM
XC95144CPLD
CM
C-C
onnector
CM
C-C
onnector
Power 1V2
Power 2V5
Power 1V8
TAGNET
RS-232
ETH-PHY
PCI-66/64 PCI-Power 3V3
Memory Configuration
Serial links
LVDS links
PO
WE
RC
MC
-J11/J22
OSC
OSC
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SecureConf
USER 1
USER 2
FLASHCPLD
PCI
Virtex4 FPGA
Write
A user configuration can be written to the FLASH via PCI. Depending on
the size of the FLASH several user configurations can be stored.
Secure Configuration 2
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SecureConf
USER 1
USER 2
FLASHCPLD
PCI
Virtex4 FPGA
The CPLD checks the FLASH for a valid user configuration and the FPGA is then configured with this configuration
Configuration data
CTRL CTRL/STATUS
Secure Configuration 3
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SecureConf
USER 1
USER 2
FLASHCPLD
PCI
Virtex4 FPGA
After configuration a watchdog is enabled inside the CPLD. It needs to be disabled by a defined sequence send via PCI. If anything goes wrong and the watchdog isn`t disabled, it will time out and the FPGA will be reconfigured with the SecureConf.
WATCHDOG
Secure Configuration 4
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SecureConf
USER 1
USER 2
FLASHCPLD
PCI
Virtex4 FPGA
The watchdog has timed out and the FPGA is reconfigured with the SecureConf. The SecureConf contains a design which will always give access to the FLASH via PCI.
Configuration data
CTRL CTRL/STATUS
WATCHDOG
Secure Configuration 5