Alarm Clock Project Final Report

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Transcript of Alarm Clock Project Final Report

Northeastern UniversityDepartment of Electrical and Computer Engineering

ECE U530: HDL and Synthesis Professor: Miriam Leeser

Alarm Clock VHDL Project Digilent Spartan- 3Designed by: Paul Aaron Bohn

Semester: Fall 2006 Date: 12/14/06


ContentIntroduction / Objective Design Description Testing Methodologya. i. ii. b. i. ii.

Page4 5 9

Design Simulation Results Analysis Hardware Testing Results Analysis

Discussion Conclusions and Future Work References Appendices

10 12 13 14


Introduction / ObjectivesThis design is a time keeping digital alarm clock that displays time in hours and minutes. The goal of this design is to implement all of the basic features that one would normally expect to find on a standard digital alarm clock. Features such as standard twelve-hour time, clock/alarm setting functionality, an alarm snooze feature, and an alarm alert indicator.

List of features to be implemented:1. 2. 3. 4. 5. 6. A.M. P.M. time (12 hour roll over) Clock setting functionality Alarm time setting functionality Alarm indicating LED/Sound output figure out how to save design to on board prom special alarm clock feature making use of a random number generator

The design has been implemented on a Spartan-3 FPGA development board. The following diagram shows the physical alarm clock interface.

( Figure 1 )

How to use:A user should be able to set the clock by holding down the clock set button and incrementing the appropriate hour/minute buttons.


Design DescriptionThis design is implemented on a Digilent Spartan-3 development board. The development board contains many inputs and outputs that aid an engineer in learning how to use the Spartan-3 FPGA. The following I/O were used for this design: a onboard 50 MHz crystal oscillator clock, three slide switches, four momentary-contact push button switches, two individual LEDs, and a four-character, seven-segment display. The pin locations of the I/O that an engineer wants to implement must be defined in a constraint file. These pin location values are listed in the Spartan-3 Starter Kit Board User Guide. This user guide can be accessed online at the manufactures website. See the references section for more details. The constraint file for this design is located at the end of the report. See p.10 in the Appendices. Below is the VHDL entity that describes the same design I/O that is in the constraint file. entity clock is port ( clk50in: in std_logic; -- 50 Mhz XTAL btn_in: in std_logic_vector(3 downto 0); -- 4 pushbutton inputs sw_in: in std_logic_vector(7 downto 0); -- 8 switch inputs digit_out: out std_logic_vector(3 downto 0); -- digit drivers led_out: out std_logic_vector(7 downto 0); -- 8 board mounted LEDs seg_out: out std_logic_vector(7 downto 0)); -- segment drivers end clock; A full list of the inputs and output and their purpose is displayed below. This list corresponds with the entity above, the design constraint file located on p.10 in the Appendices and Figure 1.

Inputs:1. Momentary Push Buttons: a. Alarm Set { btn(3) } b. Time Set { btn(2) } c. Hours { btn(1) } d. Minutes { btn(0) } Slide Switch: a. Alarm on/off b. Snooze c. Reset


Outputs:1. 2. 3. 4. 5. 6. Seven-Segment Display AM/PM indicator LED led(7) Alarm on/off indicator led(0) Blinking LED second indicating decimal point Blinking Board mounted second indicated LEDs Alarm Alert ( LED / Sound)


Design Details - How the Clock was Designed:The original code for this design project was written by Xilinx and can be found on the internet (see the reference section for more details). This design is broken up behaviorally in a series of processes. For clarity, I have put meaningful comments above each process and throughout the VHDL program code (see p.1-p.12 in the Appendices). The first task in the design process was to divide down the board mounted clock oscillator to get a clock signal that occurs once every minute. Next, I wrote a 12 hour am/pm time counter algorithm. This counter process is driven by the signal that occurs every sixty seconds. Latter, I rewrote portions of the sevensegment display code so that it would not display a leading zero. I also removed some code that created chasing LED lights on the board. The next design stage was the development of a time setting state machine. I had to figure out how to control this state using the board mounted momentary push buttons. A diagram of the state machine directly follows this page. After the previous step was completed, I created the enable signals to control each process using the state machine. At that time, I developed a minutes counting process that increments the minutes. I made some additional modifications to the code, changing the constraint file and signal naming. After this point, I began to have problems moving the project forward. I tried a myriad of solution paths to none of which worked as intended.

Synthesis:The designs synthesis report accurately displays the hardware I wanted to infer (see p.16-p.18 in the Appendices).


State Machines:



Testing MethodologyHardware Testing:The primary means of testing for this design was using hardware. The design was implemented by synthesizing the VHDL code, then generating a bit file using Xilinx ISE tools. This bit file was downloaded to the Spartin-3 development using Xilinx iMPACT. To complete the program download, I had to power the FPGA board by plugging it into an electrical outlet and hooking it up on end of the JTAG cable to the FPGA board and the other end to the computers parallel port.

ResultsThe design performs as to be expected. The clocks display is fully functional. It is capable of using all four digits of the seven-segment display and the board mounted am/pm LED indicator. The reset switch works and the state machine does change state when the user presses the push buttons (btn2 btn1 and btn0). This is indicated by LED0, LED1, and LED2.

AnalysisOverall, the design performs the basic clock functions well. Sometimes the clock freezes while the user presses the momentary pushbuttons. This might be caused by unintentional signals generated by a noisy digital contact as the switch is pressed. To eliminate this problem, one would have to de-bounce the push buttons in the software.

Design Simulation:The VHDL test bench simulated by using the ModelSim by Xilinx. Software test vectors for the state machine were not required because I did not get far enough in the design process, and the results were already seen in previous hardware tests.

ResultsThis simulation confirmed what the hardware tests were showing. Page 13 in the Appendix is a zoomed out view of the clock wave forms. From this view, the repetitive patterns of each waveform can be observed. Page 14 and 15 offer more detail by displaying the binary values of the signals in different states. One can observe the signals h2,h1,m2,m1 at the expected initial starting value of 12:01, the board mounted LED will be powered by the led_out signal, the digit of seven-segment display is controlled by the digit_out signal, and the corresponding seven-segment decoder output signal seg_out for each digit. One can also observer the alternating decimal point signal dp.

AnalysisThe simulation results did not prove to be as useful as I would have liked. Since the clock device operates in real time, it makes the simulations very long. The more interesting events happen every 60 seconds, which is an extremely long time to run a simulation. This simulation provided waveform data that is located at the end of the report. (see p.13-p.15 in the Appendices).


DiscussionLessons Learned:Much was learned while developing this project. I learned how to implement hardware using VHDL code. This includes learning about implementation of constraint file, input buffers, and output buffers. I learned how to use the development boards display by multiplexing the digit signal to the 7-segment decoder. I learned how to divide down the boards internal clock so I could use it in my design. For the first time, I learned about and used some programming constructs that I was unfamiliar with such as generate and shared variables. While working on this design, I referenced many VHDL sources including websites, course notes, course book, and the Spartan-3 Starter Kit Board User Guide.

What was Difficult:Unfortunately, the design is incomplete. My goal was to use the clock set state machine to activate and deactivate the time_counter, minute_counter, and hour_counter processes using enable signals. (time_en, min_en, hour_en) Each of these processes should be able to modify the hour/minute data depending on whether or not they are enabled. I would like to save and modify this data using the following signals h2, h1, m2, m1. This functionality was never achieved. I had much difficultly implementing the design using this approach. I have been considering many approaches to solve this problem, but most of these solution paths seem to be overly complex. That is why this project is not fully functional. Some of the possible solution paths that I tried are listed below. 1. shared variables 2. Memory (RAM) 3. state Machine 4. registers 5. multiplexers 6. structural description 7. latch flag scheme

What I Would Have Liked to Learn in Class:I would have liked to gain more hardware implementation knowledge. I would find it incredibly fascinating to spend some time on every input and output that the Digilent Spartan-3 development board offers. I am most interested in learning how to use the VGA port, RS-232, and PS2. I would also like to learn how to use the FPGA to emulate various types of hardware an old game console, arcade game, microprocessor, etc. I know where I would like to go with