Alan Hastings-Art of Analog Layout, The (2nd Edition)-Prentice Hall (2005)
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art of analog layouts
Transcript of Alan Hastings-Art of Analog Layout, The (2nd Edition)-Prentice Hall (2005)
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The Art of Analog Layout, Second EditionFront CoverPreface to the Second EditionPreface to the First EditionAcknowledgmentsContents
Chapter 1 Device Physics1.1 Semiconductors1.2 PN Junctions1.3 Bipolar Junction Transistors1.4 MOS Transistors1.5 JFET Transistors1.6 Summary1.7 Exercises
Chapter 2 Semiconductor Fabrication2.1 Silicon Manufacture2.2 Photolithography2.3 Oxide Growth and Removal2.4 Diffusion and Ion Implantation2.5 Silicon Deposition and Etching2.6 Metallization2.7 Assembly2.8 Summary2.9 Exercises
Chapter 3 Representative Processes3.1 Standard Bipolar3.2 Polysilicon-Gate CMOS3.3 Analog BiCMOS3.4 Summary3.5 Exercises
Chapter 4 Failure Mechanisms4.1 Electrical Overstress4.2 Contamination4.3 Surface Effects4.4 Parasitics4.5 Summary4.6 Exercises
Chapter 5 Resistors5.1 Resistivity and Sheet Resistance5.2 Resistor Layout5.3 Resistor Variability5.4 Resistor Parasitics5.5 Comparison of Available Resistors5.6 Adjusting Resistor Values5.7 Summary5.8 Exercises
Chapter 6 Capacitors and Inductors6.1 Capacitance6.2 Inductance6.3 Summary6.4 Exercises
Chapter 7 Matching of Resistors and Capacitors7.1 Measuring Mismatch7.2 Causes of Mismatch7.3 Rules for Device Matching7.4 Summary7.5 Exercises
Chapter 8 Bipolar Transistors8.1 Topics in Bipolar Transistor Operation8.2 Standard Bipolar Small-Signal Transistors8.3 CMOS and BiCMOS Small-Signal Bipolar Transistors8.4 Summary8.5 Exercises
Chapter 9 Applications of Bipolar Transistors9.1 Power Bipolar Transistors9.2 Matching Bipolar Transistors9.3 Rules for Bipolar Transistor Matching9.4 Summary9.5 Exercises
Chapter 10 Diodes10.1 Diodes in Standard Bipolar10.2 Diodes in CMOS and BiCMOS Processes10.3 Matching Diodes10.4 Summary10.5 Exercises
Chapter 11 Field-Effect Transistors11.1 Topics in MOS Transistor Operation11.2 Constructing CMOS Transistors11.3 Floating-Gate Transistors11.4 The JFET Transistor11.5 Summary11.6 Exercises
Chapter 12 Applications of MOS Transistors12.1 Extended-Voltage Transistors12.2 Power MOS Transistors12.3 MOS Transistor Matching12.4 Rules for MOS Transistor Matching12.5 Summary12.6 Exercises
Chapter 13 Special Topics13.1 Merged Devices13.2 Guard Rings13.3 Single-Level Interconnection13.4 Constructing the Padring13.5 ESD Structures13.6 Exercises
Chapter 14 Assembling the Die14.1 Die Planning14.2 FloorPlanning14.3 Top-Level Interconnection14.4 Conclusion14.5 Exercises
Appendix A Table of Acronyms Used in the TextAppendix B The Miller Indices of a Cubic CrystalAppendix C Sample Layout RulesAppendix D Mathematical DerivationsAppendix E Sources of Layout Editor SoftwareIndex
