AIM
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1
AIM
Pream
p 1
Pream
p 2
Pream
p 3
Pream
p 4
F, L, P1 – P4 clocksFrame,Line, &Pixel
CLK 1-4
AD1, GF1
AD2, GF2
AD3, GF3
AD4, GF4
PI-3103A Analog P/S
Clock Driver
DC Bias
CompactPCI Chassis 1
CPU
Clock Generator
Pattern Card (16 Ch.)
Timing & Control
Mux
DAQ
GPIB(PMC)
Preamp controls
‘Scope
Convert, CDS, and Video monitor
DMM
Video Signal
Preamp control, power, and offset
V, I Sense
DUT
CLK In
Bias In
Video Out 1-4
Control signal
Analog signal
Digital/timing signal
Benchtop FPATest System,Detailed View
Muxed data
Data 4
Optical isolation
Master CLKPattern Out
Data 1
Data 2
Data 3
Configuration shown provides 16 channels of pattern generation, 4 channels of programmable clock driver, 4 channels of low-noise DC bias, and 4 channels of A/D and data acquisition with 512 MB of RAM. CPU board runs Windows XP with 2 GB of RAM, dual Gb Ethernet, and standard peripheral ports
8 UnassignedChannels