AgO Analog Circuit Optimization
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Transcript of AgO Analog Circuit Optimization
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What we will talk about
• Company Background
• Challenges in Analog and RF design
© Copyright AgO Inc 20112
• Overview of AnXplorer
• Competitive Differentiation
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Company Background
• Founded in 2007
• Held senior positions at National
• Held senior position in GE and Toshiba
• Awarded 8 Patents and 15 papers -National
© Copyright AgO Inc 20113
• AgO - Advanced Generation Optimization
• Global Sales & Marketing Presence Q4 2011
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Challenges in Analog & RF Design
Achieving design specification
• Meeting or beating performance while minimising cost of implementation
• Managing greater complexity in operating and power saving modes
Maximising yield
• Validating greater numbers of process, voltage and temperature corners
• Efficiently centering design across all PVT corners using Monte Carlo
© Copyright AgO Inc 20114
Respin avoidance
• Analog circuits are responsible for ~ 50% of IC design re-spins
• Re-spins can mean missing market windows and unbudgeted costs
• Managing greater complexity in operating and power saving modes
Design porting
• Moving existing circuit designs to similar technologies
• Re-centering design to meet constraints of new technology
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Classic Analog Design Methodology
• Design methodology has changed little over the years
• Manual, iterative design with many SPICE runs
Define topology
&
resize devices
Design
specification &
constraints
Spice
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Physical layout
& adjust
Extraction
Layout verification
Spice
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Optimization StrategyOptimization Strategy
Feasibility Global Optimization Centering Database
Description• DC Operation• Increase Margin
Description• Single Corner• Meet performance
Description• All Corners• Rapid Size
Description• Conflict• Change Priority
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• Increase Margin• Quick check• Best Design Space
• Meet performance• Monte Carlo• Ready for Center
• Rapid Size• Ready for P&R
• Change Priority• System Analysis
AgO Optimization Strategy
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AnXplorer Goals
• Quickly size W/L a circuit in a given technology
• Explore suitability of different design options
• Robust design over PVT & Monte Carlo
• Support all types of devices
© Copyright AgO Inc 20117
• Explore results using database
• Optimize production yield
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AgO Design Methodology
AnXplorer automates device sizing
Define topology Design
specification &
constraints
Feasibility
Global
© Copyright AgO Inc 20118
Physical layout
& adjust
Extraction
Layout verification
Centering
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Porting of Existing Circuits
Vendor X
Common challenge
• Port existing design in technology X (say
180 nm) to technology Y (in 180 nm)
• Ensure that original design goals are met
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Vendor Y
AnXplorer approach
• Start with original sized circuit
• Define variable ranges for target circuit
• “One click” command
• Optimises and centers with new PVT
corners
Same Node
Porting
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Prioritized Design Objectives
• Most tools support a weight-based prioritisation
for multiple objectives
– Designer is often unsure of relative weights
• AnXplorer supports hierarchical design objectives
– User defines relative priority of different objectives
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– User defines relative priority of different objectives
• AnXplorer achieves important objectives before
optimizing others
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Implicit Objectives
• Imposes implicit objectives on
conditions of devices at DC
operating point
• Customizable objectives
• Detects common sub-circuits and
imposes constraints on their
Examples of sub-
circuits:
• transistors in
saturation
• transistors in linear
region
© Copyright AgO Inc 201111
imposes constraints on their
operating conditions
• Ensures a robust DC operating
point
• Feature only available for MOS
devices
region
• current mirrors
• level shifters
• differential pairs
• voltage reference
• current mirror banks
• etc
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Core Optimization Technology
Early Optimisation tools
• Frequently relied on traditional
convex/gradient methods
• These are known to have difficulty with
multiple local minima
AnXplorer
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AnXplorer
• Based on Evolutionary algorithm
• Capable of finding global minimum in
presence of many local minima
• Successfully optimised tough tests e.g.
Rastrigin’s function
• Optional logarithmic partitioning of
design space
Supports both simulation-based
optimization & equation-based
optimization
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Multiple Local Minimum
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Trade-off Analysis
• Finds multiple design points satisfying design
objectives
• Creates exploration database for post-
optimization analysis
– Database stores all explored design points
© Copyright AgO Inc 201114
– Database stores all explored design points
– Query language or GUI
• Useful for trade-off analysis with conflicting
objectives
• Useful for “what-if” analysis
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Industry Standard Formats
Design objectives Un-sized circuit
Schematics
Definition of
Design variables
Compatible with existing design flows
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AnXplorer
Sized and centered
net list
Exploration
database for
Trade off analysis
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Design Environment
• Spice Simulators
– Cadence Spectre
– Synopsys HSpice
– Mentor Eldo
– Multi-threading support
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– Multi-threading support
• Operating system
– Red Hat Enterprise Linux RHEL 5
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Competitive Differentiation
• One product, four optimization steps
• Robust centering to maximise yield –Monte Carlo
• Implicit objectives for stable DC operation (CMOS)
• Hierarchical design objectives
• User can perform trade-off analysis
© Copyright AgO Inc 201117
• User can perform trade-off analysis
• Industry standard formats and simulators
• Core based on Evolutionary Algorithm
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Analog and RF Optimization New generation Analog & RF Circuit Optimization
Hillol Sarkar
[email protected]@ago-inc.com