Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA...

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Transcript of Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA...

Page 1: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware
Page 2: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Agenda

• Programming FPGAs

• Why Are They Useful?

• NI FPGA Hardware

• Common Applications for FPGAs

• How to Learn More

Page 3: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

FPGA Technology

I/O Blocks

ProgrammableInterconnects

LogicBlocks

Page 4: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

FPGA Logic Implementation

AB

CD

FE

Implementing Logic on FPGA: F = {(A+B)CD} E

LabVIEW FPGA Code

Page 5: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Demo

• Filter

Page 6: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

LabVIEW FPGA Code Abstraction

Counter Analog I/O I/O with DMA

LabVIEW FPGA VHDL ~4000 lines

Page 7: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

LabVIEW FPGA Module

• LabVIEW code is translated to hardware circuitry implemented on the FPGA

• Natural representation of FPGA logic

FPGA

Page 8: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Demo

• Simple I/O

Page 9: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Agenda

• Programming FPGAs

• Why Are They Useful?

• NI FPGA Hardware

• Common Applications for FPGAs

• How to Learn More

Page 10: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Why Are They Useful?

• True Parallelism – Provides parallel tasks and pipelining

• High Reliability – Designs become a custom circuit

• High Determinism – Runs algorithms at deterministic rates down to 25 ns (faster in many cases)

• Reconfigurable – Create new and alter existing task-specific personalities

Page 11: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

AB

CD

FE

True Parallelism

YW X

Z

Page 12: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

High Reliability and Determinism

Hard

ware

Op

erating

System

Driver A

PI

Ap

plicatio

n S

oftw

are

Calcu

lation

Decision Making in Software

~25 ms

Response

Outputs

UUT

Multiple Software Layers

Page 13: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

High Reliability and Determinism

Hard

ware

Op

erating

System

Driver A

PI

Ap

plicatio

n S

oftw

are

Calcu

lation

25 ns*

Response

Outputs

UUT

Decision Making in Hardware

* Faster response for

80 and 120 MHz clocks Highest Reliability

Highest

Determinism

Page 14: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Demo

• AI, AO, Custom Threshold logic

Page 15: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

From LabVIEW to Hardware

Translation Optimization Synthesis Bit Stream

VHDL Generation Analysis

Logic Reduction

Place and Route

Timing Verification

Generation

Download/Run

Page 16: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Agenda

• Programming FPGAs

• What Are FPGAs and Why Are They Useful?

• NI FPGA Hardware

• Common Applications for FPGAs

• How to Learn More

Page 17: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

What Is RIO Technology?

• Use NI LabVIEW to design custom hardware circuitry with off-the-shelf devices

FPGA

Page 18: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

R Series Multifunction RIO

•General Purpose I/O for Measurement and Control

NI CompactRIO

•Industrial Control and Monitoring

NI SingleboardRIO

•Embedded Systems

NI FlexRIO

•Manufacturing Test and Design Validation

Other

•RIO IF Transceiver

•PCIe Framegrabbers

•Compact Vision System

NI LabVIEW FPGA Hardware Targets

Page 19: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Agenda

• Programming FPGAs

• What Are FPGAs and Why Are They Useful?

• NI FPGA Hardware

• Common Applications for FPGAs

• How to Learn More

Page 20: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

Page 21: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

• Coprocessing

Page 22: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

High-Speed Control

About 200 kHz loop rate

Page 23: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

Page 24: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Customize Your DAQ Device

• Custom timing & synchronization

• Multi-rate sampling

• Custom triggering

• Custom counters

• Flexible PWM

• Flexible encoder interface

Page 25: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Custom Triggered Analog Input

Page 26: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

Page 27: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Example – SPI

Digital Communication

Page 28: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

Page 29: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Sensor Simulation and FPGA

• Fully customizable hardware – Many types of sensors

• Parallelism – Many sensors on chip with no interference

• Strict timing requirements – Deterministic or highly realistic

• Onboard processing – Engineering units to sensor signals

Sensor Signals

Page 30: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Common Applications

• High-speed control

• Custom DAQ

• Digital communication protocols

• Sensor simulation

• Onboard processing and data reduction

Page 31: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Onboard Processing and Data Reduction

Output

• DMA preprocessed data

• Streaming from input to output without host involvement

Processing

• Encoding/decoding

• Filtering/averaging

• Modulation/demodulation

• Decimation

• Stream processing

Built-In I/O

• Analog voltages

• Digital communications

• Sensor signals

InputProcess

DMA to Host

Output

Page 32: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Intellectual Property (IP)

FFT

DC/RMS

Waveform Averaging

Digital filtering

Windowing

Resampling

Page 33: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

Math

Signal Processing

Data Manipulation and Transfer

RF and Communications

Digital Protocols

Data Acquisition

Signal Generation

Control

Sensor Simulation

ni.com/ipnet

LabVIEW FPGA IPNet

More than 200 IP cores and examples

Page 34: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

HDL-Based IP in LabVIEW FPGA

• HDL Interface Node

Inline HDL integration

• Component-Level IP Node

Parallel HDL integration

Page 35: Agenda - aeaclubs.org · LabVIEW FPGA Code Abstraction Counter Analog I/O I/O with DMA LabVIEW FPGA VHDL ~4000 lines. LabVIEW FPGA Module •LabVIEW code is translated to hardware

How to Learn More

ni.com/fpga ni.com/training

2 Day LabVIEW FPGA Module Course

Questions?

http://www.ni.com/fpga
http://www.ni.com/fpga
http://www.ni.com/training/

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