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  • Hezi Saar

    April 27, 2017

    IoT DevCon Conference

    Advantages of MIPI Interfaces in IoT Applications

  • 2017 Synopsys, Inc. 2

    Abstract

    In addition to sensors, high-resolution cameras are key enablers of IoT devices. The challenge for IoT designers is to find a solution that delivers low power consumption and high performance, while meeting cost constraints. MIPI CSI-2 is a proven interface in the mobile market, and because of its successful implementation, it is being utilized in new applications like IoT and virtual/augmented reality devices. The new MIPI I3C specification delivers a cost-effective solution that enables multiple sensor connectivity in a simplified architecture. This presentation defines the MIPI CSI-2 and I3C specifications, and describes their implementation, as well as power and performance advantages in IoT SoCs.

  • 2017 Synopsys, Inc. 3

    Agenda

    Implementation of MIPI interfaces in mobile applications and beyond

    Advantages of MIPI CSI-2, DSI, I3C, D-PHY specifications

    Summary

  • 2017 Synopsys, Inc. 4

    MIPI Specifications in New ApplicationsIoT / Wearables, Virtual / Augmented Reality, Automotive

  • 2017 Synopsys, Inc. 5

    From the Edge to the Cloud

    IoT Edge Devices(Smart Devices)

    Aggregation Layers(Hubs/Gateways)

    Remote Processing(Cloud Based)

    Things with sensors & actuators that monitor and

    control

    Connectivity & Interfaces to aggregate the edge data to

    send to the cloud

    Applications to analyze the data and offer cloud services

  • 2017 Synopsys, Inc. 6

    Higher DSP Processing

    + Display

    IoT Devices Getting More Complex

    Battery Life Up to 14 days

    DiscreteVoice, Image, Multiple Sensors

    More capabilities, complex features, and high performance

    Higher level of user and sensor interaction

    Devices with longer battery life

    Ability to turn on/off certain functionalities to reduce power

    Low DSP Processing, No Display

    Battery Life< 7 days

    SingleSensor

  • 2017 Synopsys, Inc. 7

    High End SoC for Always-on IoT

    Applications IoT wearables, smart energy hubs Health / fitness devices Wireless audio (Bluetooth low energy)

    Common system components RTOS or bare metal AA/Coin, lithium Bluetooth, 802.15.4, Zigbee, Wi-Fi

    Unique technology & IP needs Embedded NVM (Flash/MTP) Connectivity, sensors, multimedia and security

    Common Characteristics

    USB 2.0 Host OTG

    w/Charge Detect

    Security

    Radio (WiFi, Bluetooth Smart, 802.15.4)

    Data Fusion IP Subsystem

    ADC

    ARC EMxDProcessor

    I2C/ I3C SPI

    UART

    Timers

    ROM

    GPIOSRAM

    H/WAccel

    NVM (eFlash / MTP)

    MIPICSI2 Host

    MIPIDSI Host

    http://www.zigbee.org/

  • 2017 Synopsys, Inc. 8

    Implementation of Widely-Used MIPI SpecificationsCSI-2, DSI, D-PHY

  • 2017 Synopsys, Inc. 9

    MIPI CSI-2 Over D-PHY Overview

    CSI-2 Device

    DPH Y

    CSI-2 Host

    DPHY

    Clk+

    Clk-

    L0+

    L0-

    Clk+

    Clk-

    L0+

    L0-L1+

    L1-

    L1+

    L1-

    Frame Buffer

    CSI-2 Transmitter

    PacketBuilder

    LaneDistribution

    CCI SlaveSCL

    SDA

    SCL

    SDA

    CCI Master

    CSI-2 Packet

    CSI-2 Packet

    D-PHYHS Burst

    D-PHYHS Burst

    CSI-2 Receiver

    PacketDecoder

    LaneMerger

    CSI-2 Packet

    CSI-2 Packet

    Frame Buffer

    VC CRC

    DT WC ECC

    Payload byte size Data CRC processing

    ECC protecting the header

    Data Format Definition

    Virtual Channel Identification

    Packet Builder

  • 2017 Synopsys, Inc. 10

    MIPI CSI-2 Packets

    Data PFPHFS FEData PFPH

    KEY:SoT Start of Transmission EoT End of Transmission LPS Low Power StatePH Packet Header PF Packet Footer + Filler (if applicable)FS Frame Start FE Frame EndLS Line Start LE Line End

    Frame Start Packet

    Frame End Packet

    First Packet of Data

    Last Packet of Data

    VVALID

    HVALID

    DVALID

    SoT LPSEoT SoT EoTLPSEoT SoTEoT SoT

    Short packets used for frame synchronization

    Image data

    Low power states between

    image lines

    Short packets used for frame synchronization

  • 2017 Synopsys, Inc. 11

    DSI SPacket

    DSI SPacket

    VC CRC

    DT WC ECC

    Payload byte size Data CRC processing

    ECC protecting the header

    Data Format definition

    Virtual Channel Identification

    Packet Builder LONG Packet

    MIPI DSI Over D-PHYDSI Video Mode Example DPI Interface

    DPH Y

    DPHY

    Clk+

    Clk-

    L0+

    L0-

    Clk+

    Clk-

    L0+

    L0-

    L1+

    L1-

    L1+

    L1-

    DSI Transmitter

    PacketBuilder

    Lanedistribution

    DSI Receiver

    PacketDecoder

    Lanemerger

    VSS HSE

    VC

    DT DATA0 ECC

    ECC protecting the short packet

    Data Format definition

    Virtual Channel Identification

    Packet Builder SHORT Packet

    DATA1

    D-PHYHS Burst

    D-PHYHS Burst

    DSI LPacket

    Valid Image Line

    DSI SPacket

    VSS

    DSI SPacket

    HSE D-PHYHS Burst

    D-PHYHS Burst

    D-PHYHS Burst

    D-PHYHS Burst

    DSI LPacket

    Valid Image Line

  • 2017 Synopsys, Inc. 12

    DSI SPacket

    DSI SPacket

    VC CRC

    DT WC ECC

    Payload byte size Data CRC processing

    ECC protecting the header

    Data Format definition

    Virtual Channel Identification

    Packet Builder LONG Packet

    MIPI DSI Over D-PHYDSI Video Mode Example DPI Interface

    DPH Y

    DPHY

    Clk+

    Clk-

    L0+

    L0-

    Clk+

    Clk-

    L0+

    L0-

    L1+

    L1-

    L1+

    L1-

    DSI Transmitter

    PacketBuilder

    Lanedistribution

    DSI Receiver

    PacketDecoder

    Lanemerger

    VSS HSE

    VC

    DT DATA0 ECC

    ECC protecting the short packet

    Data Format definition

    Virtual Channel Identification

    Packet Builder SHORT Packet

    DATA1

    D-PHYHS Burst

    D-PHYHS Burst

    DSI LPacket

    Valid Image Line

    DSI SPacket

    VSS

    DSI SPacket

    HSE D-PHYHS Burst

    D-PHYHS Burst

    D-PHYHS Burst

    D-PHYHS Burst

    DSI LPacket

    Valid Image Line

  • 2017 Synopsys, Inc. 13

    D-PHY Architecture

    Synchronous Forwarded DDR clock link architecture

    One clock and multiple data lanes configuration

    Static/dynamic de-skew supported through calibration

    No encoding overhead Low-power and high-speed modes Primarily targeting camera and display Spread spectrum clocking supported for

    EMI/EMC considerations Large eco-system, proven in millions of

    phones, wearables and cars

    The Popular Physical Layer Used for CSI-2 and DSI Specifications

    Two Data Lane Configuration

  • 2017 Synopsys, Inc. 14

    Complete Camera and Display SolutionSingle-Vendor Solution, Production-Proven, Interoperable

    Secret Sauce

    I2C nowI3C soon

  • 2017 Synopsys, Inc. 15

    Implementation of New MIPI I3C Specification Standardizing Sensor Interface

  • 2017 Synopsys, Inc. 16

    Why I3C?

    Today Smartphones typically have 10-15+ sensors Which require 12-18+ pins

    Different Sensors have different requirements Fingerprint vs Compass

    Typical approach is to connect sensors using a mix of I2C and SPI I2C for lower data rates and SPI for higher

    data ratesMultiple side band signals For interrupts, chip selects, power

    management

    Challenge of Integrating Multiple Sensors with Different Requirements

    This will increase the package size and add complexity which translates into additional costs

    So many I/Os

    required!!

    Images are courtesy of the MIPI Alliance

    No Standard driver for these fragmented interfaces

  • 2017 Synopsys, Inc. 17

    MIPI I3C Standardized Sensor Interface

    It takes the goodness of I2C Two-wire, Simple

    It takes the goodness of SPI Low Power and Speed

    Adds features such as In-band interrupt/command support Dynamic addressing Advanced power management High data rates

    While maintaining support for legacy I2C sensors

    Evolutionary, not revolutionary

    You Can do More with Two Wire communication interface, Clock (SCL) and Data (SDA)

    I/Osreduced to just two!!

    Images are courtesy of the MIPI Alliance

  • 2017 Synopsys, Inc. 18

    I3C Enhanced Capabilities

    Built-in CCC commands allow efficient bus management Each device has its own attributes (speed capabilities, latency

    requirements, etc) Master can use these commands to query and store device attributes Master uses all this information to schedule I3C traffic accordingly and

    broadcast instructions (enter HDR, enable/disable interrupts, etc.) Built-in CCC commands enable advanced use cases

    Secondary master role for sensor hub applications Timing control and time-stamping

    With I3C, user application is not involved in low level protocol details Complexity in managing multiple sensor is significantly reduced with I3C

    I3C is a Sophisticated Protocol As Opposed to I2C

    Image courtesy of MIPI Alliance

  • 2017 Synopsys, Inc. 19

    I3C Transfers

    All I3C communication occurs within a frame. The frame begins with a START, followed by one or more transfers, and a STOP

    Legacy I2C messages remain unchanged Three types SDR messages:

    The address in the address header matches the Slaves dynamic address

    The address in t