Advances in Embedded Traces for 1.5µm RDL on 2.5D Glass Interposers

Fuhan Liu, Chandrasekharan Nair, Venky Sundaram and Rao R. Tummala 3D Systems Packaging Research Center

Georgia Institute of Technology Atlanta, GA USA

Email: fliu@ece.gatech.edu

Abstract

This paper presents the first demonstration of 1.5μm ultra-fine copper trace re-distribution layers (RDL) with embedded trace processes for 2.5D glass interposers. Two approaches described in this paper include: (1) Copper Trace Transfer (CTT) and (2) Photo Trench Embedding (PTE), both of which can be fabricated using existing double-side package substrate process tools on large panels. 2.5D Interposers, interconnecting logic and memory devices at high-bandwidth, require ultra-fine I/O pitch below 40µm. In order to escape route bumps at less than 40μm pitch, the interposer requires RDLs with less than 5μm ultra-fine copper wiring. Organic package substrates, using semi-additive processes (SAP), face a number of challenges in achieving less than 5μm line and space. The two embedded trace process methods in this paper are targeted at extending RDL feature sizes beyond these SAP limits. In the CTT approach, each RDL metal layer is pre-fabricated on a removable carrier and then transferred to a polymer dielectric layer laminated on an interposer core substrate. 1.5 to 5μm Copper traces were plated and successfully transferred onto a polymer laminated glass core. In the PTE approach, a high-resolution photosensitive dry film (TMMF-2014, 14μm thick) and liquid photosensitive dielectric (PN-0371D) films were explored for the RDLs. The initial feasibility of fine line photolithography and trench copper filling processes was investigated. Results showed that the film has a 2μm resolution, with an aspect ratio of seven. The feasibility of resolving 1.2μm line and space patterns was demonstrated in 4.2μm thick liquid photosensitive dielectric material. RDL traces down to 3μm using dry film and 1.5μm using liquid-based film were plated with sputtered Ti-Cu seed layers and trench fill electroplating processes. Both embedded trace approaches demonstrate the potential to scale 1.5-3μm RDL wiring using double-side, large-panel processing for low-cost, high-density interposers. 1. Introduction

High-bandwidth interconnections between logic and memory require high-density RDL wiring at ultra-fine I/O pitch for 2.5D interposers. Silicon interposers with through-silicon-vias (TSVs), fabricated using back end of line (BEOL) wafer processes have demonstrated sub-micron RDL copper traces and 1-2μm via diameters. Xilinx demonstrated the first silicon 2.5D interposer, Virtex-7, using 65nm BEOL process from TSMC with four high-performance FPGA dies interconnected at a bump pitch of 45μm with minimum Cu trace widths of 0.4μm [1]. Although such silicon interposers address the wiring density requirements, they are limited in applications by their high cost and high electrical loss of silicon and ultra-high resistivity of ultra-thin copper metallization. Shinko recently demonstrated a different

approach; an integrated thin film high-density organic package (i-THOP), using ultra-thin and liquid photosensitive polymers [2]. Chemical-mechanical polishing (CMP) was employed to make a smooth top surface layer on the substrate. Microvias were opened using photolithography, and sputtered Ti/Cu was used as the seed layer instead of electroless copper. Fine line and space structures were formed in liquid photo resist using an i-line UV stepper tool. Combining the SAP process with wafer fabrication technology, the i-THOP process demonstrated minimum trace widths of 2µm in building 40μm bump pitch RDLs. In addition, Kyocera demonstrated an organic interposer, Advanced Package X (APX), with 6µm L/S wiring using thin, low-loss advanced dielectric films laminated on low coefficient of thermal expansion (CTE) organic core resulting in 50μm bump pitch using the standard semi-additive processes [3]. The low surface roughness of this advanced thin film dielectric extends the fine line capability of low-cost SAP processes. Table 1 summarizes the status of the state-of-the-art design rules for interposers.

Table 1. RDL Status of the State-of-the-art Interposers

Interposer Technology

Silicon [1]

Integrated Organic [2]

Organic [3]

RDL Lines, μm ≤1 ≥2 ≥6

Bump Pitch, μm 45 40 50

Base Technology Wafer Wafer & Build-up

SAP

Build-up SAP

RDL Metal Cu, Al Cu Cu

RDL metal thickness, μm

≤1 2 5

Semi-additive processes on organic substrates face many

challenges in scaling down to feature sizes below 5μm, due to the surface non-planarity of laminate cores, seed layer etching causing lateral etch of traces and trace reliability issues. Embedded trace approaches were developed to address these SAP challenges, and a team from Amkor, Unimicron and Atotech demonstrated a new method using laser trench, via formation, followed by electroplated copper filling and polishing processes to remove surface copper, resulting in trace widths less than 10μm [4, 5]. Excimer laser ablation was used to form trenches as small as 6-8μm in epoxy (ABF) dry film dielectric materials [6].

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This paper investigates two different embedded trace approaches, copper trace transfer and photo-trench formation, demonstrating the fabrication of 1.5-2µm copper traces by both methods.

2. Semi-Additive Process vs. Embedded Trace Technology Fine trace formation in organic substrates started with the

development of sequential microvia build-up technology based on SAP in the early 1980s at IBM Japan that became commercial in 1987. SAP consists of four major steps: (1) desmear and electroless copper seed layer plating, (2) photolithography, (3) copper electroplating to the required thickness, and (4) copper seed layer etching. The SAP technology allows formation of very small copper traces to form multi-layer build-up wiring, for high I/O bump interconnections on organic cores. The feature sizes were around 50µm in the mid-1990s and 25µm around 2000. The SAP process enabled flip-chip technology to move from small ceramic square substrates to large organic panels, thus resulting in lower cost organic packages at reduced I/O pitch, thereby bringing the industry into a new advanced era of fine pitch area array packages. This technology is currently at 80µm bump pitch with 12-15µm trace widths in high volume manufacturing. Future single chip packages and 2.5D interposers require this line width to scale down to 1-2µm. Challenges associated with the SAP process to achieve 1-2 µm feature sizes include: (1) rough surface due to the desmear of the polymer dielectric to achieve sufficient copper to polymer adhesion, (2) seed layer etching in narrow spaces causing damage to the copper traces, (3) trace delamination due to narrow contact area, (4) palladium residues in ultra-small gaps causing electrical leakage, (5) copper trace electroplating height non-uniformity, and (6) thin dielectric film lamination to achieve planar surfaces for multi-layer RDL. Considering these challenges, there is a perceived limit of 5µm trace width for SAP processes. These challenges are illustrated in Figs.1 and 2 respectively.

The chemical desmear process commonly used to clean the microvia bottom and to roughen the build-up layer surface presents a process challenge for ultra-fine line lithography. Fig. 1 shows the surface roughness on a typical epoxy build-up film, ABF, after desmear and the effects on fine copper patterns. Fig. 2(a) shows the configurations and challenges in conventional SAP processes. The most important challenge is the removal of copper seed layer from fine gaps without damage to the plated copper traces. With decreasing line and space, the seed layer removal is affected by the higher flow resistance for liquid etchant to access the narrow channels. Hence, longer processing times and higher pressures are required, leading to damage of fine copper traces. An added challenge is the weaker adhesion strength of finer traces due to insufficient contact area, decreasing wiring reliability. The final challenge is to achieve a planar surface on the next build-up dielectric layer laminated on the plated copper lines as shown in Fig. 2(b). This non-planar surface will have a negative impact on photolithographic resolution for multi-layer fabrication. On the other hand, embedded copper traces are buried in the build-up dielectric layer, as shown in Fig. 3. As a result, there is no copper seed layer etching in narrow gaps required, and all the features will maintain their shape as

defined by photolithography. Also, the contact area and bonding strength to polymer are increased due to intimate contact in five sides of the copper traces.

Fig. 1. SEM micrograph of 10μm copper traces on a desmeared ABF film with defects caused by rough surface

Fig. 2. (a) SAP Configuration and challenges (seed layer residue, Pd residue, fine traces damage and height non-

uniformity), and (b) Non-Planar Surface on upper build-up layer.

Fig. 3. Embedded Traces Configuration and Advantages: No seed layer etching in narrow gaps, flat surface, multi-site

bonding and fine traces reliable

3. Embedded Trace Process Flows Two different process flows were explored for trace

embedding, (1) Copper Trace Transfer (CTT), and (2) Photo-Trench Embedding (PTE). In the CTT approach, fine copper circuitry was fabricated on a thin peelable copper foil using photolithographic patterning and electroplating, and then transferred by lamination into a build-up polymer dry film previously applied to the substrate. Then the carrier is peeled off and the thin Cu foil is etched away from the surface of the dielectric. In the PTE approach, photo trenches were made

Bonding Forces Planar Surface Fine Traces

Fine Traces Pd Residue

Seed Layer Bonding Force

Non-uniform Height

Fig. 2(a).

Fig. 2(b)

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using photosensitive dielectric films. After the trenches were fabricated, they were filled by copper electroplating, followed by flash etching to remove the excess surface copper.

4. Fine Line Photolithography for Embedded Traces Thee laser embedded trace approaches reported in prior

art use a laser beam to ablate microvias and fine pattern trench structures. This paper uses photolithography processes to make very fine pattern trenches by two different integration flows, thus overcoming the geometry limits of laser patterning. Photolithography has the advantages of making the best quality geometry from sub-micron to hundred micron features, which is required for high-density substrates and interposers. An advanced projection stepper, UX-44101 from Ushio, installed at Georgia Tech PRC was used for fine line photolithography. This tool is equipped with a high power i-line (λ = 365nm) light source and has a 2μm resolution in a 100mm round or 70mm x 70mm large-panel exposure area with 1μm alignment accuracy. The tool has +/- 10μm depth of focus (DOF) to accommodate some amount of substrate warpage and thickness non-uniformity.

It is well known that a smooth and flat surface is essential for fine line lithography. The authors have previously reported 2μm width and space copper wiring on thin advanced dielectric film ZS-100 (Zeon Corporation, Japan) using 7μm thick dry film photoresist [7]. In this paper, 1.5μm copper traces on thin peelable copper foils with liquid photoresist, 2μm wide trenches in 14μm thick photosensitive dry film, and 1.2μm wide trenches in 4.2μm thick liquid photosensitive dielectric film are demonstrated. Fig. 4 shows a group of plated comb structures with 1.5 to 4μm copper traces on a modified thin peelable copper foil.

Fig. 4. Micrograph of plated copper comb structure with 1.5 to 4µm L/S traces on thin copper foil.

5. Approach 1: RDL Copper Trace Transfer (CTT)

The fabrication of the fine RDL wiring using the trace transfer approach consists of two distinct processes: (1) fine RDL trace pre-fabrication and (2) RDL layer integration onto the substrate. 5A. Materials

The materials required for this approach are a thin conductive layer on a removable carrier, a thin thermosetting dielectric build-up film and a dimensionally stable core substrate. In this experiment, a thin copper foil bonded to a

thick carrier copper foil was used. After optimizing the copper foil surface treatment, 1.5 to 5μm wide copper traces were formed on the foil surface as shown in Fig. 4. The build-up film used was ZEONIFTM ZS-100 (ZS-100) with a thickness of 22μm. This advanced film has the advantages of low-loss for high-performance applications and good flow for fine pitch trace embedding. The dielectric constant of ZS-100 is 3.0 (10GHz) and loss tangent is 0.005 (10GHz). The film was laminated on glass or organic core substrates and planarized using a short hot press cycle. The core substrates used were thin glass from Asahi Glass Company (AGC) and Corning Glass. Thin and low CTE FR-4 laminate from Hitachi Chemical and low CTE BT laminate from Mitsubishi Gas Chemical were employed in the studies. 5B Prefabrication of Fine RDL Traces

Each RDL layer can be fabricated with a thin conductive layer on a removable carrier separately, and tested or inspected for fine line yield prior to transfer on to the substrate. The fine traces were fabricated by using fine line lithography and electrolytic copper plating, with the thin copper foil acting as a seed layer for plating. Details of the fine line lithography were discussed in the previous section. Fig. 5(a) shows the process flow of the RDL circuit layer pre-fabrication.

Fig. 5(a). Process flow of pre-fabrication of fine RDL traces on peelable carrier (Only 1 side shown)

5C RDL Circuitry transfer and Integration Once the RDL layers were fabricated, they were

transferred on to both sides of the core substrate simultaneously using a hot press. A thin glass core (100μm AGC Glass or 130μm thick Corning Glass) with ZS-100 build-up layers (22μm thick) on both sides, was used for the transfer. Two redistribution layers, RDL 1 and RDL 2, were pre-fabricated on both sides of the base substrate. The metal layers were embedded into the build-up layers using a hot press at a temperature of 100°C and pressure of 200 psi for 3 minutes. After the hot press process, carrier film was peeled away and ZS-100 dielectric was cured in a convection oven. The final step was a flash etch to remove the thin conductive layer. Fig. 5(b) shows the process flow of the RDL circuit layers transfer and integration.

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Fig. 5(b). Process flow of double-side RDL transferring and integration

5D Results and Discussion Fig. 6 shows a group of 1.5 to 4.5μm copper traces

successfully transferred from a thin copper foil into ZS-100 build-up layer on a 100μm thick AGC glass substrate. Thin ZS-100 film was laminated onto the core by roll lamination at a temperature of 105°C and a speed of 3 inches/min. Fig. 7 shows the cross-section of 3μm wide traces embedded in ZS-100 on 100µm thick EN-A1 glass from AGC. It can be seen that the traces are fully embedded in the build-up dielectric with a flat top surface.

Fig. 6. Micrograph of cross section of embedded 1.5 to 4.5μm L/S in ZS-100 on thin glass substrate by copper trace transfer

(CTT) method.

Fig. 7. Details of Embedded 3µm L/S in ZS-100 on thin glass substrate by CTT method

After integrating RDL 1 and RDL 2 on the base substrate,

subsequent RDLs can be realized by repeating processing steps to form RDL 3 and RDL 4. Fig. 8 shows a top view of

two RDL layers integrated on one side of a BT laminate core. Note that the texts (4μm, 5μm and 6μm) are mirrored.

Fig. 8. Embedded multi-layer RDL showing 4, 5 and 6μm copper traces on top (Note the reversed texts).

6. Approach 2: Photo Trench Embedding (PTE)

The fabrication process for photo trench embedding (PTE) can be divided into two distinct steps: (1) Fine pattern trench formation in a photosensitive dielectric layer and (2) metallization including conductive layer deposition, electrolytic plating and surface copper removing. 6A Materials

The key materials required in the photo trench approach are a high-resolution photosensitive dry film, liquid photosensitive dielectric polymer and core substrate. Dry film TMMF-2014 and liquid PN-0371D provided by Tokyo Ohka Kogyo Co., Ltd (TOK) were used in this study. The TMMF-2014 film has very high resolution and the thickness is 14µm. The core substrate used for initial study was copper clad FR-4 laminate and thin glass with ZS-100 film. The Ushio UX-44101 lithography tool was used for the performance test. The resolution of TMMF-2014 was tested on a Si wafer. Fig. 9 shows 2.0 to 4.5μm comb structures achieved using TMMF-2014 on a silicon wafer core substrate with an aspect ratio of seven to one.

Fig. 9. Feature size of 2 to 4.5μm L/S formed in 14μm thick TMMF-2014 on silicon wafer.

6B Fabrication Processes In the study of TMMF-2014, the clad copper foil on one

side of an FR-4 laminate core was etched away and the photosensitive film was laminated on the bare side of the FR-4 using a vacuum laminator, at 90°C for 30 seconds. In the study of PN-0371D, the liquid dielectric was coated by spin

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coating and followed by soft baking. After patterning by photolithography, the next step was seed layer deposition, and physical vapor deposition (PVD) was used to deposit thin Ti and Cu as the barrier and seed layer respectively. A DC sputtering tool was used to deposit the samples with 25nm thick titanium followed by 200nm thick copper on the surface and trench walls. A special copper fill electrolytic plating process was then used to fill the trenches. A vigorous Ductor spray nozzle system was used for improved plating solution circulation across the surface of the substrate to enhance trench filling. After trenches were filled, the copper on the top surface of TMMF was completely removed. In this studies, the copper was etched away using chemical etchants. The process flow is shown in Fig. 10 and the details are listed in Table 2.

Table 2. Process Flow of TMMF-2014 Lamination

Process Equipment Conditions

Lamination Vacuum Laminator 90°C, 30 sec.

Exposure Ushio UX-44101 270 mj/cm2

Post Bake Oven 100°C, 20 min.

Development Immersion, PGMEA 90 sec.

Cure Oven 200°C, 1 hour

Fig. 10. Process flow of photo trench embedding (PTE) approach.

6C Results and Discussion

Cross sectioning was performed to observe the shape of trenches and the depth of copper filled. Fig. 11 shows the cross section micrographs for 3.5μm L/S (left) and 3.0μm L/S (right) copper traces embedded in TMMF-2014 on bare FR-4

after top surface copper etching. The depth of the copper traces is about 9-10μm for both 3μm and 3.5μm L/S with an aspect ratio of approximately 3. From the results, we can see that it is feasible to create 2μm L/S fine trace structures by using photolithography on photosensitive film TMMF-2014. Ti/Cu sputtering is capable to achieve a depth of 9-10μm in 3μm wide trenches. Thus, an aspect ratio of 3 is feasible. Liquid photosensitive polymer has better resolution. Fig. 12 shows SEM image of 1.5 to 5.0μm L/S trenches formed in 4.2μm thick PN-0371D on ZS-100 dielectric film laminated thin glass substrate. Cross section of embedded 1.5 to 5.0μm copper traces in PN-0371D on ZS-100 laminated thin glass substrate is shown in Fig. 13.

.

Fig. 11. Micrograph of embedded 3.5μm (left) and 3.0μm (right) L/S copper traces in TMMF on Bare FR-4 by PTE. The

depth of the traces is 9-10μm.

Fig. 12. SEM photograph of 1.5 to 5μm L/S trenches formed in liquid photosensitive layer PN-0371D (4.2μm thick) on ZS-

100 advanced dielectric film on glass substrate.

Fig. 13. Cross section of embedded 1.5 to 5.0μm L/S traces in PN-0371D on ZS-100 on thin glass with copper thickness of

4μm by photo trench embedding (PTE) method.

Substrate Top Cu Foil Etched Core Substrate

Photosensitive Film Lamination Substrate

Photolithography Substrate

Seed Layer Coating Substrate

Substrate Trench Cu Filling by Electrolytic Plating

Top Cu Removing Substrate

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7. Conclusions With the continuous demands of increased signal

bandwidth and I/O density, ultra-high density multi-layer RDL is required on interposers and package substrates. Silicon interposer provides the wiring density needs but is a high-cost solution due to required BEOL processing. The build-up SAP is a low-cost solution but currently faces major challenges with limits of 5μm L/S. Embedded trace technology provides a new solution to overcome the challenges of SAP. Two novel low-cost embedded traces approaches were demonstrated to address the wiring density limits of semi-additive process. Embedded 1.5 to 5μm copper traces were demonstrated by using copper trace transfer method. Embedded 3μm wide 9 to 10μm thick copper traces in TMMF-2014 dry film and 1.5 to 5μm L/S traces in 4.2μm PN-0371D liquid film were demonstrated by using photo trench embedding method. The advanced embedded trace technologies break through the limits of build-up SAP. Both the copper traces (CTT) and photo trench embedding (PTE) approaches provide new ways for the fabrication of low-cost 1.5 to 2μm RDL interposers.

Acknowledgements The authors would like to acknowledge the PRC’s

consortium members for their supports, especially acknowledge Tokyo Ohka Kogyo Co., Ltd (TOK) for their high-resolution photosensitive film TMMF-2014 and liquid PN-0371D and Ushio Inc. for the advanced projection MASK Aligner UX-44101. Thanks to Mitsui Mining & Smelting Co., for thin copper foils and AtoTech for advanced copper plating and filling; Tim Fleck, an intern from Dresden University for process development; and Parthasarathi Chakraborti for PVD seed sputtering.

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