Advanced Technology of Plasma Dicing for GaAs VCSEL

© Panasonic Smart Factory Solutions Co., Ltd 2021

Advanced Technology of

Plasma Dicing for GaAs VCSEL

9th Nov 2021

Panasonic Connect Europe GmbH, Germany※1

Panasonic Smart Factory Solutions Co., Ltd., Japan※2

James Weber※1, Shogo Okita※2

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Panasonic Avionics Corporation

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Business Domain

Panasonic Smart Factory Solutions Co., Ltd.

Process Innovation Center

Process Automation Business Division

IndustrialSolutions

Organization of Panasonic Process Automation Business

China Northeast asia

US

Panasonic Corporation

Related Company・Panasonic Connect Europe

etc.

Appliances

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Front-End

Electronic Device Processing Equipment of Panasonic SFS

Surface Mounter for Compound Semiconductordevices

Back-End

Die / Flip-chip bonding for Compound Semiconductor chip

Dry Etching for various Compound Semiconductor applications

Plasma Dicing technology applied to the Compound Semiconductor industry.

✔✔

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Machine/Specification Applicable Device

High Precision Multi-Spiral-Coil ICP ProcessGaAs High Frequency / Optronics (Recess, GaAs MESA, VIA) GaN High Frequency / Optronics (Recess, MESA, Isolation)InP Optronics (MESA, VIA)SiC Power (MESA, Trench, Etch. Back)Passivation (SiO2, SiN, BCB, PI, etc.)

High Density Plasma ProcessSi / SiC VIA for GaN HEMTAll SiC trench process(SiO2 mask, Trench, Etch-Back)

Batch Processing for Mass-productionLED (PSS, GaN MESA, GaN Isolation, SiO2, etc.)

SiO2 mask etching, etc.

SiC Trench

GaAs VIA

SiC total flow

Panasonic can provide various Dry Etching applications for Compound Semiconductors based on GaAs, GaN, InP, SiC, etc.

Panasonic Provides Dry Etching Solutions for Compound Semiconductors

APX300-SMSC-ICP

APX300-SBM-ICP

APX300Batchprocessing

Φ6” x 3Φ4” x 7

SiC VIA Si VIA

PSS GaN MESA GaN Isolation SiO2 Mask

GaAs MESA

InP MESA

GaN

GaN Isolation

BCB

SiC MESA

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VCSEL Structure VCSEL Market Trends

VCSEL Dicing IssuesDebris

Chipping

VCSEL: Vertical Cavity Surface Emitting LASER

･Densely-packed laser 2D-array structure・Low power operation due to small size･Applications :

・Laser Mouse, Laser Printer・Optical Communication・Interconnection between data centers・Sensing (ToF, Gesture, etc.)

Market Expansion

Conventional Methods(Blade or Laser Dicing)・Physical & heat damage・Dust on chip・Wide dicing street width & kerf margin

・Damage Free・No dust & no debris・Improve yield per wafer by reducing dicing street width & kerf margin

Dust

Panasonic provides a new dicing technology “Plasma Dicing” to replace conventional

dicing methods

Trends of VCSEL Market and Technology

Active Layer

n-GaAs/AlAs DBR

p-GaAs/AlAs DBR

n-GaAs Substrate

n-Electrode

p-Electrode

Insulator

Light Out

Application Expansion

Market Requirements

x 5

2018 2024

$738M $3,775M

http://www.yole.fr/VCSEL_MarketUpdate.aspx#.XdJkCuawd51

Defense Aerospace

MobileConsumer

Medical

IndustrialTelecom andinfrastructure

AutomotiveTransportation

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Fully processed wafers, mounted on metal ring frame and tape, without damage.

・Dicing of thin & fragile wafers w/o damage・Possible to reduce the kerf margin・Possible to dice with low device damage

Principles and Benefits of Plasma Dicing

Plasma

Ring Frame Tape

Wafer is transferred into the Process Chamber

Wafer is transferred from the Process Chamber

Wafer is mounted on metal ring frame and tape

Fully singulated waferby Plasma Dicing

■Outline of Plasma Dicing ■ Benefits of Plasma Dicing

1. Damage Free

2. Increase Yield &Production, Low CoO

3. Particle Free

4. Variant Chip Shape & Layout

Plasma Dicing by chemical reactance of gas

・Parallel processing・Narrow dicing width and kerf margin by elimination cracks increases the amount of dies

・Clean chemical etching process・No mechanical dust, debris, vibrations, water pressure etc.・Potential to reduce inspections

・Flexible die shapes and non-orthogonal layouts

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・APX300-DM has optimized elemental technologies for Plasma Dicing

1. Enhanced ICP Plasma Source : High density and uniform plasma2. Plasma Dicing ESC Electrode & Dicing Ring Cover・Patented Panasonic design enables the Plasma Dicing process to be performed on wafers mounted on ring frame with tape

・Strong chucking force and cooling enables almost all dicing (DC) tape to be used. ・Eliminates exposure of the tape and frame to plasma

3. Etching performance・Process chamber that can use both Fluorine-based and Chlorine-based etching

gasses. Compound Semiconductor etching is possible・Multi layer dicing (SiO2, SiN, DAF & Si) is possible・Si etching rate up to 35μm/min. ≦±3%

Plasma Dicer APX300-DM (Dicer Module)

・Configuration of APX300-DM Process Chamber

Dicing Ring Cover

Panasonic OriginalESC Electrode

Plasma

Enhanced-ICPPatented

Patented

Patented

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Cross-section of WaferProcess

Mask Patterning Plasma Dicing Mask Stripping

Photo-lithography Plasma Dicing Ashing / Chemical Cleaning

Mask

GaAs GaAs

Plasma Dicing

Panasonic proposes the use of Photo-lithography and Plasma Dicing integration for small chip VCSEL dicing.

Panasonic’s VCSEL Plasma Dicing Process Flow

GaAs

Coat Exposure Development

Mask Patterning・Photo-lithography patterning on metal ring frame and tape・Narrower street width (≦30μm) and narrower kerf margin

Plasma Dicing・No physical/heat damage to chip・Etching depth of GaAs ≧100μm, incl. Au backside metal sputtering 200-500nmMask Stripping・Remove mask without any residue

-VCSEL Plasma Dicing Requirements

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Panasonic can perform photo-lithography on metal frame and tape. Coating, Alignment & Exposure and Development with ring frame and tape enable this technology to be applied on wafers from Φ2” GaAs to Φ8” GaAs

→ Panasonic tested photo-lithographySample : Novolak Photo Resist (PR), GaAs substrate, Polyolefin Dicing tape, Φ200mm ring frame

Photo-lithography on GaAs wafers on Metal Ring Frame and Tape

Thick PRHigh Aspect Ratio (A/R) Exposure

PR thickness =14.6μmDicing width = 6.3μmA/R = 2.3

PR Mask on VCSEL

PR thickness = 15.7μmDicing width = 14.8μmCompletely covered on VCSEL device structure

No tape damage

Thin GaAs substrateΦ2” up to Φ8”

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VCSEL device layerVCSEL device layer


・Possible to use Chlorine-based gas etching process without DC tape damage・High GaAs etching rate and high PR selectivity was achieved・Vertical etching profile was achieved

Results of GaAs Plasma Dicing

→ Panasonic tested the photo-lithography and Plasma DicingSample : Novolak PR, GaAs substrate, Polyolefin Dicing tape, Φ200mm metal ring frameCondition : 1. Lithography processing (coat → pre-bake → exposure → develop) to wafer with ring frame → 2. Plasma Dicing

GaAs Etching Rate (E/R) ≧ 8.0μm/min.E/R Uniformity @ 6inch ≦ ±3.0％GaAs:PR Selectivity ≧ 22Etching profile VerticalTape damage None

No tape damageduring Chlorine-based gas Plasma Dicing

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Test coupon

Dummy


Etching Depth : 127μmDicing Width : 16μmA/R : 8Profile : Vertical

Very high A/R process can be applied to GaAs VCSEL Plasma Dicing.

Results of GaAs Plasma Dicing: “Etching Profile Control”

・Etching profile can be controlled

85 deg. ~ 90 deg.

■Profile Control

Vertical TaperBowing

■High A/R GaAs Dicing

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Before PR Stripping(after Plasma Dicing)

・Able to remove PR Mask without DC tape damage･Before PR stripping, some swelling of the material was evident, however not only

the PR, but also the swelling could be removed after PR stripping.・No debris and no dust was achieved.

Results of Mask Stripping and Full-cut of GaAs Plasma Dicing

→ We tested the total integration of photo-lithography, Plasma Dicing and Chemical Washing.Sample : Novolak PR, GaAs substrate, Polyolefin Dicing tape, Φ200mm metal ring frameCondition : 1. Lithography processing (coat → pre-bake- → exposure → develop) of the wafer with ring frame →

2. Plasma Dicing → Chemical washing

After PR Stripping ■Completely singulated 6” GaAs substrate GaAs thickness : 100μm

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Panasonic can propose Plasma Dicing technology to singulate GaAs VCSEL wafers.

Panasonic developed and demonstrated suitable process flows for GaAs VCSEL wafers : Photo-lithography + Plasma Dicing.

1. Photo-lithography : Panasonic can perform photo-lithography with metal ring and tape.

2. Plasma Dicing :・APX300-DM can use Chlorine-based gas for GaAs dicing, and can be applied toGaAs Plasma Dicing.・Panasonic developed a GaAs Plasma Dicing process and achieved high A/R GaAs Dicing

3. Panasonic showed that PR can be removed by chemical solutions for wafers on metal ring frame and tape.

Conclusions and Acknowledgments

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Panasonic already has a well developed plasma dicing process:

Up to 200µm GaAs thickness200nm to 500nm gold thicknessDicing speed 4.5 to 8µm/min

Panasonic continues to improve Plasma Dicing technology for GaAs and intend to expand its application to other compound semiconductors such as GaN, etc.

Acknowledgments:Thank you very much to EV Group for their cooperation, and to several other chemical manufacturers.

Conclusions and Acknowledgments

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1. Damage Free2. Increase Yield &Production, Low CoO

3. Particle Free4. Variant Chip Shape & Layout


For more information in Europe, please contact:

Panasonic Connect Europe GmbHCaroline-Herschel-Strasse 100, 85521 Ottobrunn, Germany(Near Munich)

[email protected]

Contact Information

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mailto:[email protected]

Advanced Technology of Plasma Dicing for GaAs VCSEL

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